Add storage space for FPU registers in context switching
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4143 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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@ -44,6 +44,8 @@
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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@ -72,10 +74,84 @@
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#ifdef CONFIG_NUTTX_KERNEL
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# define REG_EXC_RETURN (10) /* EXC_RETURN */
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# define SW_XCPT_REGS (11)
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# define SW_INT_REGS (11)
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#else
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# define SW_XCPT_REGS (10)
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# define SW_INT_REGS (10)
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#endif
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/* If the MCU supports a floating point unit, then it will be necessary
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* to save the state of the FPU status register and data registers on
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* each context switch. These registers are not saved during interrupt
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* level processing, however. So, as a consequence, floating point
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* operations may NOT be performed in interrupt handlers.
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*
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* The FPU provides an extension register file containing 32 single-
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* precision registers. These can be viewed as:
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*
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* - Sixteen 64-bit doubleword registers, D0-D15
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* - Thirty-two 32-bit single-word registers, S0-S31
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* S<2n> maps to the least significant half of D<n>
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* S<2n+1> maps to the most significant half of D<n>.
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*/
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#ifdef CONFIG_ARCH_FPU
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# define REG_D0 (SW_INT_REGS+0) /* D0 */
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# define REG_S0 (SW_INT_REGS+0) /* S0 */
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# define REG_S1 (SW_INT_REGS+1) /* S1 */
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# define REG_D1 (SW_INT_REGS+2) /* D1 */
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# define REG_S2 (SW_INT_REGS+2) /* S2 */
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# define REG_S3 (SW_INT_REGS+3) /* S3 */
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# define REG_D2 (SW_INT_REGS+4) /* D2 */
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# define REG_S4 (SW_INT_REGS+4) /* S4 */
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# define REG_S5 (SW_INT_REGS+5) /* S5 */
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# define REG_D3 (SW_INT_REGS+6) /* D3 */
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# define REG_S6 (SW_INT_REGS+6) /* S6 */
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# define REG_S7 (SW_INT_REGS+7) /* S7 */
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# define REG_D4 (SW_INT_REGS+8) /* D4 */
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# define REG_S8 (SW_INT_REGS+8) /* S8 */
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# define REG_S9 (SW_INT_REGS+9) /* S9 */
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# define REG_D5 (SW_INT_REGS+10) /* D5 */
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# define REG_S10 (SW_INT_REGS+10) /* S10 */
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# define REG_S11 (SW_INT_REGS+11) /* S11 */
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# define REG_D6 (SW_INT_REGS+12) /* D6 */
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# define REG_S12 (SW_INT_REGS+12) /* S12 */
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# define REG_S13 (SW_INT_REGS+13) /* S13 */
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# define REG_D7 (SW_INT_REGS+14) /* D7 */
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# define REG_S14 (SW_INT_REGS+14) /* S14 */
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# define REG_S15 (SW_INT_REGS+15) /* S15 */
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# define REG_D8 (SW_INT_REGS+16) /* D8 */
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# define REG_S16 (SW_INT_REGS+16) /* S16 */
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# define REG_S17 (SW_INT_REGS+17) /* S17 */
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# define REG_D9 (SW_INT_REGS+18) /* D9 */
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# define REG_S18 (SW_INT_REGS+18) /* S18 */
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# define REG_S19 (SW_INT_REGS+19) /* S19 */
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# define REG_D10 (SW_INT_REGS+20) /* D10 */
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# define REG_S20 (SW_INT_REGS+20) /* S20 */
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# define REG_S21 (SW_INT_REGS+21) /* S21 */
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# define REG_D11 (SW_INT_REGS+22) /* D11 */
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# define REG_S22 (SW_INT_REGS+22) /* S22 */
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# define REG_S23 (SW_INT_REGS+23) /* S23 */
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# define REG_D12 (SW_INT_REGS+24) /* D12 */
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# define REG_S24 (SW_INT_REGS+24) /* S24 */
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# define REG_S25 (SW_INT_REGS+25) /* S25 */
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# define REG_D13 (SW_INT_REGS+26) /* D13 */
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# define REG_S26 (SW_INT_REGS+26) /* S26 */
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# define REG_S27 (SW_INT_REGS+27) /* S27 */
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# define REG_D14 (SW_INT_REGS+28) /* D14 */
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# define REG_S28 (SW_INT_REGS+28) /* S28 */
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# define REG_S29 (SW_INT_REGS+29) /* S29 */
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# define REG_D15 (SW_INT_REGS+30) /* D15 */
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# define REG_S30 (SW_INT_REGS+30) /* S30 */
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# define REG_S31 (SW_INT_REGS+31) /* S31 */
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# DEFINE REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */
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# define SW_FPU_REGS (33)
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#else
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# define SW_FPU_REGS (0)
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#endif
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/* The total number of registers saved by software */
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#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS)
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#define SW_XCPT_SIZE (4 * SW_XCPT_REGS)
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/* On entry into an IRQ, the hardware automatically saves the following
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@ -204,6 +204,11 @@
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#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
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#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
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#define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */
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#define NVIC_FPCCR_OFFSET 0x0f34 /* Floating-point Context Control Register */
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#define NVIC_FPCAR_OFFSET 0x0f38 /* Floating-point Context Address Register */
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#define NVIC_FPDSCR_OFFSET 0x0f3c /* Floating-point Default Status Control Register */
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#define NVIC_MVFR0_OFFSET 0x0f40 /* Media and VFP Feature Register 0 */
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#define NVIC_MVFR1_OFFSET 0x0f44 /* Media and VFP Feature Register 1 */
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#define NVIC_PID4_OFFSET 0x0fd0 /* Peripheral identification register (PID4) */
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#define NVIC_PID5_OFFSET 0x0fd4 /* Peripheral identification register (PID5) */
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#define NVIC_PID6_OFFSET 0x0fd8 /* Peripheral identification register (PID6) */
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