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Add peripheral support for the STM32 F2 family 

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4471 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo 2012-03-10 00:02:11 +00:00
parent f178ff6906
commit 58914ea2ee
34 changed files with 251 additions and 226 deletions
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8
nuttx/arch/arm/src/stm32/chip.h
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@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32/chip.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -55,11 +55,15 @@
# include "chip/stm32f103re_pinmap.h"
# elif defined(CONFIG_ARCH_CHIP_STM32F103VCT6)
# include "chip/stm32f103vc_pinmap.h"
# elif defined(CONFIG_ARCH_CHIP_STM32F105VBT7)
# include "chip/stm32f105vb_pinmap.h"
# elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# include "chip/stm32f107vc_pinmap.h"
# else
# error "Unsupported STM32F10XXX chip"
# endif
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_pinmap.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_pinmap.h"
#else
@ -73,6 +77,8 @@
#ifdef CONFIG_ARMV7M_CMNVECTOR
# if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_vectors.h"
# else

20
nuttx/arch/arm/src/stm32/chip/stm32_adc.h
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@ -71,7 +71,7 @@
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
@ -148,7 +148,7 @@
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
#endif
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
# define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
@ -163,7 +163,7 @@
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
#endif
@ -202,7 +202,7 @@
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ACD_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
# define ACD_CR1_RES_MASK (3 << ACD_CR1_RES_SHIFT)
# define ACD_CR1_RES_12BIT (0 << ACD_CR1_RES_SHIFT) /* 15 ADCCLK clyes */
@ -224,14 +224,14 @@
#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
#endif
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* Bits 12-15: Reserved */
# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
# define ADC_CR2_JEXTSEL_MASK (15 << ADC_CR2_JEXTSEL_SHIFT)
@ -321,7 +321,7 @@
/* ADC sample time register 1 */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_SMPR_3 0 /* 000: 3 cycles */
# define ADC_SMPR_15 1 /* 001: 15 cycles */
@ -361,7 +361,7 @@
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#endif
@ -477,7 +477,7 @@
/* Common status register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
@ -503,7 +503,7 @@
/* Common control register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */

12
nuttx/arch/arm/src/stm32/chip/stm32_can.h
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@ -61,7 +61,7 @@
/* Number of filters depends on silicon */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CAN_NFILTERS 28
#else
# define CAN_NFILTERS 14
@ -445,14 +445,14 @@
/* CAN filter master register */
#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */
# define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT)
#endif
/* CAN filter mode register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */
# define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT)
#else
@ -462,7 +462,7 @@
/* CAN filter scale register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */
# define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT)
#else
@ -472,7 +472,7 @@
/* CAN filter FIFO assignment register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */
# define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT)
#else
@ -482,7 +482,7 @@
/* CAN filter activation register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
# define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#else

6
nuttx/arch/arm/src/stm32/chip/stm32_dbgmcu.h
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@ -52,7 +52,7 @@
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
#endif
@ -99,7 +99,7 @@
/* Debug MCU APB1 freeze register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
@ -121,7 +121,7 @@
/* Debug MCU APB2 freeze register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */
# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */
# define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */

4
nuttx/arch/arm/src/stm32/chip/stm32_exti.h
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@ -55,7 +55,7 @@
# define STM32_NEXTI 19
# define STM32_EXTI_MASK 0x0007ffff
# endif
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_NEXTI 23
# define STM32_EXTI_MASK 0x007fffff
#endif
@ -91,7 +91,7 @@
# ifdef CONFIG_STM32_CONNECTIVITYLINE
# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */
# endif
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */

16
nuttx/arch/arm/src/stm32/chip/stm32_flash.h
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@ -39,7 +39,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#if defined(CONFIG_STM32_LOWDENSITY)
# define STM32_FLASH_NPAGES 32
# define STM32_FLASH_PAGESIZE 1024
@ -52,7 +52,7 @@
#elif defined(CONFIG_STM32_HIGHDENSITY)
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_PAGESIZE (128*1024)
#endif
@ -71,7 +71,7 @@
# define STM32_FLASH_AR_OFFSET 0x0014
# define STM32_FLASH_OBR_OFFSET 0x001c
# define STM32_FLASH_WRPR_OFFSET 0x0020
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_FLASH_OPTCR_OFFSET 0x0014
#endif
@ -87,7 +87,7 @@
# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
#endif
@ -109,7 +109,7 @@
#if defined(CONFIG_STM32_STM32F10XX)
# define FLASH_ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
# define FLASH_ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
@ -123,7 +123,7 @@
# define FLASH_SR_PGERR (1 << 2) /* Programming Error */
# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
# define FLASH_SR_EOP (1 << 5) /* End of Operation */
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
@ -146,7 +146,7 @@
# define FLASH_CR_OPTWRE (1 << 9) /* Option Bytes Write Enable */
# define FLASH_CR_ERRIE (1 << 10) /* Error Interrupt Enable */
# define FLASH_CR_EOPIE (1 << 12) /* End of Program Interrupt Enable */
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */
@ -166,7 +166,7 @@
/* Flash Option Control Register (OPTCR) */
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
# define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
# define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */

2
nuttx/arch/arm/src/stm32/chip/stm32_memorymap.h
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@ -45,6 +45,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_memorymap.h"
#else

6
nuttx/arch/arm/src/stm32/chip/stm32_pwr.h
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@ -78,7 +78,7 @@
# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
# define PWR_CR_VOS (1 << 14) /* Bit 14: Regulator voltage scaling output selection */
#endif
@ -89,13 +89,13 @@
#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */
#endif
#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */
# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
#endif

16
nuttx/arch/arm/src/stm32/chip/stm32_spi.h
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@ -59,7 +59,7 @@
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
#endif
@ -84,7 +84,7 @@
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
# ifdef CONFIG_STM32_STM32F40XX
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@ -98,7 +98,7 @@
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
# ifdef CONFIG_STM32_STM32F40XX
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@ -138,7 +138,7 @@
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_SPI3_FRF (1 << 4) /* Bit 4: Frame format */
#endif
@ -151,7 +151,7 @@
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */
# define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */
#endif
@ -161,13 +161,13 @@
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_SR_TIFRFE (1 << 8) /* Bit 8: TI frame format error */
#endif
/* I2S configuration register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
# define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
@ -194,7 +194,7 @@
/* I2S prescaler register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */

4
nuttx/arch/arm/src/stm32/chip/stm32_syscfg.h
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@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/****************************************************************************************************
* Pre-processor Definitions
@ -147,5 +147,5 @@
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
#endif /* CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_SYSCFG_H */

22
nuttx/arch/arm/src/stm32/chip/stm32_tim.h
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@ -56,7 +56,7 @@
/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
* 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
* For the STM32F10xx all timers are 16-bit.
* For the STM32F40xx, TIM2 and 5 are 32-bit
* For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit
*/
#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
@ -78,7 +78,7 @@
#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */
#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11 option register */
#endif
@ -157,7 +157,7 @@
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
* For the STM32F10xx all timers are 16-bit.
* For the STM32F40xx, TIM2 and 5 are 32-bit
* For the STM32F2xx and STM32F40xx, TIM2 and 5 are 32-bit
*/
#if STM32_NGTIM > 0
@ -179,7 +179,7 @@
# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
# ifdef CONFIG_STM32_STM32F40XX
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
# endif
#endif
@ -245,7 +245,7 @@
# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
# ifdef CONFIG_STM32_STM32F40XX
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET)
# endif
#endif
@ -658,7 +658,7 @@
#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
#endif
@ -941,28 +941,28 @@
#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity */
#endif
#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */
#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity (TIM2-5,9&12 only) */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (TIM2-5,9&12 only) */
#endif
#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */
#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (TIM2-5 only) */
#endif
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity (TIM2-5 only) */
#endif
@ -975,7 +975,7 @@
/* Timer 2/5 option register */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */
# define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT)
# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */

4
nuttx/arch/arm/src/stm32/chip/stm32_uart.h
View File

@ -165,7 +165,7 @@
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#endif
@ -203,7 +203,7 @@
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
#endif

4
nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
View File

@ -1,8 +1,8 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

2
nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
View File

@ -50,7 +50,7 @@
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 84 interrupt table entries for I/O interrupts. */
/* Reserve 82 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 82

113
nuttx/arch/arm/src/stm32/stm32_adc.c
View File

@ -4,7 +4,7 @@
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Diego Sanchez <dsanchez@nx-engineering.com>
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -33,11 +33,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdio.h>
@ -97,7 +97,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of one ADC block */
struct stm32_dev_s
@ -144,7 +144,7 @@ static int adc12_interrupt(int irq, void *context);
#if defined(CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3)
static int adc3_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static int adc123_interrupt(int irq, void *context);
#endif
@ -162,7 +162,7 @@ static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
static int adc_timinit(FAR struct stm32_dev_s *priv);
#endif
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
#endif
@ -409,7 +409,7 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg)
avdbg(" DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
}
#endif
}
#endif
@ -427,22 +427,22 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg)
* Returned Value:
*
****************************************************************************/
#ifdef ADC_HAVE_TIMER
static void adc_timstart(struct stm32_dev_s *priv, bool enable)
{
uint16_t regval;
avdbg("enable: %d\n", enable);
regval = tim_getreg(priv, STM32_GTIM_CR1_OFFSET);
if (enable)
{
/* Start the counter */
regval |= ATIM_CR1_CEN;
}
else
{
/* Disable the counter */
@ -564,7 +564,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
}
timclk = priv->pclck / prescaler;
reload = timclk / priv->freq;
if (reload < 1)
{
@ -591,7 +591,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
* direction bit(DIR).
* ATIM_CR1_DIR: 0: count up, 1: count down
*/
cr1 &= ~(ATIM_CR1_DIR | ATIM_CR1_CMS_MASK);
cr1 |= ATIM_CR1_EDGE;
@ -604,7 +604,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler-1);
tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
/* Clear the advanced timers repitition counter in TIM1 */
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
@ -621,7 +621,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
ocmode1 = 0;
ocmode2 = 0;
switch (priv->trigger)
{
case 0: /* TimerX CC1 event */
@ -699,7 +699,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
/* Set the event TRGO */
egr = GTIM_EGR_TG;
/* Set the duty cycle by writing to the CCR register for this channel */
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1));
@ -710,20 +710,19 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
adbg("No such trigger: %d\n", priv->trigger);
return -EINVAL;
}
/* Disable the Channel by resetting the CCxE Bit in the CCER register */
ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET);
ccer &= ~ccenable;
tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
/* Fetch the CR2, CCMR1, and CCMR2 register (already have cr1 and ccer) */
cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET);
ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
/* Reset the Output Compare Mode Bits and set the select output compare mode */
ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE |
@ -732,11 +731,11 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE);
ccmr1 |= ocmode1;
ccmr2 |= ocmode2;
/* Reset the output polarity level of all channels (selects high polarity)*/
ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P);
/* Enable the output state of the selected channel (only) */
ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | ATIM_CCER_CC4E);
@ -747,7 +746,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
/* Reset output N polarity level, output N state, output compre state,
* output compare N idle state.
*/
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP);
#else
@ -760,7 +759,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 | ATIM_CR2_OIS2N |
ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | ATIM_CR2_OIS4);
}
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
else
{
ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | GTIM_CCER_CC4NP);
@ -781,8 +780,8 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
cr1 |= GTIM_CR1_ARPE;
tim_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
/* Enable the timer counter
* All but the CEN bit with the default config in CR1
/* Enable the timer counter
* All but the CEN bit with the default config in CR1
*/
adc_timstart(priv, true);
@ -807,7 +806,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static void adc_startconv(struct stm32_dev_s *priv, bool enable)
{
uint32_t regval;
@ -835,7 +834,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
* Name: adc_rccreset
*
* Description:
* Deinitializes the ADCx peripheral registers to their default
* Deinitializes the ADCx peripheral registers to their default
* reset values. It could set all the ADCs configured.
*
* Input Parameters:
@ -915,7 +914,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset)
* Name: adc_enable
*
* Description : Enables or disables the specified ADC peripheral.
* Also, starts a conversion when the ADC is not
* Also, starts a conversion when the ADC is not
* triggered by timers
*
* Input Parameters:
@ -977,7 +976,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Release ADC from reset state */
adc_rccreset(priv, false);
/* Initialize the ADC data structures */
/* Initialize the watchdog high threshold register */
@ -1009,33 +1008,33 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* ADC CR1 Configuration */
regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET);
/* Set mode configuration (Independent mode) */
#ifdef CONFIG_STM32_STM32F10XX
regval |= ADC_CR1_IND;
#endif
/* Initialize the Analog watchdog enable */
regval |= ADC_CR1_AWDEN;
regval |= (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT);
/* Enable interrupt flags */
regval |= ADC_CR1_ALLINTS;
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* Enable or disable Overrun interrupt */
regval &= ~ADC_CR1_OVRIE;
/* Set the resolution of the conversion */
regval |= ACD_CR1_RES_12BIT;
#endif
adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
/* ADC CR2 Configuration */
@ -1045,17 +1044,17 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Clear CONT, continuous mode disable */
regval &= ~ADC_CR2_CONT;
/* Set ALIGN (Right = 0) */
regval &= ~ADC_CR2_ALIGN;
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* External trigger enable for regular channels */
regval |= ACD_CR2_EXTEN_RISING;
#endif
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
/* Configuration of the channel conversions */
@ -1079,10 +1078,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
{
regval |= (uint32_t)priv->chanlist[i] << offset;
}
/* ADC CCR configuration */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
regval = getreg32(STM32_ADC_CCR);
regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK |
ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
@ -1100,7 +1099,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Set the channel index of the first conversion */
priv->current = 0;
/* Set ADON to wake up the ADC from Power Down state. */
adc_enable(priv, true);
@ -1133,7 +1132,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
avdbg("CCR: 0x%08x\n",
getreg32(STM32_ADC_CCR));
#endif
@ -1271,14 +1270,14 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
int32_t value;
/* Identifies the interruption AWD, OVR or EOC */
adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET);
if ((adcsr & ADC_SR_AWD) != 0)
{
alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
}
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
if ((adcsr & ADC_SR_OVR) != 0)
{
alldbg("WARNING: Overrun has ocurred!\n");
@ -1289,8 +1288,8 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
if ((adcsr & ADC_SR_EOC) != 0)
{
/* Read the converted value and clear EOC bit
* (It is cleared by reading the ADC_DR)
/* Read the converted value and clear EOC bit
* (It is cleared by reading the ADC_DR)
*/
value = adc_getreg(priv, STM32_ADC_DR_OFFSET);
@ -1412,7 +1411,7 @@ static int adc3_interrupt(int irq, void *context)
*
****************************************************************************/
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static int adc123_interrupt(int irq, void *context)
{
uint32_t regval;
@ -1471,7 +1470,7 @@ static int adc123_interrupt(int irq, void *context)
* Initialize the ADC.
*
* The logic is, save nchannels : # of channels (conversions) in ADC_SQR1_L
* Then, take the chanlist array and store it in the SQR Regs,
* Then, take the chanlist array and store it in the SQR Regs,
* chanlist[0] -> ADC_SQR3_SQ1
* chanlist[1] -> ADC_SQR3_SQ2
* ...
@ -1494,7 +1493,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
{
FAR struct adc_dev_s *dev;
FAR struct stm32_dev_s *priv;
avdbg("intf: %d nchannels: %d\n", intf, nchannels);
#ifdef CONFIG_STM32_ADC1
@ -1529,10 +1528,10 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
/* Configure the selected ADC */
priv = dev->ad_priv;
DEBUGASSERT(nchannels <= ADC_MAX_SAMPLES);
priv->nchannels = nchannels;
memcpy(priv->chanlist, chanlist, nchannels);
return dev;
}

4
nuttx/arch/arm/src/stm32/stm32_adc.h
View File

@ -52,7 +52,7 @@
************************************************************************************/
/* Configuration ********************************************************************/
/* Timer devices may be used for different purposes. One special purpose is to
* control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then
* control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then
* CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is intended
* to be used for that purpose.
*/
@ -86,7 +86,7 @@
# undef CONFIG_STM32_TIM4_ADC3
#endif
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_ADC
# undef CONFIG_STM32_TIM5_ADC1

8
nuttx/arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/up_allocateheap.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -116,7 +116,7 @@
# undef CONFIG_STM32_TCMEXCLUDE
# define CONFIG_STM32_TCMEXCLUDE 1
/* All members of the STM32F40xxx family have 192Kb in three banks:
/* All members of the STM32F20xxx and STM32F40xxx families have 192Kb in three banks:
*
* 1) 112Kb of System SRAM beginning at address 0x2000:0000
* 2) 16Kb of System SRAM beginning at address 0x2001:c000
@ -133,7 +133,7 @@
* In addition, external FSMC SRAM may be available.
*/
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX
/* Set the end of system SRAM */
# define SRAM1_END 0x20020000
@ -298,7 +298,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
/* Add the STM32F40xxx TCM SRAM heap region. */
/* Add the STM32F20xxx/STM32F40xxx TCM SRAM heap region. */
#ifndef CONFIG_STM32_TCMEXCLUDE
mm_addregion((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START);

20
nuttx/arch/arm/src/stm32/stm32_dac.c
View File

@ -91,7 +91,7 @@
# undef CONFIG_STM32_DAC1_DMA
# undef CONFIG_STM32_DAC2_DMA
# endif
# elif defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# ifndef CONFIG_STM32_DMA1
# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1"
# undef CONFIG_STM32_DAC1_DMA
@ -144,7 +144,7 @@
# define DAC_DMA 2
# define DAC1_DMA_CHAN DMACHAN_DAC_CHAN1
# define DAC2_DMA_CHAN DMACHAN_DAC_CHAN2
# elif defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define HAVE_DMA 1
# define DAC_DMA 1
# define DAC1_DMA_CHAN DMAMAP_DAC1
@ -328,7 +328,7 @@ static void tim_putreg(struct stm32_chan_s *chan, int offset, uint32_t value);
/* Interrupt handler */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static int dac_interrupt(int irq, void *context);
#endif
@ -402,7 +402,7 @@ static struct dac_dev_s g_dac2dev =
};
#endif
static struct stm32_dac_s g_dacblock;
static struct stm32_dac_s g_dacblock;
/****************************************************************************
* Private Functions
@ -465,7 +465,7 @@ static void tim_putreg(struct stm32_chan_s *chan, int offset, uint32_t value)
*
****************************************************************************/
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static int dac_interrupt(int irq, void *context)
{
#warning "Missing logic"
@ -598,7 +598,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
* - Peripheral Burst: single
*/
#warning "Missing logic"
/* Enable DMA */
#warning "Missing logic"
@ -659,7 +659,7 @@ static int dac_timinit(struct stm32_chan_s *chan)
/* Selection TRGO selection: update */
#warning "Missing Logic"
/* Enable the counter */
#warning "Missing Logic"
}
@ -707,7 +707,7 @@ static int dac_chaninit(struct stm32_chan_s *chan)
* - Enable the output buffer.
*/
#warning "Missing logic"
/* Determine if DMA is supported by this channel */
#ifdef HAVE_DMA
@ -803,7 +803,7 @@ static int dac_blockinit(void)
*
* Assumptions:
* 1. Clock to the DAC block has enabled,
* 2. Board-specific logic has already configured
* 2. Board-specific logic has already configured
*
****************************************************************************/
@ -812,7 +812,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
FAR struct dac_dev_s *dev;
FAR struct stm32_chan_s *chan;
int ret;
#ifdef CONFIG_STM32_DAC1
if (intf == 1)
{

2
nuttx/arch/arm/src/stm32/stm32_dma.c
View File

@ -73,6 +73,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "stm32f10xxx_dma.c"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "stm32f20xxx_dma.c"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "stm32f40xxx_dma.c"
#endif

16
nuttx/arch/arm/src/stm32/stm32_dma.h
View File

@ -49,6 +49,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_dma.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_dma.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_dma.h"
#else
@ -60,12 +62,12 @@
*/
#if defined(CONFIG_STM32_STM32F10XX)
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
#elif defined(CONFIG_STM32_STM32F40XX)
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */
# define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */
# define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */
@ -110,7 +112,7 @@ struct stm32_dmaregs_s
uint32_t cpar;
uint32_t cmar;
};
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
struct stm32_dmaregs_s
{
uint32_t lisr;

4
nuttx/arch/arm/src/stm32/stm32_dumpgpio.c
View File

@ -63,7 +63,7 @@ static const char g_portchar[STM32_NGPIO_PORTS] =
#elif STM32_NGPIO_PORTS > 8
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
#elif STM32_NGPIO_PORTS > 7
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
#elif STM32_NGPIO_PORTS > 6
'A', 'B', 'C', 'D', 'E', 'F', 'G'
#elif STM32_NGPIO_PORTS > 5
@ -143,7 +143,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
lldbg(" GPIO%c not enabled: APB2ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_APB2ENR));
}
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",

2
nuttx/arch/arm/src/stm32/stm32_fsmc.h
View File

@ -163,7 +163,7 @@
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#endif
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */

66
nuttx/arch/arm/src/stm32/stm32_gpio.c
View File

@ -54,7 +54,7 @@
#include "chip.h"
#include "stm32_gpio.h"
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32_syscfg.h"
#endif
@ -112,8 +112,8 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
* Description:
*
* Based on configuration within the .config file, this function will
* remaps positions of alternative functions.
*
* remaps positions of alternative functions.
*
****************************************************************************/
static inline void stm32_gpioremap(void)
@ -189,7 +189,7 @@ static inline void stm32_gpioremap(void)
val |= AFIO_MAPR_PD01;
#endif
putreg32(val, STM32_AFIO_MAPR);
putreg32(val, STM32_AFIO_MAPR);
#endif
}
@ -202,8 +202,8 @@ static inline void stm32_gpioremap(void)
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
*
* Assumptions:
@ -224,15 +224,15 @@ void stm32_gpioinit(void)
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
*
* Returns:
* OK on success
* A negated errono valu on invalid port, or when pin is locked as ALT
* function.
*
*
* To-Do: Auto Power Enable
****************************************************************************/
@ -253,7 +253,7 @@ int stm32_configgpio(uint32_t cfgset)
unsigned int modecnf;
irqstate_t flags;
bool input;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
@ -261,7 +261,7 @@ int stm32_configgpio(uint32_t cfgset)
{
return -EINVAL;
}
/* Get the port base address */
base = g_gpiobase[port];
@ -281,7 +281,7 @@ int stm32_configgpio(uint32_t cfgset)
cr = base + STM32_GPIO_CRH_OFFSET;
pos = pin - 8;
}
/* Input or output? */
input = ((cfgset & GPIO_INPUT) != 0);
@ -293,9 +293,9 @@ int stm32_configgpio(uint32_t cfgset)
flags = irqsave();
/* Decode the mode and configuration */
regval = getreg32(cr);
if (input)
{
/* Input.. force mode = INPUT */
@ -305,12 +305,12 @@ int stm32_configgpio(uint32_t cfgset)
else
{
/* Output or alternate function */
modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
}
modecnf |= ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) << 2;
/* Set the port configuration register */
regval &= ~(GPIO_CR_MODECNF_MASK(pos));
@ -349,7 +349,7 @@ int stm32_configgpio(uint32_t cfgset)
shift = AFIO_EXTICR_EXTI_SHIFT(pin);
regval &= ~(AFIO_EXTICR_PORT_MASK << shift);
regval |= (((uint32_t)port) << shift);
putreg32(regval, regaddr);
}
@ -361,7 +361,7 @@ int stm32_configgpio(uint32_t cfgset)
return OK;
}
}
/* If it is an output... set the pin to the correct initial state.
* If it is pull-down or pull up, then we need to set the ODR
* appropriately for that function.
@ -390,10 +390,10 @@ int stm32_configgpio(uint32_t cfgset)
#endif
/****************************************************************************
* Name: stm32_configgpio (for the STM32F40xxx family)
* Name: stm32_configgpio (for the STM2F20xxx and STM32F40xxx family)
****************************************************************************/
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
int stm32_configgpio(uint32_t cfgset)
{
uintptr_t base;
@ -405,7 +405,7 @@ int stm32_configgpio(uint32_t cfgset)
unsigned int pos;
unsigned int pinmode;
irqstate_t flags;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
@ -413,7 +413,7 @@ int stm32_configgpio(uint32_t cfgset)
{
return -EINVAL;
}
/* Get the port base address */
base = g_gpiobase[port];
@ -595,7 +595,7 @@ int stm32_configgpio(uint32_t cfgset)
shift = SYSCFG_EXTICR_EXTI_SHIFT(pin);
regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
regval |= (((uint32_t)port) << shift);
putreg32(regval, regaddr);
}
@ -611,12 +611,12 @@ int stm32_configgpio(uint32_t cfgset)
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
* into default HiZ state (and possibly mark it's unused) and unlock it whether
* it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
*
*
* This is a safety function and prevents hardware from schocks, as unexpected
* write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
* Returns:
* OK on success
* A negated errno value on invalid port
@ -627,16 +627,16 @@ int stm32_configgpio(uint32_t cfgset)
int stm32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
#if defined(CONFIG_STM32_STM32F10XX)
cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
cfgset |= GPIO_INPUT | GPIO_FLOAT;
#else
# error "Unsupported STM32 chip"
#endif
/* To-Do: Mark its unuse for automatic power saving options */
return stm32_configgpio(cfgset);
@ -655,7 +655,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
uint32_t base;
#if defined(CONFIG_STM32_STM32F10XX)
uint32_t offset;
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
uint32_t bit;
#endif
unsigned int port;
@ -687,7 +687,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
putreg32((1 << pin), base + offset);
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
if (value)
{

34
nuttx/arch/arm/src/stm32/stm32_gpio.h
View File

@ -55,6 +55,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_gpio.h"
#else
@ -74,7 +76,7 @@ extern "C" {
#else
#define EXTERN extern
#endif
/* Bit-encoded input to stm32_configgpio() */
#if defined(CONFIG_STM32_STM32F10XX)
@ -204,7 +206,7 @@ extern "C" {
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured
* by software in several modes:
@ -401,14 +403,14 @@ extern const uint32_t g_gpiobase[STM32_NGPIO_PORTS];
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
*
* Returns:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
*
************************************************************************************/
EXTERN int stm32_configgpio(uint32_t cfgset);
@ -420,12 +422,12 @@ EXTERN int stm32_configgpio(uint32_t cfgset);
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
* into default HiZ state (and possibly mark it's unused) and unlock it whether
* it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
*
*
* This is a safety function and prevents hardware from schocks, as unexpected
* write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
* operate in PWM mode could produce excessive on-board currents and trigger
* over-current/alarm function.
*
* Returns:
* OK on success
* ERROR on invalid port
@ -459,21 +461,21 @@ EXTERN bool stm32_gpioread(uint32_t pinset);
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
*
* Parameters:
* - pinset: gpio pin configuration
* - rising/falling edge: enables
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returns:
*
* Returns:
* The previous value of the interrupt handler function pointer. This value may,
* for example, be used to restore the previous handler when multiple handlers are
* used.
*
************************************************************************************/
EXTERN xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
EXTERN xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func);
/************************************************************************************
@ -495,8 +497,8 @@ EXTERN int stm32_dumpgpio(uint32_t pinset, const char *msg);
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
************************************************************************************/

6
nuttx/arch/arm/src/stm32/stm32_lowputc.c
View File

@ -257,7 +257,7 @@
*
* mantissa = usartdiv32 / 32/
*
* Eg. usartdiv32=1250, mantissa = 39
* Eg. usartdiv32=1250, mantissa = 39
*/
#define STM32_MANTISSA (STM32_USARTDIV32 >> 5)
@ -268,7 +268,7 @@
*
* Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625)
*/
#define STM32_FRACTION ((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
/* And, finally, the BRR value is: */
@ -450,7 +450,7 @@ void stm32_lowsetup(void)
#endif
#endif /* HAVE_UART */
}
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
void stm32_lowsetup(void)
{
#if defined(HAVE_UART)

28
nuttx/arch/arm/src/stm32/stm32_pwm.c
View File

@ -610,7 +610,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
{
prescaler = 65536;
}
timclk = priv->pclk / prescaler;
reload = timclk / info->frequency;
@ -642,10 +642,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
*/
cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET);
/* Disable the timer until we get it configured */
cr1 &= ~GTIM_CR1_CEN;
cr1 &= ~GTIM_CR1_CEN;
/* Set the counter mode for the advanced timers (1,8) and most general
* purpose timers (all 2-5, but not 9-14), i.e., all but TIMTYPE_COUNTUP16
@ -664,7 +664,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
* direction bit(DIR).
* GTIM_CR1_DIR: 0: count up, 1: count down
*/
cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK);
cr1 |= GTIM_CR1_EDGE;
}
@ -696,7 +696,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
if (info->count > 0)
{
/* Save the remining count and the number of counts that will have
* elapsed on the first interrupt.
* elapsed on the first interrupt.
*/
/* If the first interrupt occurs at the end end of the first
@ -851,7 +851,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
/* Reset the output polarity level of all channels (selects high polarity)*/
ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P);
/* Enable the output state of the selected channel (only) */
ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | ATIM_CCER_CC4E);
@ -868,7 +868,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
* output compare N idle state.
*/
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP);
#else
@ -890,11 +890,11 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
bdtr |= ATIM_BDTR_MOE;
pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
}
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
else
#endif
#endif
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
{
ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | GTIM_CCER_CC4NP);
}
@ -928,7 +928,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
/* Enable the timer */
cr1 |= GTIM_CR1_CEN;
cr1 |= GTIM_CR1_CEN;
pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
/* And enable timer interrupts at the NVIC */
@ -1006,7 +1006,7 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
else
{
/* Decrement the count of pulses remaining using the number of
* pulses generated since the last interrupt.
* pulses generated since the last interrupt.
*/
priv->count -= priv->prev;
@ -1027,7 +1027,7 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
pwmllvdbg("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
regval, priv->prev, priv->curr, priv->count);
return OK;
return OK;
}
#endif
@ -1063,7 +1063,7 @@ static int pwm_tim8interrupt(int irq, void *context)
* Name: pwm_pulsecount
*
* Description:
* Pick an optimal pulse count to program the RCR.
* Pick an optimal pulse count to program the RCR.
*
* Input parameters:
* count - The total count remaining
@ -1173,7 +1173,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"

8
nuttx/arch/arm/src/stm32/stm32_qencoder.c
View File

@ -113,7 +113,7 @@
/* On the F4 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */
@ -185,7 +185,7 @@ struct stm32_qeconfig_s
#ifdef HAVE_MIXEDWIDTH_TIMERS
uint8_t width; /* Timer width (16- or 32-bits) */
#endif
#ifdef CONFIG_STM32_STM32F40XX
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */
uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */
#else
@ -1042,7 +1042,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"
@ -1056,7 +1056,7 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"

4
nuttx/arch/arm/src/stm32/stm32_rcc.c
View File

@ -78,6 +78,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_rcc.c"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_rcc.c"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_rcc.c"
#else
@ -99,7 +101,7 @@ void stm32_clockconfig(void)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions in board.h */

8
nuttx/arch/arm/src/stm32/stm32_rcc.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_rcc.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
*
* Redistribution and use in source and binary forms, with or without
@ -47,6 +47,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_rcc.h"
#endif
@ -102,7 +104,7 @@ extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static inline void stm32_mco1config(uint32_t source, uint32_t div)
{
uint32_t regval;
@ -134,7 +136,7 @@ static inline void stm32_mco1config(uint32_t source, uint32_t div)
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
static inline void stm32_mco2config(uint32_t source, uint32_t div)
{
uint32_t regval;

2
nuttx/arch/arm/src/stm32/stm32_rtc.c
View File

@ -73,6 +73,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "stm32f10xxx_rtc.c"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "stm32f20xxx_rtc.c"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "stm32f40xxx_rtc.c"
#endif

2
nuttx/arch/arm/src/stm32/stm32_rtc.h
View File

@ -46,6 +46,8 @@
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_rtc.h"
# include "chip/stm32_bkp.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_rtc.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_rtc.h"
#endif

8
nuttx/arch/arm/src/stm32/stm32_sdio.c
View File

@ -118,7 +118,7 @@
# ifndef CONFIG_SDIO_DMAPRIO
# if defined(CONFIG_STM32_STM32F10XX)
# define CONFIG_SDIO_DMAPRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define CONFIG_SDIO_DMAPRIO DMA_SCR_PRIVERYHI
# else
# error "Unknown STM32 DMA"
@ -128,7 +128,7 @@
# if (CONFIG_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SDIO_DMAPRIO"
# endif
# elif defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if (CONFIG_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SDIO_DMAPRIO"
# endif
@ -190,7 +190,7 @@
/* STM32 F4 stream configuration register (SCR) settings. */
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
@ -210,7 +210,7 @@
#if defined(CONFIG_STM32_STM32F10XX)
# define SDIO_DMACHAN DMACHAN_SDIO
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SDIO_DMACHAN DMAMAP_SDIO
#else
# error "Unknown STM32 DMA"

4
nuttx/arch/arm/src/stm32/stm32_syscfg.h
View File

@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_STM32_STM32F40XX
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32_syscfg.h"
/****************************************************************************************************
@ -100,5 +100,5 @@ static inline void stm32_selectrmii(void)
putreg32(regval, STM32_SYSCFG_PMC);
}
#endif /* CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */
#endif /* __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H */

12
nuttx/arch/arm/src/stm32/stm32_vectors.S
View File

@ -145,6 +145,8 @@ stm32_vectors:
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/chip/stm32f10xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/chip/stm32f20xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/chip/stm32f40xxx_vectors.h"
#else
@ -176,6 +178,8 @@ handlers:
#if defined(CONFIG_STM32_STM32F10XX)
# include "chip/chip/stm32f10xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/chip/stm32f20xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/chip/stm32f40xxx_vectors.h"
#else
@ -204,7 +208,7 @@ stm32_common:
/* Complete the context save */
#ifdef CONFIG_NUTTX_KERNEL
#ifdef CONFIG_NUTTX_KERNEL
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
* (handler mode) if the state is on the MSP. It can only be on the PSP if
* EXC_RETURN is 0xfffffffd (unprivileged thread)
@ -242,7 +246,7 @@ stm32_common:
* values.
*/
#ifdef CONFIG_NUTTX_KERNEL
#ifdef CONFIG_NUTTX_KERNEL
stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */
#else
stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
@ -307,7 +311,7 @@ stm32_common:
ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
#ifdef CONFIG_NUTTX_KERNEL
#ifdef CONFIG_NUTTX_KERNEL
ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
#else
ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
@ -321,7 +325,7 @@ stm32_common:
* r1 = Address of the return stack (same as r0)
*/
1:
#ifdef CONFIG_NUTTX_KERNEL
#ifdef CONFIG_NUTTX_KERNEL
ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
#else
ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */