Add USB device bit definitions
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2706 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -286,8 +286,9 @@
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*/
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/* USB OTG Controller ***************************************************************/
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/* OTG registers */
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/* OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt
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/* OTG registers:
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*
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* OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt
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* Clear
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*/
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@ -326,128 +327,260 @@
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/* USB Device Controller ************************************************************/
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/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
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/* USB Device Interrupt Status */
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#define USBDEV_INTST_
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/* USB Device Interrupt Enable */
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#define USBDEV_INTEN_
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/* USB Device Interrupt Clear */
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#define USBDEV_INTCLR_
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/* USB Device Interrupt Set */
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#define USBDEV_INTSET_
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/* SIE Command registers */
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/* USB Command Code */
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#define USBDEV_CMDCODE_
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/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt
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* Clear, USB Device Interrupt Set, and USB Device Interrupt Priority
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*/
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#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */
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#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */
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#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */
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#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */
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#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */
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#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */
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#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */
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#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */
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#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */
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#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */
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/* Bits 10-31: Reserved */
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/* SIE Command registers:
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*
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* USB Command Code
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*/
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/* Bits 0-7: Reserved */
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#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */
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#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT)
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# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT)
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# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT)
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# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT)
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#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */
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#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT)
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#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */
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#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT)
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/* Bits 24-31: Reserved */
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/* USB Command Data */
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#define USBDEV_CMDDATA_
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/* USB transfer registers */
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#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */
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#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT)
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/* Bits 8-31: Reserved */
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/* USB transfer registers:
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*
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* USB Receive Data (Bits 0-31: Received data)
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*/
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/* USB Receive Data */
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#define USBDEV_RXDATA_
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/* USB Receive Packet Length */
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#define USBDEV_RXPLEN_
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/* USB Transmit Data */
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#define USBDEV_TXDATA_
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#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */
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#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT)
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#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid*/
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#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */
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/* Bits 12-31: Reserved */
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/* USB Transmit Data (Bits 0-31: Transmit data) */
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/* USB Transmit Packet Length */
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#define USBDEV_TXPLEN_
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#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */
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#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT)
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/* Bits 10-31: Reserved */
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/* USB Control */
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#define USBDEV_CTRL_
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/* More Device interrupt registers */
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#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */
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#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */
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#define USBDEV_CTRL_LOGENDPOINT_SHIFT (2) /* Bits 2-5: Logical Endpoint number */
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#define USBDEV_CTRL_LOGENDPOINT_MASK (15 << USBDEV_CTRL_LOGENDPOINT_SHIFT)
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/* Bits 6-31: Reserved */
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/* Endpoint interrupt registers:
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*
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* USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt
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* Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond
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* to on RX or TX value for any of 15 logical endpoints).
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*/
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/* USB Device Interrupt Priority */
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#define USBDEV_INTPRI_
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#define USBDEV_LOGEPRX(n) (1 << ((n) << 1))
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#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1)
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#define USBDEV_LOGEPRX0 (1 << 0)
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#define USBDEV_LOGEPTX0 (1 << 1)
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#define USBDEV_LOGEPRX1 (1 << 2)
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#define USBDEV_LOGEPTX1 (1 << 3)
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#define USBDEV_LOGEPRX2 (1 << 4)
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#define USBDEV_LOGEPTX2 (1 << 5)
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#define USBDEV_LOGEPRX3 (1 << 6)
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#define USBDEV_LOGEPTX3 (1 << 7)
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#define USBDEV_LOGEPRX4 (1 << 8)
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#define USBDEV_LOGEPTX4 (1 << 9)
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#define USBDEV_LOGEPRX5 (1 << 10)
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#define USBDEV_LOGEPTX5 (1 << 11)
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#define USBDEV_LOGEPRX6 (1 << 12)
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#define USBDEV_LOGEPTX6 (1 << 13)
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#define USBDEV_LOGEPRX7 (1 << 14)
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#define USBDEV_LOGEPTX7 (1 << 15)
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#define USBDEV_LOGEPRX8 (1 << 16)
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#define USBDEV_LOGEPTX8 (1 << 17)
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#define USBDEV_LOGEPRX9 (1 << 18)
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#define USBDEV_LOGEPTX9 (1 << 19)
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#define USBDEV_LOGEPRX10 (1 << 20)
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#define USBDEV_LOGEPTX10 (1 << 21)
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#define USBDEV_LOGEPRX11 (1 << 22)
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#define USBDEV_LOGEPTX11 (1 << 23)
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#define USBDEV_LOGEPRX12 (1 << 24)
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#define USBDEV_LOGEPTX12 (1 << 25)
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#define USBDEV_LOGEPRX13 (1 << 26)
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#define USBDEV_LOGEPTX13 (1 << 27)
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#define USBDEV_LOGEPRX14 (1 << 28)
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#define USBDEV_LOGEPTX14 (1 << 29)
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#define USBDEV_LOGEPRX15 (1 << 30)
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#define USBDEV_LOGEPTX15 (1 << 31)
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/* Endpoint interrupt registers */
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/* Endpoint realization registers:
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*
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* USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints)
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*/
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/* USB Endpoint Interrupt Status */
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#define USBDEV_EPINTST_
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/* USB Endpoint Interrupt Enable */
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#define USBDEV_EPINTEN_
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/* USB Endpoint Interrupt Clear */
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#define USBDEV_EPINTCLR_
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/* USB Endpoint Interrupt Set */
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#define USBDEV_EPINTSET_
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/* USB Endpoint Priority */
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#define USBDEV_EPINTPRI_
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#define USBDEV_PHYEP(n) (1 << (n))
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#define USBDEV_PHYEP0 (1 << 0)
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#define USBDEV_PHYEP0 (1 << 1)
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#define USBDEV_PHYEP0 (1 << 2)
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#define USBDEV_PHYEP0 (1 << 3)
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#define USBDEV_PHYEP0 (1 << 4)
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#define USBDEV_PHYEP0 (1 << 5)
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#define USBDEV_PHYEP0 (1 << 6)
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#define USBDEV_PHYEP0 (1 << 7)
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#define USBDEV_PHYEP0 (1 << 8)
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#define USBDEV_PHYEP0 (1 << 9)
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#define USBDEV_PHYEP10 (1 << 10)
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#define USBDEV_PHYEP11 (1 << 11)
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#define USBDEV_PHYEP12 (1 << 12)
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#define USBDEV_PHYEP13 (1 << 13)
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#define USBDEV_PHYEP14 (1 << 14)
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#define USBDEV_PHYEP15 (1 << 15)
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#define USBDEV_PHYEP16 (1 << 16)
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#define USBDEV_PHYEP17 (1 << 17)
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#define USBDEV_PHYEP18 (1 << 18)
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#define USBDEV_PHYEP19 (1 << 19)
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#define USBDEV_PHYEP20 (1 << 20)
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#define USBDEV_PHYEP21 (1 << 21)
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#define USBDEV_PHYEP22 (1 << 22)
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#define USBDEV_PHYEP23 (1 << 23)
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#define USBDEV_PHYEP24 (1 << 24)
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#define USBDEV_PHYEP25 (1 << 25)
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#define USBDEV_PHYEP26 (1 << 26)
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#define USBDEV_PHYEP27 (1 << 27)
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#define USBDEV_PHYEP28 (1 << 28)
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#define USBDEV_PHYEP29 (1 << 29)
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#define USBDEV_PHYEP30 (1 << 30)
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#define USBDEV_PHYEP31 (1 << 31)
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/* Endpoint realization registers */
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/* USB Realize Endpoint */
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#define USBDEV_REEP_
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/* USB Endpoint Index */
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#define USBDEV_EPIND_
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#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */
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#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT)
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/* Bits 5-31: Reserved */
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/* USB MaxPacketSize */
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#define USBDEV_MAXPSIZE_
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/* DMA registers */
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#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */
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#define USBDEV_MAXPSIZE_ (0x3ff << USBDEV_MAXPSIZE_SHIFT)
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/* Bits 10-31: Reserved */
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/* DMA registers:
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*
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* USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers
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* contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions
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* above. PHYEP0-1 (bits 0-1) must be zero.
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*/
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/* USB DMA Request Status */
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#define USBDEV_DMARST_
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/* USB DMA Request Clear */
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#define USBDEV_DMARCLR_
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/* USB DMA Request Set */
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#define USBDEV_DMARSET_
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/* USB UDCA Head */
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#define USBDEV_UDCAH_
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/* USB Endpoint DMA Status */
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#define USBDEV_EPDMAST_
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/* USB Endpoint DMA Enable */
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#define USBDEV_EPDMAEN_
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/* USB Endpoint DMA Disable */
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#define USBDEV_EPDMADIS_
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/* USB DMA Interrupt Status */
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#define USBDEV_DMAINTST_
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/* USB DMA Interrupt Enable */
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#define USBDEV_DMAINTEN_
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/* USB End of Transfer Interrupt Status */
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#define USBDEV_EOTINTST_
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/* USB End of Transfer Interrupt Clear */
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#define USBDEV_EOTINTCLR_
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/* USB End of Transfer Interrupt Set */
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#define USBDEV_EOTINTSET_
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/* USB New DD Request Interrupt Status */
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#define USBDEV_NDDRINTST_
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/* USB New DD Request Interrupt Clear */
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#define USBDEV_NDDRINTCLR_
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/* USB New DD Request Interrupt Set */
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#define USBDEV_NDDRINTSET_
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/* USB System Error Interrupt Status */
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#define USBDEV_SYSERRINTST_
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/* USB System Error Interrupt Clear */
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#define USBDEV_SYSERRINTCLR_
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/* USB System Error Interrupt Set */
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#define USBDEV_SYSERRINTSET_
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/* Bits 0-6: Reserved */
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#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */
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#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT)
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/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable.
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* Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP*
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* definitions above. PHYEP0-1 (bits 0-1) must be zero.
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*/
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/* USB DMA Interrupt Status and USB DMA Interrupt Enable */
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#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */
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#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */
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#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */
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/* Bits 3-31: Reserved */
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/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB
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* End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31.
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* Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero.
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*/
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/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB
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* New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31.
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* Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero.
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*/
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/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System
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* Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use
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* the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero.
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*/
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/* OTG I2C registers ****************************************************************/
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/* I2C Receive */
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#define OTGI2C_RX_
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/* I2C Transmit */
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#define OTGI2C_TX_
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/* I2C Status */
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#define OTGI2C_STS_
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/* I2C Control */
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#define OTGI2C_CTL_
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/* I2C Clock High */
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#define OTGI2C_CLKHI_
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/* I2C Clock Low */
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#define OTGI2C_CLKLO_
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#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */
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#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT)
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/* Bits 8-31: Reserved */
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/* I2C Transmit */
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#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */
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#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT)
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#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */
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#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */
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/* Bits 3-31: Reserved */
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/* I2C Status */
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#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */
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#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */
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#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */
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#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */
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#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */
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#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */
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#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */
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#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */
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#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */
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#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */
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#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */
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#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */
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/* Bits 12-31: Reserved */
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/* I2C Control */
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#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */
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#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */
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#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */
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#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */
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#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */
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#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */
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#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */
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#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */
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#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */
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/* Bits 9-31: Reserved */
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/* I2C Clock High */
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#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */
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#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT)
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/* Bits 8-31: Reserved */
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/* I2C Clock Low */
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#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */
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#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT)
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/* Bits 8-31: Reserved */
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/* Clock control registers ***********************************************************/
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/* OTG clock controller */
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#define USBOTG_CLKCTRL_
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/* OTG clock status */
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#define USBOTG_CLKST_
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/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */
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/* USB Clock Control */
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#define USBDEV_CLKCTRL_
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/* USB Clock Status */
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#define USBDEV_CLKST_
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#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */
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#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */
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#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */
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#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */
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#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */
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#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */
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/* Bits 5-31: Reserved */
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/************************************************************************************
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* Public Types
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