More init logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2303 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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@ -552,7 +552,7 @@ __start:
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* as possible. Modifies r0, r1, r2, and r14.
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*/
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bl up_lowsetup
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bl up_lowsetup
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showprogress 'A'
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/* Setup system stack (and get the BSS range) */
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@ -53,6 +53,7 @@
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************************************************************************************/
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.globl __start
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.globl os_start
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.file "mc9s12ne64_start.S"
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/****************************************************************************
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@ -62,10 +63,20 @@
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/* Memory map initialization */
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.macro MMCINIT
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movb #0, HC12_MMC_INITRG /* Set the register map position */
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clr HC12_MMC_INITRG /* Set the register map position to 0x0000*/
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nop
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movb #32, HC12_MMC_INITRM /* Set the RAM map position */
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movb #1, HC12_MMC_MISC /* MISC: EXSTR1=0 EXSTR0=0 ROMHM=0 ROMON=1 */
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ldab #0x09
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stab *HC12_MMC_INITEE /* Set EEPROM position to 0x0800 */
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#ifdef CONFIG_HC12_SERIALMON
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ldab #0x39 /* Set RAM position to 0x3800 */
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#else
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ldab #0x20 /* Set RAM position to 0x2000*/
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#endif
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stab *HC12_MMC_INITRM
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ldaa #MMC_MISC_ROMON /* MISC: EXSTR1=0 EXSTR0=0 ROMHM=0 ROMON=1 */
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staa *HC12_MMC_MISC
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.endm
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/* System clock initialization */
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@ -74,35 +85,33 @@
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/* Select the clock source from crystal */
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movb #0, HC12_CRG_CLKSEL
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movb #CRG_CRGSEL_PLLSEL, HC12_CRG_CLKSEL
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clr HC12_CRG_CLKSEL
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/* Set the multipler and divider and enable the PLL */
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movb #0, HC12_CRG_PLLCTL
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movb #15, HC12_CRG_SYNR
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movb #15, HC12_CRG_REFDV
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movb #(CRG_PLLCTL_CME|CRG_PLLCTL_PLLON), HC12_CRG_PLLCTL
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bclr *HC12_CRG_PLLCTL #CRG_PLLCTL_PLLON
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ldab #15
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stab HC12_CRG_SYNR
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stab HC12_CRG_REFDV
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bset *HC12_CRG_PLLCTL #CRG_PLLCTL_PLLON
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/* Wait for the PLL to lock on */
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.Lpll_lock:
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ldab HC12_CRG_CRGFLG
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clra
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andb #CRG_CRGFLG_LOCK
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ldx #0
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bne .Lpll_lock
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tbne d,.Lpll_lock
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brclr *HC12_CRG_CRGFLG #CRG_CRGFLG_LOCK .Lpll_lock
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/* The select the PLL clock source */
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/* Then select the PLL clock source */
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bset HC12_CRG_CLKSEL_OFFSET, #CRG_CLKSEL_PLLSEL
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bset *HC12_CRG_CLKSEL #CRG_CLKSEL_PLLSEL
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.endm
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/****************************************************************************
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* .text
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****************************************************************************/
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.section nonbanked, "x"
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/****************************************************************************
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* Name: __start
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*
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@ -112,6 +121,87 @@
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****************************************************************************/
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__start:
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MMCINIT /* Initialize the MMC */
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PLLINIT /* Initialize the PLL */
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/* Hardware setup */
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MMCINIT /* Initialize the MMC */
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PLLINIT /* Initialize the PLL */
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/* Setup the stack pointer */
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lds .Lstackbase
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/* Clear BSS */
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ldx .Lsbss /* Start of .BSS */
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ldd .Lebss /* End+1 of .BSS */
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.Lclearbss:
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pshd
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cpx 2,sp+ /* Check if all BSS has been cleared */
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beq .Lbsscleared /* If so, exit the loop */
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clr 0,x /* Clear this byte */
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inx /* Address the next byte */
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bra .Lclearbss /* And loop until all cleared */
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.Lbsscleared:
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/* Initialize the data section */
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ldx .Lsdata /* Start of .DATA (destination) */
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movw .Ledata, 0, sp /* End of .DATA (destination) */
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ldy .Leronly /* Start of .DATA (source) */
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.Linitdata:
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cpx 0, sp /* Check if all .DATA has been initialized */
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beq .Ldatainitialized /* If so, exit the loop */
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ldab 0, y /* Fetch the next byte from the source */
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iny /* Increment the source address */
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stab 0, x /* Store the byte to the destination */
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inx /* Increment the destination address */
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bra .Linitdata /* And loop until all of .DATA is initialized */
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.Ldatainitialized:
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/* Now, start the OS */
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call os_start
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bra __start
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/* Variables:
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* _sbss is the start of the BSS region (see ld.script)
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* _ebss is the end of the BSS regsion (see ld.script)
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* The idle task stack starts at the end of BSS and is
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* of size CONFIG_IDLETHREAD_STACKSIZE. The heap continues
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* from there until the end of memory. See g_heapbase
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* below.
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*/
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.Lsbss:
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.long _sbss
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.Lebss:
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.long _ebss
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.Lstackbase:
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.hword _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
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.Leronly:
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.long _eronly /* Where .data defaults are stored in FLASH */
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.Lsdata:
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.long _sdata /* Where .data needs to reside in SDRAM */
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.Ledata:
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.long _edata
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.size __start, .-__start
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/* This global variable is unsigned long g_heapbase and is
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* exported from here only because of its coupling to LCO
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* above.
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*/
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.data
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.align 4
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.globl g_heapbase
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.type g_heapbase, object
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g_heapbase:
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.long _ebss+CONFIG_IDLETHREAD_STACKSIZE
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.size g_heapbase, .-g_heapbase
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.end
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.end
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@ -64,7 +64,7 @@
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* Vectors
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************************************************************************************/
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.section .vectors, "rd"
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.section .vectors, "x"
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.align 2
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.globl hc12_vectors
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.type hc12_vectors, function
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@ -33,17 +33,14 @@
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*
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****************************************************************************/
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/* The DEMO9S12NE64 has 512Kb of FLASH beginning at address 0x0800:0000 and
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* 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH,
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* FLASH memory is aliased to address 0x0000:0000 where the code expects to
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* begin execution by jumping to the entry point in the 0x0800:0000 address
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* range.
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/* The DEMO9S12NE64 has 64Kb of FLASH and 8Kb of SRAM that are assumed to be
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* positioned as below:
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*/
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MEMORY
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{
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flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K
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sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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flash (rx) : ORIGIN = 0x0800, LENGTH = 64K
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sram (rwx) : ORIGIN = 0x3800, LENGTH = 8K
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}
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OUTPUT_ARCH(m68hc12)
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