Add (and use) some new PIC32MX CP0 macros
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4079 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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@ -338,7 +338,7 @@ struct xcptcontext
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* Name: cp0_getstatus
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*
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* Description:
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* Disable interrupts
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* Read the CP0 STATUS register
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*
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* Input Parameters:
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* None
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@ -355,7 +355,7 @@ static inline irqstate_t cp0_getstatus(void)
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t mfc0 %0,$12\n" /* Get CP0 status register */
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"\t mfc0 %0, $12, 0\n" /* Get CP0 status register */
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"\t.set pop\n"
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: "=r" (status)
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:
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@ -369,7 +369,7 @@ static inline irqstate_t cp0_getstatus(void)
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* Name: cp0_putstatus
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*
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* Description:
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* Disable interrupts
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* Write the CP0 STATUS register
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*
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* Input Parameters:
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* None
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@ -386,7 +386,7 @@ static inline void cp0_putstatus(irqstate_t status)
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"\t.set push\n"
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"\t.set noat\n"
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"\t.set noreorder\n"
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"\tmtc0 %0,$12\n" /* Set the status to the provided value */
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"\tmtc0 %0, $12, 0\n" /* Set the status to the provided value */
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"\tnop\n" /* MTC0 status hazard: */
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"\tnop\n" /* Recommended spacing: 3 */
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"\tnop\n"
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@ -398,6 +398,66 @@ static inline void cp0_putstatus(irqstate_t status)
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);
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}
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/****************************************************************************
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* Name: cp0_getcause
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*
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* Description:
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* Get the CP0 CAUSE register
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline uint32_t cp0_getcause(void)
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{
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register irqstate_t cause;
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t mfc0 %0, $13, 0\n" /* Get CP0 cause register */
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"\t.set pop\n"
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: "=r" (cause)
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:
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: "memory"
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);
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return cause;
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}
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/****************************************************************************
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* Name: cp0_putcause
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*
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* Description:
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* Write the CP0 CAUSE register
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void cp0_putcause(uint32_t cause)
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{
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t.set noreorder\n"
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"\tmtc0 %0, $13, 0\n" /* Set the cause to the provided value */
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"\t.set pop\n"
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:
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: "r" (cause)
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: "memory"
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);
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}
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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@ -67,6 +67,126 @@
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Name: cp0_getintctl
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*
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* Description:
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* Get the CP0 IntCtl register
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline uint32_t cp0_getintctl(void)
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{
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register irqstate_t ebase;
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t mfc0 %0, $12, 1\n" /* Get CP0 IntCtl register */
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"\t.set pop\n"
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: "=r" (ebase)
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:
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: "memory"
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);
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return cause;
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}
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/****************************************************************************
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* Name: cp0_putintctl
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*
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* Description:
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* Write the CP0 IntCtl register
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void cp0_putintctl(uint32_t ebase)
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{
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t.set noreorder\n"
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"\tmtc0 %0, $12, 1\n" /* Set the IntCtl to the provided value */
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"\t.set pop\n"
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:
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: "r" (ebase)
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: "memory"
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);
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}
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/****************************************************************************
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* Name: cp0_getebase
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*
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* Description:
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* Get the CP0 EBASE register
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline uint32_t cp0_getebase(void)
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{
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register irqstate_t ebase;
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t mfc0 %0, $15, 1\n" /* Get CP0 EBASE register */
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"\t.set pop\n"
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: "=r" (ebase)
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:
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: "memory"
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);
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return cause;
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}
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/****************************************************************************
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* Name: cp0_putebase
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*
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* Description:
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* Write the CP0 EBASE register
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void cp0_putebase(uint32_t ebase)
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{
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t.set noreorder\n"
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"\tmtc0 %0, $15, 1\n" /* Set the EBASE to the provided value */
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"\t.set pop\n"
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:
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: "r" (ebase)
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: "memory"
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);
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}
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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@ -107,14 +107,33 @@ void up_irqinitialize(void)
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{
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(void)up_prioritize_irq(irq, (INT_ICP_MID_PRIORITY << 2));
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}
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/* Set the CP0 cause IV bit meaning that the interrupt exception uses
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* the "special interrupt vector"
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*/
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asm volatile("\tmfc0 %0,$13,0\n" : "=r"(regval));
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/* Set the BEV bit in the STATUS register */
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regval = cp0_getstatus();
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regval |= CP0_STATUS_BEV;
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cp0_putstatus(regval);
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/* Set the EBASE value to the beginning of boot FLASH */
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cp0_putebase(0xbfc00000);
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/* Set the INTCTL vector spacing to non-zero */
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cp0_putintctl(0x00000020);
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/* Set the IV bit in the CAUSE register */
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regval = cp0_getcause();
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regval |= CP0_CAUSE_IV;
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asm volatile("\tmtc0 %0,$13,0\n" : : "r"(regval));
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cp0_putcause(regval);
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/* Clear the EXL bit in the STATUS register */
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regval = cp0_getstatus();
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//regval &= ~CP0_STATUS_BEV;
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regval &= ~CP0_STATUS_EXL;
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cp0_putstatus(regval);
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/* Configure multi- or single- vector interrupts */
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