Add PHY init logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3100 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
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3db717c4ec
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@ -1239,7 +1239,7 @@
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For people who have their own configurations and/or Makefiles,
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you will need to make a couple of changes:
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- Replace all occurrences of CONFIG_EXAMPLE=foobar with
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- Replace all occurrences of CONFIG_EXAMPLE=foobar with
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CONFIG_APP_DIR=examples/foobar in all of the configuration
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files.
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- Replace any occurrences of examples/$(CONFIG_EXAMPLE) with
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@ -1329,8 +1329,13 @@
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not refer to an open file.
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* configs/olimex-lpc1766stk - Add support for the Olimex LPC1766-STK
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development board. The OS test and NSH configurations (only) have been
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verified.
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verified.
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5.14 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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* configs/olimex-lpc1766stk/nettest - Add examples/nettest configuration to
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verify the LPC17xx ethernet driver currently under development.
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* arch/arm/src/lpc17xx/lpc17xx_ethernet.c/.h - Began development of
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the LPC17xx Ethernet driver.
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@ -8,7 +8,7 @@
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<tr align="center" bgcolor="#e4e4e4">
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<td>
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<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
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<p>Last Updated: November 9, 2010</p>
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<p>Last Updated: November 11, 2010</p>
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</td>
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</tr>
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</table>
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@ -1982,6 +1982,11 @@ buildroot-1.8 2009-12-21 <spudmonkey@racsa.co.cr>
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<ul><pre>
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nuttx-5.14 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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* configs/olimex-lpc1766stk/nettest - Add examples/nettest configuration to
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verify the LPC17xx ethernet driver currently under development.
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* arch/arm/src/lpc17xx/lpc17xx_ethernet.c/.h - Began development of
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the LPC17xx Ethernet driver.
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pascal-2.1 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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buildroot-1.9 2010-xx-xx <spudmonkey@racsa.co.cr>
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@ -192,7 +192,7 @@ struct lm3s_driver_s
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#if LM3S_NETHCONTROLLERS > 1
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uint32_t ld_base; /* Ethernet controller base address */
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int ld-irq; /* Ethernet controller IRQ */
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int ld_irq; /* Ethernet controller IRQ */
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#endif
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bool ld_bifup; /* true:ifup false:ifdown */
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@ -50,6 +50,7 @@
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/mii.h>
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#include <net/uip/uip.h>
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#include <net/uip/uip-arp.h>
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@ -103,9 +104,23 @@
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#define BUF ((struct uip_eth_hdr *)priv->lp_dev.d_buf)
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/* Select PHY-specific values. Add more PHYs as needed. */
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#ifdef CONFIG_PHY_KS8721
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# define LPC17_PHYNAME "KS8721"
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# define LPC17_PHYID1 MII_PHYID1_KS8721
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# define LPC17_PHYID2 MII_PHYID2_KS8721
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# define LPC17_HAVE_PHY 1
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#else
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# warning "No PHY specified!"
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# undef LPC17_HAVE_PHY
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#endif
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#define MII_BIG_TIMEOUT 666666
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/* This is the number of ethernet GPIO pins that must be configured */
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#define GPIO_NENET_PINS 10
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#define GPIO_NENET_PINS 10
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/* Register debug */
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@ -123,7 +138,19 @@
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struct lpc17_driver_s
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{
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/* The following fields would only be necessary on chips that support
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* multiple Ethernet controllers.
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*/
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#if LM3S_NETHCONTROLLERS > 1
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uint32_t lp_base; /* Ethernet controller base address */
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int lp_irq; /* Ethernet controller IRQ */
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#endif
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bool lp_bifup; /* true:ifup false:ifdown */
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#ifdef LPC17_HAVE_PHY
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uint8_t lp_phyaddr; /* PHY device address */
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#endif
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WDOG_ID lp_txpoll; /* TX poll timer */
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WDOG_ID lp_txtimeout; /* TX timeout timer */
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@ -157,18 +184,16 @@ static const uint16_t g_enetpins[GPIO_NENET_PINS] =
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* Private Function Prototypes
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****************************************************************************/
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/* Register operations ********************************************************/
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/* Register operations */
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#ifdef CONFIG_LPC17_ENET_REGDEBUG
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static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite);
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static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite);
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static uint32_t lpc17_getreg(uint32_t addr);
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static void lpc17_putreg(uint32_t val, uint32_t addr);
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static void lpc17_showpins(void);
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#else
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# define lpc17_getreg(addr) getreg32(addr)
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# define lpc17_putreg(val,addr) putreg32(val,addr)
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# define lpc17_showpins()
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#endif
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/* Common TX logic */
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@ -199,8 +224,38 @@ static int lpc17_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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/* Initialization functions */
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static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata);
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#ifdef CONFIG_LPC17_ENET_REGDEBUG
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static void lpc17_showpins(void);
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#else
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# define lpc17_showpins()
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#endif
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/* PHY initialization functions */
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#ifdef LPC17_HAVE_PHY
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# ifdef CONFIG_LPC17_ENET_REGDEBUG
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static void lpc17_showmii(uint8_t phyaddr, const char *msg);
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# else
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# define lpc17_showmii(phyaddr,msg)
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# endif
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static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr,
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uint16_t phydata);
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static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr);
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static inline int lpc17_phyreset(uint8_t phyaddr);
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# ifdef CONFIG_PHY_AUTONEG
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static inline int lpc17_phyautoneg(uint8_t phyaddr);
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# endif
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static int lpc17_phyfixed(uint8_t phyaddr, bool speed100, bool fullduplex);
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static void lpc17_phyfullduplex(uint8_t phyaddr);
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static inline int lpc17_phyinit(struct lpc17_driver_s *priv);
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#else
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# define lpc17_phyinit()
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#endif
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/* EMAC Initialization functions */
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static void lpc17_ethreset(struct lpc17_driver_s *priv);
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/****************************************************************************
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* Private Functions
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@ -328,22 +383,6 @@ static void lpc17_putreg(uint32_t val, uint32_t addr)
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}
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#endif
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/*******************************************************************************
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* Name: lpc17_showpins
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*
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* Description:
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* Dump GPIO register
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*
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*******************************************************************************/
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#ifdef CONFIG_LPC17_ENET_REGDEBUG
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static void lpc17_showpins(void)
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{
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lpc17_dumpgpio(GPIO_PORT0|GPIO_PIN0, "P0[1-15]");
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lpc17_dumpgpio(GPIO_PORT0|GPIO_PIN16, "P0[16-31]");
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}
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#endif
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/****************************************************************************
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* Function: lpc17_transmit
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*
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@ -653,6 +692,7 @@ static void lpc17_polltimer(int argc, uint32_t arg, ...)
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static int lpc17_ifup(struct uip_driver_s *dev)
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{
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FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)dev->d_private;
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uint32_t regval;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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@ -660,6 +700,20 @@ static int lpc17_ifup(struct uip_driver_s *dev)
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/* Initilize Ethernet interface */
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/* Configure the MAC station address */
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regval = (uint32_t)priv->lp_dev.d_mac.ether_addr_octet[1] << 8 |
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(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[0];
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lpc17_putreg(regval, LPC17_ETH_SA0);
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regval = (uint32_t)priv->lp_dev.d_mac.ether_addr_octet[3] << 8 |
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(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[2];
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lpc17_putreg(regval, LPC17_ETH_SA1);
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regval = (uint32_t)priv->lp_dev.d_mac.ether_addr_octet[5] << 8 |
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(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[4];
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lpc17_putreg(regval, LPC17_ETH_SA2);
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/* Set and activate a timer process */
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(void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_polltimer, 1, (uint32_t)priv);
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@ -809,6 +863,61 @@ static int lpc17_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
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}
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#endif
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/*******************************************************************************
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* Name: lpc17_showpins
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*
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* Description:
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* Dump GPIO registers
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*
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* Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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*******************************************************************************/
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#ifdef CONFIG_LPC17_ENET_REGDEBUG
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static void lpc17_showpins(void)
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{
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lpc17_dumpgpio(GPIO_PORT0|GPIO_PIN0, "P0[1-15]");
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lpc17_dumpgpio(GPIO_PORT0|GPIO_PIN16, "P0[16-31]");
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}
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#endif
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/*******************************************************************************
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* Name: lpc17_showmii
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*
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* Description:
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* Dump PHY MII registers
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*
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* Parameters:
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* phyaddr - The device address where the PHY was discovered
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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*******************************************************************************/
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#if defined(CONFIG_LPC17_ENET_REGDEBUG) && defined(LPC17_HAVE_PHY)
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static void lpc17_showmii(uint8_t phyaddr, const char *msg)
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{
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lldbg("PHY " LPC17_PHYNAME ": %s\n", msg);
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lldbg(" MCR: %04x\n", lpc17_getreg(MII_MCR));
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lldbg(" MSR: %04x\n", lpc17_getreg(MII_MSR));
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lldbg(" ADVERTISE: %04x\n", lpc17_getreg(MII_ADVERTISE));
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lldbg(" LPA: %04x\n", lpc17_getreg(MII_LPA));
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lldbg(" EXPANSION: %04x\n", lpc17_getreg(MII_EXPANSION));
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#ifdef CONFIG_PHY_KS8721
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lldbg(" 10BTCR: %04x\n", lpc17_getreg(MII_KS8721_10BTCR));
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#endif
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phywrite
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*
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@ -827,6 +936,7 @@ static int lpc17_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
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*
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****************************************************************************/
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#ifdef LPC17_HAVE_PHY
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static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata)
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{
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uint32_t regval;
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@ -849,9 +959,10 @@ static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata)
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while ((lpc17_getreg(LPC17_ETH_MIND) & ETH_MIND_BUSY) != 0);
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phywrite
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* Function: lpc17_phyread
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*
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* Description:
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* Read a value from an MII PHY register
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@ -867,6 +978,7 @@ static void lpc17_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata)
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*
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****************************************************************************/
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#ifdef LPC17_HAVE_PHY
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static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr)
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{
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uint32_t regval;
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@ -890,7 +1002,400 @@ static uint16_t lpc17_phyread(uint8_t phyaddr, uint8_t regaddr)
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/* Return the PHY register data */
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return (uint16_t)lpc17_getreg(LPC17_ETH_MRDD);
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return (uint16_t)(lpc17_getreg(LPC17_ETH_MRDD) & ETH_MRDD_MASK);
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phyreset
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*
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* Description:
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* Reset the PHY
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*
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* Parameters:
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* phyaddr - The device address where the PHY was discovered
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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****************************************************************************/
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#ifdef LPC17_HAVE_PHY
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static inline int lpc17_phyreset(uint8_t phyaddr)
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{
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int32_t timeout;
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uint16_t phyreg;
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/* Reset the PHY. Needs a minimal 50uS delay after reset. */
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lpc17_phywrite(phyaddr, MII_MCR, MII_MCR_RESET);
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/* Wait for a minimum of 50uS no matter what */
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up_udelay(50);
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/* The MCR reset bit is self-clearing. Wait for it to be clear
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* indicating that the reset is complete.
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*/
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for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--)
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{
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phyreg = lpc17_phyread(phyaddr, MII_MCR);
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if ((phyreg & MII_MCR_RESET) == 0)
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{
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return OK;
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}
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}
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nlldbg("Reset failed. MCR: %04x\n", phyreg);
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return -ETIMEDOUT;
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phyautoneg
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*
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* Description:
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* Enable auto-negotiation.
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*
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* Parameters:
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* phyaddr - The device address where the PHY was discovered
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* The adverisement regiser has already been configured.
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*
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****************************************************************************/
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#if defined(LPC17_HAVE_PHY) && defined(CONFIG_PHY_AUTONEG)
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static inline int lpc17_phyautoneg(uint8_t phyaddr)
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{
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int32_t timeout;
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uint16_t phyreg;
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/* Start auto-negotiation */
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lpc17_phywrite(phyaddr, MII_MCR, MII_MCR_ANENABLE | MII_MCR_ANRESTART);
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/* Wait for autonegotiation to complete */
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for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if auto-negotiation has completed */
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phyreg = lpc17_phyread(phyaddr, MII_MSR);
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if ((phyreg & (MII_MSR_LINKSTATUS | MII_MSR_ANEGCOMPLETE)) ==
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(MII_MSR_LINKSTATUS | MII_MSR_ANEGCOMPLETE))
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{
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/* Yes.. return success */
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return OK;
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}
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}
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nlldbg("Auto-negotiation failed. MSR: %04x\n", phyreg);
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return -ETIMEDOUT;
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}
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#endif
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/****************************************************************************
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* Function: lpc17_phyfixed
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*
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* Description:
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* Set fixed PHY configuration.
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*
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* Parameters:
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* phyaddr - The device address where the PHY was discovered
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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*
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****************************************************************************/
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#ifdef LPC17_HAVE_PHY
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static int lpc17_phyfixed(uint8_t phyaddr, bool speed100, bool fullduplex)
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{
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int32_t timeout;
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uint16_t phyreg;
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/* Disable auto-negotiation and set fixed Speed and Duplex settings */
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phyreg = 0;
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if (speed100)
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{
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phyreg = MII_MCR_SPEED100;
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}
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if (fullduplex)
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{
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phyreg |= MII_MCR_FULLDPLX;
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}
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lpc17_phywrite(phyaddr, MII_MCR, phyreg);
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/* Then wait for the link to be established */
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for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--)
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{
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phyreg = lpc17_phyread(phyaddr, MII_MSR);
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if (phyreg & MII_MSR_LINKSTATUS)
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{
|
||||
/* Yes.. return success */
|
||||
|
||||
return OK;
|
||||
}
|
||||
}
|
||||
|
||||
nlldbg("Link failed. MSR: %04x\n", phyreg);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Function: lpc17_phyfulldplex
|
||||
*
|
||||
* Description:
|
||||
* Tweak a few things for full duplex.
|
||||
*
|
||||
* Parameters:
|
||||
* phyaddr - The device address where the PHY was discovered
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC17_HAVE_PHY
|
||||
static void lpc17_phyfullduplex(uint8_t phyaddr)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the inter-packet gap */
|
||||
|
||||
lpc17_putreg(21,LPC17_ETH_IPGT);
|
||||
|
||||
/* Set MAC to operate in full duplex mode */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_MAC2);
|
||||
regval |= ETH_MAC2_FD;
|
||||
lpc17_putreg(regval, LPC17_ETH_MAC2);
|
||||
|
||||
/* Select full duplex operation for ethernet controller */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_CMD);
|
||||
regval |= ETH_CMD_FD;
|
||||
lpc17_putreg(regval, LPC17_ETH_CMD);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Function: lpc17_phyinit
|
||||
*
|
||||
* Description:
|
||||
* Initialize the PHY
|
||||
*
|
||||
* Parameters:
|
||||
* priv - Pointer to EMAC device driver structure
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC17_HAVE_PHY
|
||||
static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
|
||||
{
|
||||
unsigned int phyaddr;
|
||||
uint16_t phyreg;
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
|
||||
/* MII configuration: host clocked divided per board.h, no suppress
|
||||
* preambl,e no scan increment.
|
||||
*/
|
||||
|
||||
lpc17_putreg(ETH_MCFG_CLKSEL_DIV, LPC17_ETH_MCFG);
|
||||
lpc17_putreg(0, LPC17_ETH_MCMD);
|
||||
|
||||
/* Enter RMII mode and select 100 MBPS support */
|
||||
|
||||
lpc17_putreg(ETH_CMD_RMII, LPC17_ETH_CMD);
|
||||
lpc17_putreg(ETH_SUPP_SPEED, LPC17_ETH_SUPP);
|
||||
|
||||
/* Find PHY Address. Because controller has a pull-up and the
|
||||
* PHY have pull-down resistors on RXD lines some times the PHY
|
||||
* latches different at different addresses.
|
||||
*/
|
||||
|
||||
for (phyaddr = 1; phyaddr < 32; phyaddr++)
|
||||
{
|
||||
/* Check if we can see the selected device ID at this
|
||||
* PHY address.
|
||||
*/
|
||||
|
||||
phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1);
|
||||
if (phyreg == LPC17_PHYID1)
|
||||
{
|
||||
phyreg = lpc17_phyread(phyaddr, MII_PHYID2);
|
||||
if (phyreg == LPC17_PHYID2)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
nlldbg("phyaddr: %d\n", phyaddr);
|
||||
|
||||
/* Check if the PHY device address was found */
|
||||
|
||||
if (phyaddr > 31)
|
||||
{
|
||||
/* Failed to find PHY at any location */
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Save the discovered PHY device address */
|
||||
|
||||
priv->lp_phyaddr = phyaddr;
|
||||
|
||||
/* Reset the PHY */
|
||||
|
||||
ret = lpc17_phyreset(phyaddr);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
lpc17_showmii(phyaddr, "After reset");
|
||||
|
||||
/* Check for preamble suppression support */
|
||||
|
||||
phyreg = lpc17_phyread(phyaddr, MII_MSR);
|
||||
if ((phyreg & MII_MSR_MFRAMESUPPRESS) != 0)
|
||||
{
|
||||
/* The PHY supports preamble suppression */
|
||||
|
||||
regval = lpc17_getreg(LPC17_ETH_MCFG);
|
||||
regval |= ETH_MCFG_SUPPRE;
|
||||
lpc17_putreg(regval, LPC17_ETH_MCFG);
|
||||
}
|
||||
|
||||
/* Are we configured to do auto-negotiation? */
|
||||
|
||||
#ifdef CONFIG_PHY_AUTONEG
|
||||
/* Setup the Auto-negotiation advertisement: 100 or 10, and HD or FD */
|
||||
|
||||
lpc17_phywrite(phyaddr, MII_ADVERTISE,
|
||||
(MII_ADVERTISE_100BASETXFULL | MII_ADVERTISE_100BASETXHALF |
|
||||
MII_ADVERTISE_10BASETXFULL | MII_ADVERTISE_10BASETXHALF |
|
||||
MII_ADVERTISE_CSMA));
|
||||
ret = lpc17_phyautoneg(phyaddr);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
/* Set up the fixed PHY configuration */
|
||||
|
||||
ret = lpc17_phyfixed(phyaddr, );
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* The link is established */
|
||||
|
||||
lpc17_showmii(phyaddr, "After link established");
|
||||
|
||||
/* Check configuration */
|
||||
|
||||
#ifdef CONFIG_PHY_KS8721
|
||||
phyreg = lpc17_phyread(phyaddr, MII_KS8721_10BTCR);
|
||||
|
||||
switch (phyreg & KS8721_10BTCR_MODE_MASK)
|
||||
{
|
||||
case KS8721_10BTCR_MODE_10BTHD: /* 10BASE-T half duplex */
|
||||
nlldbg("10BASE-T half duplex\n");
|
||||
lpc17_putreg(0, LPC17_ETH_SUPP);
|
||||
lpc17_phyfixed(phyaddr, false, false);
|
||||
break;
|
||||
case KS8721_10BTCR_MODE_100BTHD: /* 100BASE-T half duplex */
|
||||
nlldbg("100BASE-T half duplex\n");
|
||||
lpc17_phyfixed(phyaddr, true, false);
|
||||
break;
|
||||
case KS8721_10BTCR_MODE_10BTFD: /* 10BASE-T full duplex */
|
||||
nlldbg("10BASE-T full duplex\n");
|
||||
lpc17_putreg(0, LPC17_ETH_SUPP);
|
||||
lpc17_phyfullduplex(phyaddr);
|
||||
lpc17_phyfixed(phyaddr, false, true);
|
||||
break;
|
||||
case KS8721_10BTCR_MODE_100BTFD: /* 100BASE-T full duplex */
|
||||
nlldbg("100BASE-T full duplex\n");
|
||||
lpc17_phyfullduplex(phyaddr);
|
||||
lpc17_phyfixed(phyaddr, true, true);
|
||||
break;
|
||||
default:
|
||||
lldbg("Unrecognized mode: %04x\n", phyreg);
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Function: lpc17_ethreset
|
||||
*
|
||||
* Description:
|
||||
* Configure and reset the Ethernet module, leaving it in a disabled state.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - Reference to the driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; a negated errno on failure
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void lpc17_ethreset(struct lpc17_driver_s *priv)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
#if LPC17_NETHCONTROLLERS > 1
|
||||
# error "If multiple interfaces are supported, this function would have to be redesigned"
|
||||
#endif
|
||||
|
||||
/* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
/* Put the Ethernet controller into the reset state */
|
||||
|
||||
/* Wait just a bit. This is a much longer delay than necessary */
|
||||
|
||||
up_mdelay(2);
|
||||
|
||||
/* Then take the Ethernet controller out of the reset state */
|
||||
|
||||
/* Disable all Ethernet controller interrupts */
|
||||
|
||||
/* Clear any pending interrupts (shouldn't be any) */
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -919,10 +1424,14 @@ int lpc17_ethinitialize(int intf)
|
|||
static inline int lpc17_ethinitialize(int intf)
|
||||
#endif
|
||||
{
|
||||
struct lpc17_driver_s *priv = &g_ethdrvr[intf];
|
||||
struct lpc17_driver_s *priv;
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
DEBUGASSERT(inf < LPC17_NETHCONTROLLERS);
|
||||
priv = &g_ethdrvr[intf];
|
||||
|
||||
/* Turn on the ethernet MAC clock */
|
||||
|
||||
regval = lpc17_getreg(LPC17_SYSCON_PCONP);
|
||||
|
|
@ -937,34 +1446,51 @@ static inline int lpc17_ethinitialize(int intf)
|
|||
}
|
||||
lpc17_showpins();
|
||||
|
||||
/* Initialize the driver structure */
|
||||
|
||||
memset(g_ethdrvr, 0, CONFIG_LPC17_NINTERFACES*sizeof(struct lpc17_driver_s));
|
||||
priv->lp_dev.d_ifup = lpc17_ifup; /* I/F down callback */
|
||||
priv->lp_dev.d_ifdown = lpc17_ifdown; /* I/F up (new IP address) callback */
|
||||
priv->lp_dev.d_txavail = lpc17_txavail; /* New TX data callback */
|
||||
#ifdef CONFIG_NET_IGMP
|
||||
priv->lp_dev.d_addmac = lpc17_addmac; /* Add multicast MAC address */
|
||||
priv->lp_dev.d_rmmac = lpc17_rmmac; /* Remove multicast MAC address */
|
||||
#endif
|
||||
priv->lp_dev.d_private = (void*)priv; /* Used to recover private state from dev */
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
# error "A mechanism to associate base address an IRQ with an interface is needed"
|
||||
priv->lp_base = ??; /* Ethernet controller base address */
|
||||
priv->lp_irq = ??; /* Ethernet controller IRQ number */
|
||||
#endif
|
||||
|
||||
/* Create a watchdog for timing polling for and timing of transmisstions */
|
||||
|
||||
priv->lp_txpoll = wd_create(); /* Create periodic poll timer */
|
||||
priv->lp_txtimeout = wd_create(); /* Create TX timeout timer */
|
||||
|
||||
/* Perform minimal, one-time initialization -- just reset the controller and
|
||||
* leave it disabled. The Ethernet controller will be reset and properly
|
||||
* re-initialized each time lpc17_ifup() is called.
|
||||
*/
|
||||
|
||||
lpc17_ethreset(priv);
|
||||
lpc17_ifdown(&priv->lp_dev);
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
if (irq_attach(LPC17_IRQ_ETH, lpc17_interrupt))
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
ret = irq_attach(priv->irq, lpc17_interrupt);
|
||||
#else
|
||||
ret = irq_attach(LPC17_IRQ_ETH, lpc17_interrupt);
|
||||
#endif
|
||||
if (ret != 0)
|
||||
{
|
||||
/* We could not attach the ISR to the the interrupt */
|
||||
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* Initialize the driver structure */
|
||||
|
||||
memset(g_ethdrvr, 0, CONFIG_LPC17_NINTERFACES*sizeof(struct lpc17_driver_s));
|
||||
priv->lp_dev.d_ifup = lpc17_ifup; /* I/F down callback */
|
||||
priv->lp_dev.d_ifdown = lpc17_ifdown; /* I/F up (new IP address) callback */
|
||||
priv->lp_dev.d_txavail = lpc17_txavail; /* New TX data callback */
|
||||
#ifdef CONFIG_NET_IGMP
|
||||
priv->lp_dev.d_addmac = lpc17_addmac; /* Add multicast MAC address */
|
||||
priv->lp_dev.d_rmmac = lpc17_rmmac; /* Remove multicast MAC address */
|
||||
#endif
|
||||
priv->lp_dev.d_private = (void*)g_ethdrvr; /* Used to recover private state from dev */
|
||||
|
||||
/* Create a watchdog for timing polling for and timing of transmisstions */
|
||||
|
||||
priv->lp_txpoll = wd_create(); /* Create periodic poll timer */
|
||||
priv->lp_txtimeout = wd_create(); /* Create TX timeout timer */
|
||||
|
||||
/* Read the MAC address from the hardware into priv->lp_dev.d_mac.ether_addr_octet */
|
||||
|
||||
/* Register the device with the OS so that socket IOCTLs can be performed */
|
||||
|
||||
(void)netdev_register(&priv->lp_dev);
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@
|
|||
|
||||
#define ETH_MAC2_FD (1 << 0) /* Bit 0: Full duplex */
|
||||
#define ETH_MAC2_FLC (1 << 1) /* Bit 1: Frame length checking */
|
||||
#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge fram enable */
|
||||
#define ETH_MAC2_HFE (1 << 2) /* Bit 2: Huge frame enable */
|
||||
#define ETH_MAC2_DCRC (1 << 3) /* Bit 3: Delayed CRC */
|
||||
#define ETH_MAC2_CRCEN (1 << 4) /* Bit 4: CRC enable */
|
||||
#define ETH_MAC2_PADCRCEN (1 << 5) /* Bit 5: Pad/CRC enable */
|
||||
|
|
@ -238,7 +238,7 @@
|
|||
|
||||
#define ETH_MCFG_SCANINC (1 << 0) /* Bit 0: Scan increment */
|
||||
#define ETH_MCFG_SUPPRE (1 << 1) /* Bit 1: Suppress preamble */
|
||||
#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5:Clock select */
|
||||
#define ETH_MCFG_CLKSEL_SHIFT (2) /* Bits 2-5: Clock select */
|
||||
#define ETH_MCFG_CLKSEL_MASK (15 << ETH_MCFG_CLKSEL_SHIFT)
|
||||
# define ETH_MCFG_CLKSEL_DIV4 (0 << ETH_MCFG_CLKSEL_SHIFT)
|
||||
# define ETH_MCFG_CLKSEL_DIV6 (2 << ETH_MCFG_CLKSEL_SHIFT)
|
||||
|
|
@ -316,7 +316,7 @@
|
|||
|
||||
#define ETH_CMD_RXEN (1 << 0) /* Bit 0: Receive enable */
|
||||
#define ETH_CMD_TXEN (1 << 1) /* Bit 1: Transmit enable */
|
||||
/* Bit 2: Reserved */
|
||||
/* Bit 2: Reserved */
|
||||
#define ETH_CMD_REGRST (1 << 3) /* Bit 3: Reset host registers */
|
||||
#define ETH_CMD_TXRST (1 << 4) /* Bit 4: Reset transmit datapath */
|
||||
#define ETH_CMD_RXRST (1 << 5) /* Bit 5: Reset receive datapath */
|
||||
|
|
|
|||
|
|
@ -601,6 +601,14 @@ Olimex LPC1766-STK Configuration Options
|
|||
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
CONFIG_UARTn_2STOP - Two stop bits
|
||||
|
||||
|
||||
LPC17xx specific PHY/Ethernet device driver settings
|
||||
|
||||
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
|
||||
CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
|
||||
LPC17xx USB Configuration
|
||||
|
||||
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
|
||||
|
|
|
|||
|
|
@ -122,6 +122,11 @@
|
|||
#define CONFIG_LP17_FLASH 1
|
||||
#define BOARD_FLASHCFG_VALUE 0x0000303a
|
||||
|
||||
/* Ethernet configuration */
|
||||
|
||||
//#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV44
|
||||
#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
/* LED1 LED2 */
|
||||
|
|
|
|||
|
|
@ -181,6 +181,19 @@ CONFIG_UART1_2STOP=0
|
|||
CONFIG_UART2_2STOP=0
|
||||
CONFIG_UART3_2STOP=0
|
||||
|
||||
#
|
||||
# LPC17xx specific PHY/Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
|
||||
# CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
# CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
# CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
#
|
||||
CONFIG_PHY_KS8721=y
|
||||
CONFIG_PHY_AUTONEG=y
|
||||
CONFIG_PHY_SPEED100=n
|
||||
CONFIG_PHY_FDUPLEX=y
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
|||
|
|
@ -181,6 +181,19 @@ CONFIG_UART1_2STOP=0
|
|||
CONFIG_UART2_2STOP=0
|
||||
CONFIG_UART3_2STOP=0
|
||||
|
||||
#
|
||||
# LPC17xx specific PHY/Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
|
||||
# CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
# CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
# CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
#
|
||||
CONFIG_PHY_KS8721=y
|
||||
CONFIG_PHY_AUTONEG=y
|
||||
CONFIG_PHY_SPEED100=n
|
||||
CONFIG_PHY_FDUPLEX=y
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
|||
|
|
@ -181,6 +181,19 @@ CONFIG_UART1_2STOP=0
|
|||
CONFIG_UART2_2STOP=0
|
||||
CONFIG_UART3_2STOP=0
|
||||
|
||||
#
|
||||
# LPC17xx specific PHY/Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
|
||||
# CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
# CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
# CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
#
|
||||
CONFIG_PHY_KS8721=y
|
||||
CONFIG_PHY_AUTONEG=y
|
||||
CONFIG_PHY_SPEED100=n
|
||||
CONFIG_PHY_FDUPLEX=y
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
|||
|
|
@ -181,6 +181,19 @@ CONFIG_UART1_2STOP=0
|
|||
CONFIG_UART2_2STOP=0
|
||||
CONFIG_UART3_2STOP=0
|
||||
|
||||
#
|
||||
# LPC17xx specific PHY/Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
|
||||
# CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
# CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
# CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
#
|
||||
CONFIG_PHY_KS8721=y
|
||||
CONFIG_PHY_AUTONEG=y
|
||||
CONFIG_PHY_SPEED100=n
|
||||
CONFIG_PHY_FDUPLEX=y
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
|||
|
|
@ -181,6 +181,19 @@ CONFIG_UART1_2STOP=0
|
|||
CONFIG_UART2_2STOP=0
|
||||
CONFIG_UART3_2STOP=0
|
||||
|
||||
#
|
||||
# LPC17xx specific PHY/Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
|
||||
# CONFIG_PHY_AUTONEG - Enable auto-negotion
|
||||
# CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
|
||||
# CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
|
||||
#
|
||||
CONFIG_PHY_KS8721=y
|
||||
CONFIG_PHY_AUTONEG=y
|
||||
CONFIG_PHY_SPEED100=n
|
||||
CONFIG_PHY_FDUPLEX=y
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
|
|
|||
|
|
@ -305,7 +305,7 @@
|
|||
|
||||
/* LM3S6918 LED Configuration, address 0x17 */
|
||||
|
||||
#define LM3S_LEDCONFIG_LED0_SHIFT 0 /* Bits 3-0: LED0 Source */
|
||||
#define LM3S_LEDCONFIG_LED0_SHIFT (0) /* Bits 3-0: LED0 Source */
|
||||
#define LM3S_LEDCONFIG_LED0_MASK (0x0f << LM3S_LEDCONFIG_LED0_SHIFT)
|
||||
#define LM3S_LEDCONFIG_LED0_LINKOK (0 << LM3S_LEDCONFIG_LED0_SHIFT) /* Link OK */
|
||||
#define LM3S_LEDCONFIG_LED0_RXTX (1 << LM3S_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */
|
||||
|
|
@ -313,7 +313,7 @@
|
|||
#define LM3S_LEDCONFIG_LED0_10BASET (6 << LM3S_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */
|
||||
#define LM3S_LEDCONFIG_LED0_FDUPLEX (7 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED0_OKRXTX (8 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED1_SHIFT 4 /* Bits 7-4: LED1 Source */
|
||||
#define LM3S_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */
|
||||
#define LM3S_LEDCONFIG_LED1_MASK (0x0f << LM3S_LEDCONFIG_LED1_SHIFT)
|
||||
#define LM3S_LEDCONFIG_LED1_LINKOK (0 << LM3S_LEDCONFIG_LED1_SHIFT) /* Link OK */
|
||||
#define LM3S_LEDCONFIG_LED1_RXTX (1 << LM3S_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */
|
||||
|
|
@ -324,7 +324,7 @@
|
|||
|
||||
/* LM3S6918 MDI/MDIX Control, address 0x18 */
|
||||
|
||||
#define LM3S_MDICONTROL_MDIXSD_SHIFT 0 /* Bits 3-0: Auto-Switching Seed */
|
||||
#define LM3S_MDICONTROL_MDIXSD_SHIFT (0) /* Bits 3-0: Auto-Switching Seed */
|
||||
#define LM3S_MDICONTROL_MDIXSD_MASK (0x0f << LM3S_MDICONTROL_MDIXSD_SHIFT)
|
||||
#define LM3S_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */
|
||||
#define LM3S_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */
|
||||
|
|
|
|||
Loading…
Reference in New Issue