Add LPC43xx CGU and CCU header files
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4883 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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/****************************************************************************************************
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* arch/arm/src/lpc43xx/chip/lpc43_ccu.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define LPC43_CCU1_PM_OFFSET 0x0000 /* CCU1 power mode register */
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#define LPC43_CCU1_BASE_STAT_OFFSET 0x0004 /* CCU1 base clock status register */
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#define LPC43_CCU1_APB3_BUS_CFG_OFFSET 0x0100 /* CLK_APB3_BUS clock configuration register */
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#define LPC43_CCU1_APB3_BUS_STAT_OFFSET 0x0104 /* CLK_APB3_BUS clock status register */
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#define LPC43_CCU1_APB3_I2C1_CFG_OFFSET 0x0108 /* CLK_APB3_I2C1 configuration register */
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#define LPC43_CCU1_APB3_I2C1_STAT_OFFSET 0x010c /* CLK_APB3_I2C1 status register */
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#define LPC43_CCU1_APB3_DAC_CFG_OFFSET 0x0110 /* CLK_APB3_DAC configuration register */
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#define LPC43_CCU1_APB3_DAC_STAT_OFFSET 0x0114 /* CLK_APB3_DAC status register */
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#define LPC43_CCU1_APB3_ADC0_CFG_OFFSET 0x0118 /* CLK_APB3_ADC0 configuration register */
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#define LPC43_CCU1_APB3_ADC0_STAT_OFFSET 0x011c /* CLK_APB3_ADC0 status register */
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#define LPC43_CCU1_APB3_ADC1_CFG_OFFSET 0x0120 /* CLK_APB3_ADC1 configuration register */
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#define LPC43_CCU1_APB3_ADC1_STAT_OFFSET 0x0124 /* CLK_APB3_ADC1 status register */
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#define LPC43_CCU1_APB3_CAN0_CFG_OFFSET 0x0128 /* CLK_APB3_CAN0 configuration register */
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#define LPC43_CCU1_APB3_CAN0_STAT_OFFSET 0x012c /* CLK_APB3_CAN0 status register */
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#define LPC43_CCU1_APB1_BUS_CFG_OFFSET 0x0200 /* CLK_APB1_BUS configuration register */
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#define LPC43_CCU1_APB1_BUS_STAT_OFFSET 0x0204 /* CLK_APB1_BUS status register */
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#define LPC43_CCU1_APB1_MCPWM_CFG_OFFSET 0x0208 /* CLK_APB1_MOTOCON configuration register */
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#define LPC43_CCU1_APB1_MCPWM_STAT_OFFSET 0x020c /* CLK_APB1_MOTOCON status register */
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#define LPC43_CCU1_APB1_I2C0_CFG_OFFSET 0x0210 /* CLK_APB1_I2C0 configuration register */
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#define LPC43_CCU1_APB1_I2C0_STAT_OFFSET 0x0214 /* CLK_APB1_I2C0 status register */
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#define LPC43_CCU1_APB1_I2S_CFG_OFFSET 0x0218 /* CLK_APB1_I2S configuration register */
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#define LPC43_CCU1_APB1_I2S_STAT_OFFSET 0x021c /* CLK_APB1_I2S status register */
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#define LPC43_CCU1_APB1_CAN1_CFG_OFFSET 0x0220 /* CLK_APB3_CAN1 configuration register */
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#define LPC43_CCU1_APB1_CAN1_STAT_OFFSET 0x0224 /* CLK_APB3_CAN1 status register */
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#define LPC43_CCU1_SPIFI_CFG_OFFSET 0x0300 /* CLK_SPIFI configuration register */
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#define LPC43_CCU1_SPIFI_STAT_OFFSET 0x0304 /* CLK_SPIFI status register */
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#define LPC43_CCU1_M4_BUS_CFG_OFFSET 0x0400 /* CLK_M4_BUS configuration register */
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#define LPC43_CCU1_M4_BUS_STAT_OFFSET 0x0404 /* CLK_M4_BUS status register */
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#define LPC43_CCU1_M4_SPIFI_CFG_OFFSET 0x0408 /* CLK_M4_SPIFI configuration register */
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#define LPC43_CCU1_M4_SPIFI_STAT_OFFSET 0x040c /* CLK_M4_SPIFI status register */
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#define LPC43_CCU1_M4_GPIO_CFG_OFFSET 0x0410 /* CLK_M4_GPIO configuration register */
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#define LPC43_CCU1_M4_GPIO_STAT_OFFSET 0x0414 /* CLK_M4_GPIO status register */
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#define LPC43_CCU1_M4_LCD_CFG_OFFSET 0x0418 /* CLK_M4_LCD configuration register */
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#define LPC43_CCU1_M4_LCD_STAT_OFFSET 0x041c /* CLK_M4_LCD status register */
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#define LPC43_CCU1_M4_ETHERNET_CFG_OFFSET 0x0420 /* CLK_M4_ETHERNET configuration register */
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#define LPC43_CCU1_M4_ETHERNET_STAT_OFFSET 0x0424 /* CLK_M4_ETHERNET status register */
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#define LPC43_CCU1_M4_USB0_CFG_OFFSET 0x0428 /* CLK_M4_USB0 configuration register */
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#define LPC43_CCU1_M4_USB0_STAT_OFFSET 0x042c /* CLK_M4_USB0 status register */
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#define LPC43_CCU1_M4_EMC_CFG_OFFSET 0x0430 /* CLK_M4_EMC configuration register */
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#define LPC43_CCU1_M4_EMC_STAT_OFFSET 0x0434 /* CLK_M4_EMC status register */
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#define LPC43_CCU1_M4_SDIO_CFG_OFFSET 0x0438 /* CLK_M4_SDIO configuration register */
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#define LPC43_CCU1_M4_SDIO_STAT_OFFSET 0x043c /* CLK_M4_SDIO status register */
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#define LPC43_CCU1_M4_DMA_CFG_OFFSET 0x0440 /* CLK_M4_DMA configuration register */
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#define LPC43_CCU1_M4_DMA_STAT_OFFSET 0x0444 /* CLK_M4_DMA status register */
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#define LPC43_CCU1_M4_M4CORE_CFG_OFFSET 0x0448 /* CLK_M4_M4CORE configuration register */
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#define LPC43_CCU1_M4_M4CORE_STAT_OFFSET 0x044c /* CLK_M4_M4CORE status register */
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#define LPC43_CCU1_M4_SCT_CFG_OFFSET 0x0468 /* CLK_M4_SCT configuration register */
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#define LPC43_CCU1_M4_SCT_STAT_OFFSET 0x046c /* CLK_M4_SCT status register */
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#define LPC43_CCU1_M4_USB1_CFG_OFFSET 0x0470 /* CLK_M4_USB1 configuration register */
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#define LPC43_CCU1_M4_USB1_STAT_OFFSET 0x0474 /* CLK_M4_USB1 status register */
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#define LPC43_CCU1_M4_EMCDIV_CFG_OFFSET 0x0478 /* CLK_M4_EMCDIV configuration register */
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#define LPC43_CCU1_M4_EMCDIV_STAT_OFFSET 0x047c /* CLK_M4_EMCDIV status register */
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#define LPC43_CCU1_M4_FLASHA_CFG_OFFSET 0x0480 /* CLK_M4_FLASHA configuration register */
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#define LPC43_CCU1_M4_FLASHA_STAT_OFFSET 0x0484 /* CLK_M4_FLASHA status register */
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#define LPC43_CCU1_M4_FLASHB_CFG_OFFSET 0x0488 /* CLK_M4_FLASHB configuration register */
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#define LPC43_CCU1_M4_FLASHB_STAT_OFFSET 0x048c /* CLK_M4_FLASHB status register */
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#define LPC43_CCU1_M4_M0APP_CFG_OFFSET 0x0490 /* CLK_M4_M0_CFG configuration register */
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#define LPC43_CCU1_M4_M0APP_STAT_OFFSET 0x0494 /* CLK_M4_M0_STAT status register */
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#define LPC43_CCU1_M4_VADC_CFG_OFFSET 0x0498 /* CLK_M4_VADC_CFG configuration register */
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#define LPC43_CCU1_M4_VADC_STAT_OFFSET 0x049c /* CLK_M4_VADC_STAT configuration register */
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#define LPC43_CCU1_M4_EEPROM_CFG_OFFSET 0x04a0 /* CLK_M4_EEPROM configuration register */
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#define LPC43_CCU1_M4_EEPROM_STAT_OFFSET 0x04a4 /* CLK_M4_EEPROM status register */
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#define LPC43_CCU1_M4_WWDT_CFG_OFFSET 0x0500 /* CLK_M4_WWDT configuration register */
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#define LPC43_CCU1_M4_WWDT_STAT_OFFSET 0x0504 /* CLK_M4_WWDT status register */
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#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_UART0 configuration register */
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#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_UART0 status register */
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#define LPC43_CCU1_M4_UART1_CFG_OFFSET 0x0510 /* CLK_M4_UART1 configuration register */
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#define LPC43_CCU1_M4_UART1_STAT_OFFSET 0x0514 /* CLK_M4_UART1 status register */
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#define LPC43_CCU1_M4_SSP0_CFG_OFFSET 0x0518 /* CLK_M4_SSP0 configuration register */
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#define LPC43_CCU1_M4_SSP0_STAT_OFFSET 0x051c /* CLK_M4_SSP0 status register */
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#define LPC43_CCU1_M4_TIMER0_CFG_OFFSET 0x0520 /* CLK_M4_TIMER0 configuration register */
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#define LPC43_CCU1_M4_TIMER0_STAT_OFFSET 0x0524 /* CLK_M4_TIMER0 status register */
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#define LPC43_CCU1_M4_TIMER1_CFG_OFFSET 0x0528 /* CLK_M4_TIMER1 configuration register */
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#define LPC43_CCU1_M4_TIMER1_STAT_OFFSET 0x052c /* CLK_M4_TIMER1 status register */
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#define LPC43_CCU1_M4_SCU_CFG_OFFSET 0x0530 /* CLK_M4_SCU configuration register */
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#define LPC43_CCU1_M4_SCU_STAT_OFFSET 0x0534 /* CLK_M4_SCU status register */
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#define LPC43_CCU1_M4_CREG_CFG_OFFSET 0x0538 /* CLK_M4_CREG configuration register */
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#define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */
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#define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */
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#define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */
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#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_UART2 configuration register */
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#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_UART2 status register */
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#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_UART3 configuration register */
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#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_UART3 status register */
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#define LPC43_CCU1_M4_TIMER2_CFG_OFFSET 0x0618 /* CLK_M4_TIMER2 configuration register */
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#define LPC43_CCU1_M4_TIMER2_STAT_OFFSET 0x061c /* CLK_M4_TIMER2 status register */
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#define LPC43_CCU1_M4_TIMER3_CFG_OFFSET 0x0620 /* CLK_M4_TIMER3 configuration register */
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#define LPC43_CCU1_M4_TIMER3_STAT_OFFSET 0x0624 /* CLK_M4_TIMER3 status register */
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#define LPC43_CCU1_M4_SSP1_CFG_OFFSET 0x0628 /* CLK_M4_SSP1 configuration register */
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#define LPC43_CCU1_M4_SSP1_STAT_OFFSET 0x062c /* CLK_M4_SSP1 status register */
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#define LPC43_CCU1_M4_QEI_CFG_OFFSET 0x0630 /* CLK_M4_QEI configuration register */
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#define LPC43_CCU1_M4_QEI_STAT_OFFSET 0x0634 /* CLK_M4_QEI status register */
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#define LPC43_CCU1_PERIPH_BUS_CFG_OFFSET 0x0700 /* CLK_PERIPH_BUS configuration register */
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#define LPC43_CCU1_PERIPH_BUS_STAT_OFFSET 0x0704 /* CLK_PERIPH_BUS status register */
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#define LPC43_CCU1_PERIPH_CORE_CFG_OFFSET 0x0710 /* CLK_PERIPH_CORE configuration register */
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#define LPC43_CCU1_PERIPH_CORE_STAT_OFFSET 0x0714 /* CLK_PERIPH_CORE status register */
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#define LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET 0x0718 /* CLK_PERIPH_SGPIO configuration register */
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#define LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET 0x071c /* CLK_PERIPH_SGPIO status register */
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#define LPC43_CCU1_USB0_CFG_OFFSET 0x0800 /* CLK_USB0 configuration register */
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#define LPC43_CCU1_USB0_STAT_OFFSET 0x0804 /* CLK_USB0 status register */
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#define LPC43_CCU1_USB1_CFG_OFFSET 0x0900 /* CLK_USB1 configuration register */
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#define LPC43_CCU1_USB1_STAT_OFFSET 0x0904 /* CLK_USB1 status register */
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#define LPC43_CCU1_SPI_CFG_OFFSET 0x0a00 /* CLK_SPI configuration register */
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#define LPC43_CCU1_SPI_STAT_OFFSET 0x0a04 /* CLK_SPI status register */
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#define LPC43_CCU1_VADC_CFG_OFFSET 0x0b00 /* CLK_VADC configuration register */
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#define LPC43_CCU1_VADC_STAT_OFFSET 0x0b04 /* CLK_VADC status register */
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#define LPC43_CCU2_PM_OFFSET 0x0000 /* CCU2 power mode register */
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#define LPC43_CCU2_BASE_STAT_OFFSET 0x0004 /* CCU2 base clocks status register */
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#define LPC43_CCU2_APLL_CFG_OFFSET 0x0100 /* CLK_APLL configuration register */
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#define LPC43_CCU2_APLL_STAT_OFFSET 0x0104 /* CLK_APLL status register */
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#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_UART3 configuration register */
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#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_UART3 status register */
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#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_UART2 configuration register */
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#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_UART2 status register */
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#define LPC43_CCU2_APB0_UART1_CFG_OFFSET 0x0400 /* CLK_APB0_UART1 configuration register */
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#define LPC43_CCU2_APB0_UART1_STAT_OFFSET 0x0404 /* CLK_APB0_UART1 status register */
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#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_UART0 configuration register */
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#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_UART0 status register */
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#define LPC43_CCU2_APB2_SSP1_CFG_OFFSET 0x0600 /* CLK_APB2_SSP1 configuration register */
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#define LPC43_CCU2_APB2_SSP1_STAT_OFFSET 0x0604 /* CLK_APB2_SSP1 status register */
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#define LPC43_CCU2_APB0_SSP0_CFG_OFFSET 0x0700 /* CLK_APB0_SSP0 configuration register */
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#define LPC43_CCU2_APB0_SSP0_STAT_OFFSET 0x0704 /* CLK_APB0_SSP0 status register */
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#define LPC43_CCU2_SDIO_CFG_OFFSET 0x0800 /* CLK_SDIO configuration register (for SD/MMC) */
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#define LPC43_CCU2_SDIO_STAT_OFFSET 0x0804 /* CLK_SDIO status register (for SD/MMC) */
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/* Register Addresses *******************************************************************************/
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#define LPC43_CCU1_PM (LPC43_CCU1_BASE+LPC43_CCU1_PM_OFFSET)
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#define LPC43_CCU1_BASE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_BASE_STAT_OFFSET)
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#define LPC43_CCU1_APB3_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_CFG_OFFSET)
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#define LPC43_CCU1_APB3_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_BUS_STAT_OFFSET)
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#define LPC43_CCU1_APB3_I2C1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_CFG_OFFSET)
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#define LPC43_CCU1_APB3_I2C1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_I2C1_STAT_OFFSET)
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#define LPC43_CCU1_APB3_DAC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_CFG_OFFSET)
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#define LPC43_CCU1_APB3_DAC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_DAC_STAT_OFFSET)
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#define LPC43_CCU1_APB3_ADC0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_CFG_OFFSET)
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#define LPC43_CCU1_APB3_ADC0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC0_STAT_OFFSET)
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#define LPC43_CCU1_APB3_ADC1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_CFG_OFFSET)
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#define LPC43_CCU1_APB3_ADC1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_ADC1_STAT_OFFSET)
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#define LPC43_CCU1_APB3_CAN0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_CFG_OFFSET)
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#define LPC43_CCU1_APB3_CAN0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB3_CAN0_STAT_OFFSET)
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#define LPC43_CCU1_APB1_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_CFG_OFFSET)
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#define LPC43_CCU1_APB1_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_BUS_STAT_OFFSET)
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#define LPC43_CCU1_APB1_MCPWM_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_CFG_OFFSET)
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#define LPC43_CCU1_APB1_MCPWM_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_MCPWM_STAT_OFFSET)
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#define LPC43_CCU1_APB1_I2C0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_CFG_OFFSET)
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#define LPC43_CCU1_APB1_I2C0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2C0_STAT_OFFSET)
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#define LPC43_CCU1_APB1_I2S_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_CFG_OFFSET)
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#define LPC43_CCU1_APB1_I2S_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_I2S_STAT_OFFSET)
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#define LPC43_CCU1_APB1_CAN1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_CFG_OFFSET)
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#define LPC43_CCU1_APB1_CAN1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_APB1_CAN1_STAT_OFFSET)
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#define LPC43_CCU1_SPIFI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_CFG_OFFSET)
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#define LPC43_CCU1_SPIFI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_SPIFI_STAT_OFFSET)
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#define LPC43_CCU1_M4_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_CFG_OFFSET)
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#define LPC43_CCU1_M4_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_BUS_STAT_OFFSET)
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#define LPC43_CCU1_M4_SPIFI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_SPIFI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SPIFI_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_GPIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_GPIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_GPIO_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_LCD_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_LCD_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_LCD_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_ETHERNET_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_ETHERNET_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_ETHERNET_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_USB0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_USB0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB0_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_EMC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_EMC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMC_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_SDIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_SDIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SDIO_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_DMA_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_DMA_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_DMA_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_M4CORE_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_M4CORE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_M4CORE_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_SCT_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_SCT_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCT_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_USB1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_USB1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USB1_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_EMCDIV_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_EMCDIV_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EMCDIV_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_FLASHA_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_FLASHA_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHA_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_FLASHB_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_FLASHB_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_FLASHB_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_M0APP_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_M0APP_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_M0APP_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_VADC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_VADC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_VADC_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_EEPROM_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_EEPROM_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_EEPROM_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_WWDT_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_WWDT_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_WWDT_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_USART0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_USART0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART0_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_UART1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_UART1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_UART1_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_SSP0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_SSP0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP0_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER0_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER1_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_SCU_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_SCU_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SCU_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_CREG_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_CREG_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_CREG_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_RITIMER_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_RITIMER_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_RITIMER_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_USART2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_USART2_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART2_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_USART3_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_USART3_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_USART3_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER2_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER2_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER2_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER3_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_TIMER3_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_TIMER3_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_SSP1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_SSP1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_SSP1_STAT_OFFSET)
|
||||
#define LPC43_CCU1_M4_QEI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_CFG_OFFSET)
|
||||
#define LPC43_CCU1_M4_QEI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_M4_QEI_STAT_OFFSET)
|
||||
#define LPC43_CCU1_PERIPH_BUS_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_CFG_OFFSET)
|
||||
#define LPC43_CCU1_PERIPH_BUS_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_BUS_STAT_OFFSET)
|
||||
#define LPC43_CCU1_PERIPH_CORE_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_CFG_OFFSET)
|
||||
#define LPC43_CCU1_PERIPH_CORE_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_CORE_STAT_OFFSET)
|
||||
#define LPC43_CCU1_PERIPH_SGPIO_CFG (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_CFG_OFFSET)
|
||||
#define LPC43_CCU1_PERIPH_SGPIO_STAT (LPC43_CCU1_BASE+LPC43_CCU1_PERIPH_SGPIO_STAT_OFFSET)
|
||||
#define LPC43_CCU1_USB0_CFG (LPC43_CCU1_BASE+LPC43_CCU1_USB0_CFG_OFFSET)
|
||||
#define LPC43_CCU1_USB0_STAT (LPC43_CCU1_BASE+LPC43_CCU1_USB0_STAT_OFFSET)
|
||||
#define LPC43_CCU1_USB1_CFG (LPC43_CCU1_BASE+LPC43_CCU1_USB1_CFG_OFFSET)
|
||||
#define LPC43_CCU1_USB1_STAT (LPC43_CCU1_BASE+LPC43_CCU1_USB1_STAT_OFFSET)
|
||||
#define LPC43_CCU1_SPI_CFG (LPC43_CCU1_BASE+LPC43_CCU1_SPI_CFG_OFFSET)
|
||||
#define LPC43_CCU1_SPI_STAT (LPC43_CCU1_BASE+LPC43_CCU1_SPI_STAT_OFFSET)
|
||||
#define LPC43_CCU1_VADC_CFG (LPC43_CCU1_BASE+LPC43_CCU1_VADC_CFG_OFFSET)
|
||||
#define LPC43_CCU1_VADC_STAT (LPC43_CCU1_BASE+LPC43_CCU1_VADC_STAT_OFFSET)
|
||||
|
||||
#define LPC43_CCU2_PM (LPC43_CCU2_BASE+LPC43_CCU2_PM_OFFSET)
|
||||
#define LPC43_CCU2_BASE_STAT (LPC43_CCU2_BASE+LPC43_CCU2_BASE_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APLL_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APLL_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APLL_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APLL_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APB2_USART3_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APB2_USART3_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART3_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APB2_USART2_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APB2_USART2_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_USART2_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APB0_UART1_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APB0_UART1_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_UART1_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APB0_USART0_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APB0_USART0_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_USART0_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APB2_SSP1_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APB2_SSP1_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB2_SSP1_STAT_OFFSET)
|
||||
#define LPC43_CCU2_APB0_SSP0_CFG (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_CFG_OFFSET)
|
||||
#define LPC43_CCU2_APB0_SSP0_STAT (LPC43_CCU2_BASE+LPC43_CCU2_APB0_SSP0_STAT_OFFSET)
|
||||
#define LPC43_CCU2_SDIO_CFG (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_CFG_OFFSET)
|
||||
#define LPC43_CCU2_SDIO_STAT (LPC43_CCU2_BASE+LPC43_CCU2_SDIO_STAT_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *************************************************************************/
|
||||
|
||||
/* CCU1/2 Power Mode Register */
|
||||
|
||||
#define CCU_PM_PD (1 << 0) /* Bit 0: Initiate power-down mode */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* CCU1 Base Clock Status Register */
|
||||
|
||||
#define CCU1_BASE_STAT_AB3 (1 << 0) /* Bit 0: Base clock indicator for BASE_APB3_CLK */
|
||||
#define CCU1_BASE_STAT_APB1 (1 << 1) /* Bit 1: Base clock indicator for BASE_APB1_CLK */
|
||||
#define CCU1_BASE_STAT_SPIFI (1 << 2) /* Bit 2: Base clock indicator for BASE_SPIFI_CLK */
|
||||
#define CCU1_BASE_STAT_M4 (1 << 3) /* Bit 3: Base clock indicator for BASE_M4_CLK */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define CCU1_BASE_STAT_PERIPH (1 << 6) /* Bit 6: Base clock indicator for BASE_PERIPH_CLK */
|
||||
#define CCU1_BASE_STAT_USB0 (1 << 7) /* Bit 7: Base clock indicator for BASE_USB0_CLK */
|
||||
#define CCU1_BASE_STAT_USB1 (1 << 8) /* Bit 8: Base clock indicator for BASE_USB1_CLK */
|
||||
#define CCU1_BASE_STAT_SPI (1 << 9) /* Bit 9: Base clock indicator for BASE_SPI_CLK */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* CCU2 Base Clock Status Register */
|
||||
/* Bit 0: Reserved */
|
||||
#define CCU2_BASE_STAT_UART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_UART3_CLK */
|
||||
#define CCU2_BASE_STAT_UART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_UART2_CLK */
|
||||
#define CCU2_BASE_STAT_UART1 (1 << 3) /* Bit 3: Base clock indicator for BASE_UART1_CLK */
|
||||
#define CCU2_BASE_STAT_UART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_UART0_CLK */
|
||||
#define CCU2_BASE_STAT_SSP1 (1 << 5) /* Bit 5: Base clock indicator for BASE_SSP1_CLK */
|
||||
#define CCU2_BASE_STAT_SSP0 (1 << 6) /* Bit 6: Base clock indicator for BASE_SSP0_CLK */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* CCU1/2 Branch Clock Configuration/Status Registers */
|
||||
|
||||
#define CCU_CLK_CFG_RUN (1 << 0) /* Bit 0: Run enable */
|
||||
#define CCU_CLK_CFG_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable */
|
||||
#define CCU_CLK_CFG_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable */
|
||||
/* Bits 3-31: Reserved */
|
||||
/* CCU1/2 Branch Clock Status Registers */
|
||||
|
||||
#define CCU_CLK_STAT_RUN (1 << 0) /* Bit 0: Run enable status */
|
||||
#define CCU_CLK_STAT_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable status */
|
||||
#define CCU_CLK_STAT_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable status */
|
||||
/* Bits 3-31: Reserved */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H */
|
||||
|
|
@ -0,0 +1,843 @@
|
|||
/****************************************************************************************************
|
||||
* arch/arm/src/lpc43xx/chip/lpc43_cgu.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H
|
||||
#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define LPC43_FREQ_MON_OFFSET 0x014 /* Frequency monitor register */
|
||||
#define LPC43_XTAL_OSC_CTRL_OFFSET 0x018 /* Crystal oscillator control register */
|
||||
#define LPC43_PLL0USB_STAT_OFFSET 0x01c /* PLL0USB status register */
|
||||
#define LPC43_PLL0USB_CTRL_OFFSET 0x020 /* PLL0USB control register */
|
||||
#define LPC43_PLL0USB_MDIV_OFFSET 0x024 /* PLL0USB M-divider register */
|
||||
#define LPC43_PLL0USB_NP_DIV_OFFSET 0x028 /* PLL0USB N/P-divider register */
|
||||
#define LPC43_PLL0AUDIO_STAT_OFFSET 0x02c /* PLL0AUDIO status register */
|
||||
#define LPC43_PLL0AUDIO_CTRL_OFFSET 0x030 /* PLL0AUDIO control register */
|
||||
#define LPC43_PLL0AUDIO_MDIV_OFFSET 0x034 /* PLL0AUDIO M-divider */
|
||||
#define LPC43_PLL0AUDIO_NP_DIV_OFFSET 0x038 /* PLL0AUDIO N/P-divider */
|
||||
#define LPC43_PLL0AUDIO_FRAC_OFFSET 0x03c /* PLL0AUDIO fractional */
|
||||
#define LPC43_PLL1_STAT_OFFSET 0x040 /* PLL1 status register */
|
||||
#define LPC43_PLL1_CTRL_OFFSET 0x044 /* PLL1 control register */
|
||||
#define LPC43_IDIVA_CTRL_OFFSET 0x048 /* Integer divider A control register */
|
||||
#define LPC43_IDIVB_CTRL_OFFSET 0x04c /* Integer divider B control register */
|
||||
#define LPC43_IDIVC_CTRL_OFFSET 0x050 /* Integer divider C control register */
|
||||
#define LPC43_IDIVD_CTRL_OFFSET 0x054 /* Integer divider D control register */
|
||||
#define LPC43_IDIVE_CTRL_OFFSET 0x058 /* Integer divider E control register */
|
||||
#define LPC43_BASE_SAFE_CLK_OFFSET 0x05c /* Output stage 0 control register (BASE_SAFE_CLK) */
|
||||
#define LPC43_BASE_USB0_CLK_OFFSET 0x060 /* Output stage 1 control register (BASE_USB0_CLK) */
|
||||
#define LPC43_BASE_PERIPH_CLK_OFFSET 0x064 /* Output stage 2 control register (BASE_PERIPH_CLK) */
|
||||
#define LPC43_BASE_USB1_CLK_OFFSET 0x068 /* Output stage 3 control register (BASE_USB1_CLK) */
|
||||
#define LPC43_BASE_M4_CLK_OFFSET 0x06c /* Output stage 4 control register (BASE_M4_CLK) */
|
||||
#define LPC43_BASE_SPIFI_CLK_OFFSET 0x070 /* Output stage 5 control register (BASE_SPIFI_CLK) */
|
||||
#define LPC43_BASE_SPI_CLK_OFFSET 0x074 /* Output stage 6 control register (BASE_SPI_CLK) */
|
||||
#define LPC43_BASE_PHYRX_CLK_OFFSET 0x078 /* Output stage 7 control register (BASE_PHY_RX_CLK) */
|
||||
#define LPC43_BASE_PHYTX_CLK_OFFSET 0x07c /* Output stage 8 control register (BASE_PHY_TX_CLK) */
|
||||
#define LPC43_BASE_APB1_CLK_OFFSET 0x080 /* Output stage 9 control register (BASE_APB1_CLK) */
|
||||
#define LPC43_BASE_APB3_CLK_OFFSET 0x084 /* Output stage 10 control register (BASE_APB3_CLK) */
|
||||
#define LPC43_BASE_LCD_CLK_OFFSET 0x088 /* Output stage 11 control register (BASE_LCD_CLK) */
|
||||
#define LPC43_BASE_VADC_CLK_OFFSET 0x08c /* Output stage 12 control register (BASE_VADC_CLK) */
|
||||
#define LPC43_BASE_SDIO_CLK_OFFSET 0x090 /* Output stage 13 control register (BASE_SDIO_CLK) */
|
||||
#define LPC43_BASE_SSP0_CLK_OFFSET 0x094 /* Output stage 14 control register (BASE_SSP0_CLK) */
|
||||
#define LPC43_BASE_SSP1_CLK_OFFSET 0x098 /* Output stage 15 control register (BASE_SSP1_CLK) */
|
||||
#define LPC43_BASE_UART0_CLK_OFFSET 0x09c /* Output stage 16 control register (BASE_UART0_CLK) */
|
||||
#define LPC43_BASE_UART1_CLK_OFFSET 0x0a0 /* Output stage 17 control register (BASE_UART1_CLK) */
|
||||
#define LPC43_BASE_UART2_CLK_OFFSET 0x0a4 /* Output stage 18 control register (BASE_UART2_CLK) */
|
||||
#define LPC43_BASE_UART3_CLK_OFFSET 0x0a8 /* Output stage 19 control register (BASE_UART3_CLK) */
|
||||
#define LPC43_BASE_OUT_CLK_OFFSET 0x0ac /* Output stage 20 control register (BASE_OUT_CLK) */
|
||||
#define LPC43_BASE_APLL_CLK_OFFSET 0x0c0 /* Output stage 25 control register (BASE_APLL_CLK) */
|
||||
#define LPC43_BASE_CGU_OUT0_CLK_OFFSET 0x0c4 /* Output stage 26 control register (BASE_CGU_OUT0_CLK) */
|
||||
#define LPC43_BASE_CGU_OUT1_CLK_OFFSET 0x0c8 /* Output stage 27 control register (BASE_CGU_OUT1_CLK) */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define LPC43_FREQ_MON (LPC43_CGU_BASE+LPC43_FREQ_MON_OFFSET)
|
||||
#define LPC43_XTAL_OSC_CTRL (LPC43_CGU_BASE+LPC43_XTAL_OSC_CTRL_OFFSET)
|
||||
#define LPC43_PLL0USB_STAT (LPC43_CGU_BASE+LPC43_PLL0USB_STAT_OFFSET)
|
||||
#define LPC43_PLL0USB_CTRL (LPC43_CGU_BASE+LPC43_PLL0USB_CTRL_OFFSET)
|
||||
#define LPC43_PLL0USB_MDIV (LPC43_CGU_BASE+LPC43_PLL0USB_MDIV_OFFSET)
|
||||
#define LPC43_PLL0USB_NP_DIV (LPC43_CGU_BASE+LPC43_PLL0USB_NP_DIV_OFFSET)
|
||||
#define LPC43_PLL0AUDIO_STAT (LPC43_CGU_BASE+LPC43_PLL0AUDIO_STAT_OFFSET)
|
||||
#define LPC43_PLL0AUDIO_CTRL (LPC43_CGU_BASE+LPC43_PLL0AUDIO_CTRL_OFFSET)
|
||||
#define LPC43_PLL0AUDIO_MDIV (LPC43_CGU_BASE+LPC43_PLL0AUDIO_MDIV_OFFSET)
|
||||
#define LPC43_PLL0AUDIO_NP_DIV (LPC43_CGU_BASE+LPC43_PLL0AUDIO_NP_DIV_OFFSET)
|
||||
#define LPC43_PLL0AUDIO_FRAC (LPC43_CGU_BASE+LPC43_PLL0AUDIO_FRAC_OFFSET)
|
||||
#define LPC43_PLL1_STAT (LPC43_CGU_BASE+LPC43_PLL1_STAT_OFFSET)
|
||||
#define LPC43_PLL1_CTRL (LPC43_CGU_BASE+LPC43_PLL1_CTRL_OFFSET)
|
||||
#define LPC43_IDIVA_CTRL (LPC43_CGU_BASE+LPC43_IDIVA_CTRL_OFFSET)
|
||||
#define LPC43_IDIVB_CTRL (LPC43_CGU_BASE+LPC43_IDIVB_CTRL_OFFSET)
|
||||
#define LPC43_IDIVC_CTRL (LPC43_CGU_BASE+LPC43_IDIVC_CTRL_OFFSET)
|
||||
#define LPC43_IDIVD_CTRL (LPC43_CGU_BASE+LPC43_IDIVD_CTRL_OFFSET)
|
||||
#define LPC43_IDIVE_CTRL (LPC43_CGU_BASE+LPC43_IDIVE_CTRL_OFFSET)
|
||||
#define LPC43_BASE_SAFE_CLK (LPC43_CGU_BASE+LPC43_BASE_SAFE_CLK_OFFSET)
|
||||
#define LPC43_BASE_USB0_CLK (LPC43_CGU_BASE+LPC43_BASE_USB0_CLK_OFFSET)
|
||||
#define LPC43_BASE_PERIPH_CLK (LPC43_CGU_BASE+LPC43_BASE_PERIPH_CLK_OFFSET)
|
||||
#define LPC43_BASE_USB1_CLK (LPC43_CGU_BASE+LPC43_BASE_USB1_CLK_OFFSET)
|
||||
#define LPC43_BASE_M4_CLK (LPC43_CGU_BASE+LPC43_BASE_M4_CLK_OFFSET)
|
||||
#define LPC43_BASE_SPIFI_CLK (LPC43_CGU_BASE+LPC43_BASE_SPIFI_CLK_OFFSET)
|
||||
#define LPC43_BASE_SPI_CLK (LPC43_CGU_BASE+LPC43_BASE_SPI_CLK_OFFSET)
|
||||
#define LPC43_BASE_PHYRX_CLK (LPC43_CGU_BASE+LPC43_BASE_PHYRX_CLK_OFFSET)
|
||||
#define LPC43_BASE_PHYTX_CLK (LPC43_CGU_BASE+LPC43_BASE_PHYTX_CLK_OFFSET)
|
||||
#define LPC43_BASE_APB1_CLK (LPC43_CGU_BASE+LPC43_BASE_APB1_CLK_OFFSET)
|
||||
#define LPC43_BASE_APB3_CLK (LPC43_CGU_BASE+LPC43_BASE_APB3_CLK_OFFSET)
|
||||
#define LPC43_BASE_LCD_CLK (LPC43_CGU_BASE+LPC43_BASE_LCD_CLK_OFFSET)
|
||||
#define LPC43_BASE_VADC_CLK (LPC43_CGU_BASE+LPC43_BASE_VADC_CLK_OFFSET)
|
||||
#define LPC43_BASE_SDIO_CLK (LPC43_CGU_BASE+LPC43_BASE_SDIO_CLK_OFFSET)
|
||||
#define LPC43_BASE_SSP0_CLK (LPC43_CGU_BASE+LPC43_BASE_SSP0_CLK_OFFSET)
|
||||
#define LPC43_BASE_SSP1_CLK (LPC43_CGU_BASE+LPC43_BASE_SSP1_CLK_OFFSET)
|
||||
#define LPC43_BASE_UART0_CLK (LPC43_CGU_BASE+LPC43_BASE_UART0_CLK_OFFSET)
|
||||
#define LPC43_BASE_UART1_CLK (LPC43_CGU_BASE+LPC43_BASE_UART1_CLK_OFFSET)
|
||||
#define LPC43_BASE_UART2_CLK (LPC43_CGU_BASE+LPC43_BASE_UART2_CLK_OFFSET)
|
||||
#define LPC43_BASE_UART3_CLK (LPC43_CGU_BASE+LPC43_BASE_UART3_CLK_OFFSET)
|
||||
#define LPC43_BASE_OUT_CLK (LPC43_CGU_BASE+LPC43_BASE_OUT_CLK_OFFSET)
|
||||
#define LPC43_BASE_APLL_CLK (LPC43_CGU_BASE+LPC43_BASE_APLL_CLK_OFFSET)
|
||||
#define LPC43_BASE_CGU_OUT0_CLK (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT0_CLK_OFFSET)
|
||||
#define LPC43_BASE_CGU_OUT1_CLK (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT1_CLK_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *************************************************************************/
|
||||
|
||||
/* Frequency monitor register */
|
||||
|
||||
#define FREQ_MON_RCNT_SHIFT (0) /* Bits 0-8: 9-bit reference clock-counter value */
|
||||
#define FREQ_MON_RCNT_MASK (0x1ff << FREQ_MON_RCNT_SHIFT)
|
||||
#define FREQ_MON_FCNT_SHIFT (9) /* Bits 9-22: 14-bit selected clock-counter value */
|
||||
#define FREQ_MON_FCNT_MASK (0x3fff << FREQ_MON_FCNT_SHIFT)
|
||||
#define FREQ_MON_MEAS (1 << 23) /* Bit 23: Measure frequency */
|
||||
#define FREQ_MON_CLKSEL_SHIFT (24) /* Bits 24-28: Clock-source selection */
|
||||
#define FREQ_MON_CLKSEL_MASK (31 << FREQ_MON_CLKSEL_SHIFT)
|
||||
# define FREQ_MON_CLKSEL_32KHZOSC (0 << FREQ_MON_CLKSEL_SHIFT) /* 32 kHz oscillator (default) */
|
||||
# define FREQ_MON_CLKSEL_IRQ (1 << FREQ_MON_CLKSEL_SHIFT) /* IRC */
|
||||
# define FREQ_MON_CLKSEL_ENET_RXCLK (2 << FREQ_MON_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define FREQ_MON_CLKSEL_ENET_TXCLK (3 << FREQ_MON_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define FREQ_MON_CLKSEL_GPCLKIN (4 << FREQ_MON_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define FREQ_MON_CLKSEL_XTAL (6 << FREQ_MON_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define FREQ_MON_CLKSEL_PLL0USB (7 << FREQ_MON_CLKSEL_SHIFT) /* PLL0USB */
|
||||
# define FREQ_MON_CLKSEL_PLL0AUDIO (8 << FREQ_MON_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define FREQ_MON_CLKSEL_PLL1 (9 << FREQ_MON_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define FREQ_MON_CLKSEL_IDIVA (12 << FREQ_MON_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define FREQ_MON_CLKSEL_IDIVB (13 << FREQ_MON_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define FREQ_MON_CLKSEL_IDIVC (14 << FREQ_MON_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define FREQ_MON_CLKSEL_IDIVD (15 << FREQ_MON_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define FREQ_MON_CLKSEL_IDIVE (16 << FREQ_MON_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Crystal oscillator control register */
|
||||
|
||||
#define XTAL_OSC_CTRL_ENABLE (1 << 0) /* Bit 0: Oscillator-pad enable */
|
||||
#define XTAL_OSC_CTRL_BYPASS (1 << 1) /* Bit 1: Configure crystal or external-clock input */
|
||||
#define XTAL_OSC_CTRL_HF (1 << 2) /* Bit 2: Select frequency range
|
||||
/* Bits 3-31: Reserved */
|
||||
/* PLL0USB status register */
|
||||
|
||||
#define PLL0USB_STAT_LOCK (1 << 0) /* Bit 0: PLL0 lock indicator */
|
||||
#define PLL0USB_STAT_FR (1 << 1) /* Bit 1: PLL0 free running indicator */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* PLL0USB control register */
|
||||
|
||||
#define PLL0USB_CTRL_PD (1 << 0) /* Bit 0: PLL0 power down */
|
||||
#define PLL0USB_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */
|
||||
#define PLL0USB_CTRL_DIRECTI (1 << 2) /* Bit 2: PLL0 direct input */
|
||||
#define PLL0USB_CTRL_DIRECTO (1 << 3) /* Bit 3: PLL0 direct output */
|
||||
#define PLL0USB_CTRL_CLKEN (1 << 4) /* Bit 4: PLL0 clock enable */
|
||||
/* Bit 5: Reserved */
|
||||
#define PLL0USB_CTRL_FRM (1 << 6) /* Bit 6: Free running mode */
|
||||
/* Bits 7-10: Reserved */
|
||||
#define PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define PLL0USB_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define PLL0USB_CTRL_CLKSEL_MASK (31 << PLL0USB_CTRL_CLKSEL_SHIFT)
|
||||
# define PLL0USB_CLKSEL_32KHZOSC (0 << PLL0USB_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define PLL0USB_CLKSEL_IRC (1 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define PLL0USB_CLKSEL_ENET_RXCLK (2 << PLL0USB_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define PLL0USB_CLKSEL_ENET_TXCLK (3 << PLL0USB_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define PLL0USB_CLKSEL_GPCLKIN (4 << PLL0USB_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define PLL0USB_CLKSEL_XTAL (6 << PLL0USB_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define PLL0USB_CLKSEL_PLL1 (9 << PLL0USB_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define PLL0USB_CLKSEL_IDIVA (12 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define PLL0USB_CLKSEL_IDIVB (13 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define PLL0USB_CLKSEL_IDIVC (14 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define PLL0USB_CLKSEL_IDIVD (15 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define PLL0USB_CLKSEL_IDIVE (16 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* PLL0USB M-divider register */
|
||||
|
||||
#define PLL0USB_MDIV_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */
|
||||
#define PLL0USB_MDIV_MDEC_MASK (0x1ffff << PLL0USB_MDIV_MDEC_SHIFT)
|
||||
# define PLL0USB_MDIV_MDEC(n) ((n) << PLL0USB_MDIV_MDEC_SHIFT)
|
||||
#define PLL0USB_MDIV_SELP_SHIFT (17) /* Bits 17-21: Bandwidth select P value */
|
||||
#define PLL0USB_MDIV_SELP_MASK (0x1f << PLL0USB_MDIV_SELP_SHIFT)
|
||||
# define PLL0USB_MDIV_SELP(n) ((n) << PLL0USB_MDIV_SELP_SHIFT)
|
||||
#define PLL0USB_MDIV_SELI_SHIFT (22) /* Bits 22-27: Bandwidth select I value */
|
||||
#define PLL0USB_MDIV_SELI_MASK (0x3f << PLL0USB_MDIV_SELI_SHIFT)
|
||||
# define PLL0USB_MDIV_SELI(n) ((n) << PLL0USB_MDIV_SELI_SHIFT)
|
||||
#define PLL0USB_MDIV_SELR_SHIFT (28) /* Bits 28-31: Bandwidth select R value */
|
||||
#define PLL0USB_MDIV_SELR_MASK (15 << PLL0USB_MDIV_SELR_SHIFT)
|
||||
# define PLL0USB_MDIV_SELR(n) ((n) << PLL0USB_MDIV_SELR_SHIFT)
|
||||
|
||||
/* PLL0USB N/P-divider register */
|
||||
|
||||
#define PLL0USB_NP_DIV_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient value */
|
||||
#define PLL0USB_NP_DIV_PDEC_MASK (0x7f << PLL0USB_NP_DIV_PDEC_SHIFT)
|
||||
# define PLL0USB_NP_DIV_PDEC(n) ((n) << PLL0USB_NP_DIV_PDEC_SHIFT)
|
||||
/* Bits 7-11: Reserved */
|
||||
#define PLL0USB_NP_DIV_NDEC_SHIFT (12) /* Bits 12-21: Decoded N-divider coefficient value */
|
||||
#define PLL0USB_NP_DIV_NDEC_MASK (0x3ff << PLL0USB_NP_DIV_NDEC_SHIFT)
|
||||
# define PLL0USB_NP_DIV_NDEC(n) ((n) << PLL0USB_NP_DIV_NDEC_SHIFT)
|
||||
/* Bits 22-31: Reserved */
|
||||
/* PLL0AUDIO status register */
|
||||
|
||||
#define PLL0AUDIO_STAT_LOCK (1 << 0) /* Bit 0: PLL0 lock indicator */
|
||||
#define PLL0AUDIO_STAT_FR (1 << 1) /* Bit 1: PLL0 free running indicator */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* PLL0AUDIO control register */
|
||||
|
||||
#define PLL0AUDIO_CTRL_PD (1 << 0) /* Bit 0: PLL0 power down */
|
||||
#define PLL0AUDIO_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */
|
||||
#define PLL0AUDIO_CTRL_DIRECTI (1 << 2) /* Bit 2: PLL0 direct input */
|
||||
#define PLL0AUDIO_CTRL_DIRECTO (1 << 3) /* Bit 3: PLL0 direct output */
|
||||
#define PLL0AUDIO_CTRL_CLKEN (1 << 4) /* Bit 4: PLL0 clock enable */
|
||||
/* Bit 5: Reserved */
|
||||
#define PLL0AUDIO_CTRL_FRM (1 << 6) /* Bit 6: Free running mode */
|
||||
/* Bits 7-10: Reserved */
|
||||
#define PLL0AUDIO_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
|
||||
#define PLL0AUDIO_CTRL_PLLFRACTREQ (1 << 12) /* Bit 12: Fractional PLL word write request */
|
||||
#define PLL0AUDIO_CTRL_SELEXT (1 << 13) /* Bit 13: Select fractional divider */
|
||||
#define PLL0AUDIO_CTRL_MODPD (1 << 14) /* Bit 14: Sigma-Delta modulator power-down */
|
||||
/* Bits 15-23: Reserved */
|
||||
#define PLL0AUDIO_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define PLL0AUDIO_CTRL_CLKSEL_MASK (31 << PLL0AUDIO_CTRL_CLKSEL_SHIFT)
|
||||
# define PLL0AUDIO_CLKSEL_32KHZOSC (0 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define PLL0AUDIO_CLKSEL_IRC (1 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define PLL0AUDIO_CLKSEL_ENET_RXCLK (2 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define PLL0AUDIO_CLKSEL_ENET_TXCLK (3 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define PLL0AUDIO_CLKSEL_GPCLKIN (4 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define PLL0AUDIO_CLKSEL_XTAL (6 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define PLL0AUDIO_CLKSEL_PLL1 (9 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define PLL0AUDIO_CLKSEL_IDIVA (12 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define PLL0AUDIO_CLKSEL_IDIVB (13 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define PLL0AUDIO_CLKSEL_IDIVC (14 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define PLL0AUDIO_CLKSEL_IDIVD (15 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define PLL0AUDIO_CLKSEL_IDIVE (16 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* PLL0AUDIO M-divider */
|
||||
|
||||
#define PLL0AUDIO_MDIV_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */
|
||||
#define PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << PLL0AUDIO_MDIV_MDEC_SHIFT)
|
||||
# define PLL0AUDIO_MDIV_MDEC(n) ((n) << PLL0AUDIO_MDIV_MDEC_SHIFT)
|
||||
/* Bits 17-31: Reserved */
|
||||
/* PLL0AUDIO N/P-divider */
|
||||
|
||||
#define PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient value */
|
||||
#define PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << PLL0AUDIO_NP_DIV_PDEC_SHIFT)
|
||||
# define PLL0AUDIO_NP_DIV_PDEC(n) ((n) << PLL0AUDIO_NP_DIV_PDEC_SHIFT)
|
||||
/* Bits 7-11: Reserved */
|
||||
#define PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) /* Bits 12-21: Decoded N-divider coefficient value */
|
||||
#define PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << PLL0AUDIO_NP_DIV_NDEC_SHIFT)
|
||||
# define PLL0AUDIO_NP_DIV_NDEC(n) ((n) << PLL0AUDIO_NP_DIV_NDEC_SHIFT)
|
||||
/* Bits 22-31: Reserved */
|
||||
/* PLL0AUDIO fractional */
|
||||
|
||||
#define PLL0AUDIO_FRAC_CTRL_SHIFT (0) /* Bits 0-21: Decoded P-divider coefficient value */
|
||||
#define PLL0AUDIO_FRAC_CTRL_MASK (0x3fffff << PLL0AUDIO_FRAC_CTRL_SHIFT)
|
||||
# define PLL0AUDIO_FRA_CCTRL(n) ((n) << PLL0AUDIO_FRAC_CTRL_SHIFT)
|
||||
/* Bits 22-31: Reserved */
|
||||
/* PLL1 status register */
|
||||
|
||||
#define PLL1_STAT_LOCK (1 << 0) /* Bit 0: PLL1 lock indicator */
|
||||
/* Bits 1-31: Reserved */
|
||||
/* PLL1 control register */
|
||||
|
||||
#define PLL1_CTRL_PD (1 << 0) /* Bit 0: PLL1 power down */
|
||||
#define PLL1_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */
|
||||
/* Bits 2-5: Reserved */
|
||||
#define PLL1_CTRL_FBSEL (1 << 6) /* Bit 6: PLL1 feedback select */
|
||||
#define PLL1_CTRL_DIRECT (1 << 7) /* Bit 7: PLL1 direct CCO output */
|
||||
|
||||
#define PLL1_CTRL_PSEL_SHIFT (8) /* Bits 8-9: Post-divider division ratio P */
|
||||
#define PLL1_CTRL_PSEL_MASK (3 << PLL1_CTRL_PSEL_SHIFT)
|
||||
# define PLL1_CTRL_PSEL_DIV1 (0 << PLL1_CTRL_PSEL_SHIFT)
|
||||
# define PLL1_CTRL_PSEL_DIV2 (1 << PLL1_CTRL_PSEL_SHIFT)
|
||||
# define PLL1_CTRL_PSEL_DIV4 (2 << PLL1_CTRL_PSEL_SHIFT)
|
||||
# define PLL1_CTRL_PSEL_DIV8 (3 << PLL1_CTRL_PSEL_SHIFT)
|
||||
/* Bit 10: Reserved */
|
||||
#define PLL1_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
#define PLL1_CTRL_NSEL_SHIFT (12) /* Bits 12-13: Pre-divider division ratio N */
|
||||
#define PLL1_CTRL_NSEL_MASK (3 << PLL1_CTRL_NSEL_SHIFT)
|
||||
# define PLL1_CTRL_NSEL_DIV1 (0 << PLL1_CTRL_NSEL_SHIFT)
|
||||
# define PLL1_CTRL_NSEL_DIV2 (1 << PLL1_CTRL_NSEL_SHIFT)
|
||||
# define PLL1_CTRL_NSEL_DIV3 (2 << PLL1_CTRL_NSEL_SHIFT)
|
||||
# define PLL1_CTRL_NSEL_DIV4 (3 << PLL1_CTRL_NSEL_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define PLL1_CTRL_MSEL_SHIFT (16) /* Bits 16-17: Feedback-divider division ratio M */
|
||||
#define PLL1_CTRL_MSEL_MASK (3 << PLL1_CTRL_MSEL_SHIFT)
|
||||
# define PLL1_CTRL_MSEL_DIV(n) (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */
|
||||
#define PLL1_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define PLL1_CTRL_CLKSEL_MASK (31 << PLL1_CTRL_CLKSEL_SHIFT)
|
||||
# define PLL1_CLKSEL_32KHZOSC (0 << PLL1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define PLL1_CLKSEL_IRC (1 << PLL1_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define PLL1_CLKSEL_ENET_RXCLK (2 << PLL1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define PLL1_CLKSEL_ENET_TXCLK (3 << PLL1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define PLL1_CLKSEL_GPCLKIN (4 << PLL1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define PLL1_CLKSEL_XTAL (6 << PLL1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define PLL1_CLKSEL_PLL0USB (7 << PLL1_CTRL_CLKSEL_SHIFT) /* PLL0USB */
|
||||
# define PLL1_CLKSEL_PLL0AUDIO (8 << PLL1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define PLL1_CLKSEL_IDIVA (12 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define PLL1_CLKSEL_IDIVB (13 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define PLL1_CLKSEL_IDIVC (14 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define PLL1_CLKSEL_IDIVD (15 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define PLL1_CLKSEL_IDIVE (16 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Integer divider A control register */
|
||||
|
||||
#define IDIVA_CTRL_PD (1 << 0) /* Bit 0: Integer divider A power down */
|
||||
/* Bit 1: Reserved */
|
||||
#define IDIVA_CTRL_IDIV_SHIFT (2) /* Bits 2-3: Integer divider A divider values (1/(IDIV + 1)) */
|
||||
#define IDIVA_CTRL_IDIV_MASK (3 << IDIVA_CTRL_IDIV_SHIFT)
|
||||
# define IDIVA_CTRL_IDIV(n) (((n)-1) << IDIVA_CTRL_IDIV_SHIFT) /* n=1..4 */
|
||||
/* Bits 4-10: Reserved */
|
||||
#define IDIVA_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define IDIVA_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define IDIVA_CTRL_CLKSEL_MASK (31 << IDIVA_CTRL_CLKSEL_SHIFT)
|
||||
# define IDIVA_CLKSEL_32KHZOSC (0 << IDIVA_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define IDIVA_CLKSEL_IRC (1 << IDIVA_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define IDIVA_CLKSEL_ENET_RXCLK (2 << IDIVA_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define IDIVA_CLKSEL_ENET_TXCLK (3 << IDIVA_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define IDIVA_CLKSEL_GPCLKIN (4 << IDIVA_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define IDIVA_CLKSEL_XTAL (6 << IDIVA_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define IDIVA_CLKSEL_PLL0USB (7 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL0USB */
|
||||
# define IDIVA_CLKSEL_PLL0AUDIO (8 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define IDIVA_CLKSEL_PLL1 (9 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Integer divider B/C/D control register */
|
||||
|
||||
#define IDIVBCD_CTRL_PD (1 << 0) /* Bit 0: Integer divider power down */
|
||||
/* Bit 1: Reserved */
|
||||
#define IDIVBCD_CTRL_IDIV_SHIFT (2) /* Bits 2-5: Integer divider A divider values (1/(IDIV + 1)) */
|
||||
#define IDIVBCD_CTRL_IDIV_MASK (15 << IDIVBCD_CTRL_IDIV_SHIFT)
|
||||
# define IDIVBCD_CTRL_IDIV_DIV(n) (((n)-1) << IDIVBCD_CTRL_IDIV_SHIFT) /* n=1..16 */
|
||||
/* Bits 6-10: Reserved */
|
||||
#define IDIVBCD_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define IDIVBCD_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define IDIVBCD_CTRL_CLKSEL_MASK (31 << IDIVBCD_CTRL_CLKSEL_SHIFT)
|
||||
# define IDIVBCD_CLKSEL_32KHZOSC (0 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define IDIVBCD_CLKSEL_IRC (1 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define IDIVBCD_CLKSEL_ENET_RXCLK (2 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define IDIVBCD_CLKSEL_ENET_TXCLK (3 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define IDIVBCD_CLKSEL_GPCLKIN (4 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define IDIVBCD_CLKSEL_XTAL (6 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define IDIVBCD_CLKSEL_PLL0AUDIO (8 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define IDIVBCD_CLKSEL_PLL1 (9 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define IDIVBCD_CLKSEL_IDIVA (12 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Integer divider E control register */
|
||||
|
||||
#define IDIVE_CTRL_PD (1 << 0) /* Bit 0: Integer divider E power down */
|
||||
/* Bit 1: Reserved */
|
||||
#define IDIVE_CTRL_IDIV_SHIFT (2) /* Bits 2-9: Integer divider A divider values (1/(IDIV + 1)) */
|
||||
#define IDIVE_CTRL_IDIV_MASK (0xff << IDIVE_CTRL_IDIV_SHIFT)
|
||||
# define IDIVE_CTRL_IDIV_DIV(n) (((n)-1) << IDIVE_CTRL_IDIV_SHIFT) /* n=1..256 */
|
||||
/* Bit 10: Reserved */
|
||||
#define IDIVE_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define IDIVE_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define IDIVE_CTRL_CLKSEL_MASK (31 << IDIVE_CTRL_CLKSEL_SHIFT)
|
||||
# define IDIVE_CLKSEL_32KHZOSC (0 << IDIVE_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define IDIVE_CLKSEL_IRC (1 << IDIVE_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define IDIVE_CLKSEL_ENET_RXCLK (2 << IDIVE_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define IDIVE_CLKSEL_ENET_TXCLK (3 << IDIVE_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define IDIVE_CLKSEL_GPCLKIN (4 << IDIVE_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define IDIVE_CLKSEL_XTAL (6 << IDIVE_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define IDIVE_CLKSEL_PLL0AUDIO (8 << IDIVE_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define IDIVE_CLKSEL_PLL1 (9 << IDIVE_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define IDIVE_CLKSEL_IDIVA (12 << IDIVE_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 0 control register (BASE_SAFE_CLK) */
|
||||
|
||||
#define BASE_SAFE_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_SAFE_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_SAFE_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_SAFE_CLK_CLKSEL_MASK (31 << BASE_SAFE_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_SAFE_CLKSEL_IRC (1 << BASE_SAFE_CLK_CLKSEL_SHIFT) /* IRC (default) */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 1 control register (BASE_USB0_CLK) */
|
||||
|
||||
#define BASE_USB0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_USB0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_USB0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_USB0_CLK_CLKSEL_MASK (31 << BASE_USB0_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_USB0_CLKSEL_PLL0USB (7 << BASE_USB0_CLK_CLKSEL_SHIFT) /* PLL0USB (default) */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 2 control register (BASE_PERIPH_CLK) */
|
||||
|
||||
#define BASE_PERIPH_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_PERIPH_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_PERIPH_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_PERIPH_CLK_CLKSEL_MASK (31 << BASE_PERIPH_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_PERIPH_CLKSEL_32KHZOSC (0 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_PERIPH_CLKSEL_IRC (1 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_PERIPH_CLKSEL_ENET_RXCLK (2 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_PERIPH_CLKSEL_ENET_TXCLK (3 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_PERIPH_CLKSEL_GPCLKIN (4 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_PERIPH_CLKSEL_XTAL (6 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_PERIPH_CLKSEL_PLL0AUDIO (8 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_PERIPH_CLKSEL_PLL1 (9 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_PERIPH_CLKSEL_IDIVA (12 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_PERIPH_CLKSEL_IDIVB (13 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_PERIPH_CLKSEL_IDIVC (14 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_PERIPH_CLKSEL_IDIVD (15 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_PERIPH_CLKSEL_IDIVE (16 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 3 control register (BASE_USB1_CLK) */
|
||||
|
||||
#define BASE_USB1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_USB1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_USB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_USB1_CLK_CLKSEL_MASK (31 << BASE_USB1_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_USB1_CLKSEL_32KHZOSC (0 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_USB1_CLKSEL_IRC (1 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_USB1_CLKSEL_ENET_RXCLK (2 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_USB1_CLKSEL_ENET_TXCLK (3 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_USB1_CLKSEL_GPCLKIN (4 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_USB1_CLKSEL_XTAL (6 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_USB1_CLKSEL_PLL0USB (7 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0USB */
|
||||
# define BASE_USB1_CLKSEL_PLL0AUDIO (8 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_USB1_CLKSEL_PLL1 (9 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_USB1_CLKSEL_IDIVA (12 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_USB1_CLKSEL_IDIVB (13 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_USB1_CLKSEL_IDIVC (14 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_USB1_CLKSEL_IDIVD (15 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_USB1_CLKSEL_IDIVE (16 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 4 control register (BASE_M4_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_M4_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_M4_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_M4_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_M4_CLK_CLKSEL_MASK (31 << BASE_M4_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_M4_CLKSEL_32KHZOSC (0 << BASE_M4_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_M4_CLKSEL_IRC (1 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_M4_CLKSEL_ENET_RXCLK (2 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_M4_CLKSEL_ENET_TXCLK (3 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_M4_CLKSEL_GPCLKIN (4 << BASE_M4_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_M4_CLKSEL_XTAL (6 << BASE_M4_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_M4_CLKSEL_PLL0AUDIO (8 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_M4_CLKSEL_PLL1 (9 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_M4_CLKSEL_IDIVA (12 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_M4_CLKSEL_IDIVB (13 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_M4_CLKSEL_IDIVC (14 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_M4_CLKSEL_IDIVD (15 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_M4_CLKSEL_IDIVE (16 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 5 control register (BASE_SPIFI_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_SPIFI_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_SPIFI_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_SPIFI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_SPIFI_CLK_CLKSEL_MASK (31 << BASE_SPIFI_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_SPIFI_CLKSEL_32KHZOSC (0 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_SPIFI_CLKSEL_IRC (1 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_SPIFI_CLKSEL_ENET_RXCLK (2 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_SPIFI_CLKSEL_ENET_TXCLK (3 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_SPIFI_CLKSEL_GPCLKIN (4 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_SPIFI_CLKSEL_XTAL (6 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_SPIFI_CLKSEL_PLL0AUDIO (8 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_SPIFI_CLKSEL_PLL1 (9 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_SPIFI_CLKSEL_IDIVA (12 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_SPIFI_CLKSEL_IDIVB (13 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_SPIFI_CLKSEL_IDIVC (14 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_SPIFI_CLKSEL_IDIVD (15 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_SPIFI_CLKSEL_IDIVE (16 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 6 control register (BASE_SPI_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_SPI_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_SPI_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_SPI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_SPI_CLK_CLKSEL_MASK (31 << BASE_SPI_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_SPI_CLKSEL_32KHZOSC (0 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_SPI_CLKSEL_IRC (1 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_SPI_CLKSEL_ENET_RXCLK (2 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_SPI_CLKSEL_ENET_TXCLK (3 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_SPI_CLKSEL_GPCLKIN (4 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_SPI_CLKSEL_XTAL (6 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_SPI_CLKSEL_PLL0AUDIO (8 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_SPI_CLKSEL_PLL1 (9 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_SPI_CLKSEL_IDIVA (12 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_SPI_CLKSEL_IDIVB (13 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_SPI_CLKSEL_IDIVC (14 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_SPI_CLKSEL_IDIVD (15 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_SPI_CLKSEL_IDIVE (16 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 7 control register (BASE_PHY_RX_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_PHYRX_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_PHYRX_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_PHYRX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_PHYRX_CLK_CLKSEL_MASK (31 << BASE_PHYRX_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_PHYRX_CLKSEL_32KHZOSC (0 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_PHYRX_CLKSEL_IRC (1 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_PHYRX_CLKSEL_ENET_RXCLK (2 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_PHYRX_CLKSEL_ENET_TXCLK (3 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_PHYRX_CLKSEL_GPCLKIN (4 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_PHYRX_CLKSEL_XTAL (6 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_PHYRX_CLKSEL_PLL0AUDIO (8 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_PHYRX_CLKSEL_PLL1 (9 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_PHYRX_CLKSEL_IDIVA (12 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_PHYRX_CLKSEL_IDIVB (13 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_PHYRX_CLKSEL_IDIVC (14 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_PHYRX_CLKSEL_IDIVD (15 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_PHYRX_CLKSEL_IDIVE (16 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 8 control register (BASE_PHY_TX_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_PHYTX_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_PHYTX_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_PHYTX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_PHYTX_CLK_CLKSEL_MASK (31 << BASE_PHYTX_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_PHYTX_CLKSEL_32KHZOSC (0 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_PHYTX_CLKSEL_IRC (1 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_PHYTX_CLKSEL_ENET_RXCLK (2 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_PHYTX_CLKSEL_ENET_TXCLK (3 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_PHYTX_CLKSEL_GPCLKIN (4 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_PHYTX_CLKSEL_XTAL (6 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_PHYTX_CLKSEL_PLL0AUDIO (8 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_PHYTX_CLKSEL_PLL1 (9 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_PHYTX_CLKSEL_IDIVA (12 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_PHYTX_CLKSEL_IDIVB (13 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_PHYTX_CLKSEL_IDIVC (14 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_PHYTX_CLKSEL_IDIVD (15 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_PHYTX_CLKSEL_IDIVE (16 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 9 control register (BASE_APB1_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_APB1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_APB1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_APB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_APB1_CLK_CLKSEL_MASK (31 << BASE_APB1_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_APB1_CLKSEL_32KHZOSC (0 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_APB1_CLKSEL_IRC (1 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_APB1_CLKSEL_ENET_RXCLK (2 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_APB1_CLKSEL_ENET_TXCLK (3 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_APB1_CLKSEL_GPCLKIN (4 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_APB1_CLKSEL_XTAL (6 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_APB1_CLKSEL_PLL0AUDIO (8 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_APB1_CLKSEL_PLL1 (9 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_APB1_CLKSEL_IDIVA (12 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_APB1_CLKSEL_IDIVB (13 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_APB1_CLKSEL_IDIVC (14 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_APB1_CLKSEL_IDIVD (15 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_APB1_CLKSEL_IDIVE (16 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 11 control register (BASE_LCD_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_LCD_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_LCD_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_LCD_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_LCD_CLK_CLKSEL_MASK (31 << BASE_LCD_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_LCD_CLKSEL_32KHZOSC (0 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_LCD_CLKSEL_IRC (1 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_LCD_CLKSEL_ENET_RXCLK (2 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_LCD_CLKSEL_ENET_TXCLK (3 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_LCD_CLKSEL_GPCLKIN (4 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_LCD_CLKSEL_XTAL (6 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_LCD_CLKSEL_PLL0AUDIO (8 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_LCD_CLKSEL_PLL1 (9 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_LCD_CLKSEL_IDIVA (12 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_LCD_CLKSEL_IDIVB (13 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_LCD_CLKSEL_IDIVC (14 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_LCD_CLKSEL_IDIVD (15 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_LCD_CLKSEL_IDIVE (16 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 12 control register (BASE_VADC_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_VADC_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_VADC_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_VADC_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_VADC_CLK_CLKSEL_MASK (31 << BASE_VADC_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_VADC_CLKSEL_32KHZOSC (0 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_VADC_CLKSEL_IRC (1 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_VADC_CLKSEL_ENET_RXCLK (2 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_VADC_CLKSEL_ENET_TXCLK (3 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_VADC_CLKSEL_GPCLKIN (4 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_VADC_CLKSEL_XTAL (6 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_VADC_CLKSEL_PLL0AUDIO (8 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_VADC_CLKSEL_PLL1 (9 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_VADC_CLKSEL_IDIVA (12 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_VADC_CLKSEL_IDIVB (13 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_VADC_CLKSEL_IDIVC (14 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 14 control register (BASE_SSP0_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_SSP0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_SSP0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_SSP0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_SSP0_CLK_CLKSEL_MASK (31 << BASE_SSP0_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_SSP0_CLKSEL_32KHZOSC (0 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_SSP0_CLKSEL_IRC (1 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_SSP0_CLKSEL_ENET_RXCLK (2 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_SSP0_CLKSEL_ENET_TXCLK (3 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_SSP0_CLKSEL_GPCLKIN (4 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_SSP0_CLKSEL_XTAL (6 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_SSP0_CLKSEL_PLL0AUDIO (8 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_SSP0_CLKSEL_PLL1 (9 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_SSP0_CLKSEL_IDIVA (12 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_SSP0_CLKSEL_IDIVB (13 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_SSP0_CLKSEL_IDIVC (14 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_SSP0_CLKSEL_IDIVD (15 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_SSP0_CLKSEL_IDIVE (16 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 15 control register (BASE_SSP1_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_SSP1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_SSP1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_SSP1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_SSP1_CLK_CLKSEL_MASK (31 << BASE_SSP1_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_SSP1_CLKSEL_32KHZOSC (0 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_SSP1_CLKSEL_IRC (1 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_SSP1_CLKSEL_ENET_RXCLK (2 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_SSP1_CLKSEL_ENET_TXCLK (3 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_SSP1_CLKSEL_GPCLKIN (4 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_SSP1_CLKSEL_XTAL (6 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_SSP1_CLKSEL_PLL0AUDIO (8 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_SSP1_CLKSEL_PLL1 (9 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_SSP1_CLKSEL_IDIVA (12 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_SSP1_CLKSEL_IDIVB (13 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_SSP1_CLKSEL_IDIVC (14 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_SSP1_CLKSEL_IDIVD (15 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_SSP1_CLKSEL_IDIVE (16 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 16 control register (BASE_UART0_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_UART0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_UART0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_UART0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_UART0_CLK_CLKSEL_MASK (31 << BASE_UART0_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_UART0_CLKSEL_32KHZOSC (0 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_UART0_CLKSEL_IRC (1 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_UART0_CLKSEL_ENET_RXCLK (2 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_UART0_CLKSEL_ENET_TXCLK (3 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_UART0_CLKSEL_GPCLKIN (4 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_UART0_CLKSEL_XTAL (6 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_UART0_CLKSEL_PLL0AUDIO (8 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_UART0_CLKSEL_PLL1 (9 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_UART0_CLKSEL_IDIVA (12 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_UART0_CLKSEL_IDIVB (13 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_UART0_CLKSEL_IDIVC (14 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_UART0_CLKSEL_IDIVD (15 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_UART0_CLKSEL_IDIVE (16 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 18 control register (BASE_UART2_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_UART2_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_UART2_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_UART2_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_UART2_CLK_CLKSEL_MASK (31 << BASE_UART2_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_UART2_CLKSEL_32KHZOSC (0 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_UART2_CLKSEL_IRC (1 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_UART2_CLKSEL_ENET_RXCLK (2 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_UART2_CLKSEL_ENET_TXCLK (3 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_UART2_CLKSEL_GPCLKIN (4 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_UART2_CLKSEL_XTAL (6 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_UART2_CLKSEL_PLL0AUDIO (8 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_UART2_CLKSEL_PLL1 (9 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_UART2_CLKSEL_IDIVA (12 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_UART2_CLKSEL_IDIVB (13 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_UART2_CLKSEL_IDIVC (14 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_UART2_CLKSEL_IDIVD (15 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_UART2_CLKSEL_IDIVE (16 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 19 control register (BASE_UART3_CLK) */
|
||||
/* NOTE: Clocks 4-19 are identical */
|
||||
|
||||
#define BASE_UART3_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_UART3_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_UART3_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_UART3_CLK_CLKSEL_MASK (31 << BASE_UART3_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_UART3_CLKSEL_32KHZOSC (0 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_UART3_CLKSEL_IRC (1 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_UART3_CLKSEL_ENET_RXCLK (2 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_UART3_CLKSEL_ENET_TXCLK (3 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_UART3_CLKSEL_GPCLKIN (4 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_UART3_CLKSEL_XTAL (6 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_UART3_CLKSEL_PLL0AUDIO (8 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_UART3_CLKSEL_PLL1 (9 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_UART3_CLKSEL_IDIVA (12 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_UART3_CLKSEL_IDIVB (13 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_UART3_CLKSEL_IDIVC (14 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_UART3_CLKSEL_IDIVD (15 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_UART3_CLKSEL_IDIVE (16 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 20 control register (BASE_OUT_CLK) */
|
||||
|
||||
#define BASE_OUT_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_OUT_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_OUT_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
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#define BASE_OUT_CLK_CLKSEL_MASK (31 << BASE_OUT_CLK_CLKSEL_SHIFT)
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# define BASE_OUT_CLKSEL_32KHZOSC (0 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
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# define BASE_OUT_CLKSEL_IRC (1 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IRC (default) */
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# define BASE_OUT_CLKSEL_ENET_RXCLK (2 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
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# define BASE_OUT_CLKSEL_ENET_TXCLK (3 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
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# define BASE_OUT_CLKSEL_GPCLKIN (4 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
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# define BASE_OUT_CLKSEL_XTAL (6 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
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# define BASE_OUT_CLKSEL_PLL0USB (7 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0USB */
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# define BASE_OUT_CLKSEL_PLL0AUDIO (8 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
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# define BASE_OUT_CLKSEL_PLL1 (9 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL1 */
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# define BASE_OUT_CLKSEL_IDIVA (12 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVA */
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# define BASE_OUT_CLKSEL_IDIVB (13 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVB */
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# define BASE_OUT_CLKSEL_IDIVC (14 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVC */
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# define BASE_OUT_CLKSEL_IDIVD (15 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVD */
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# define BASE_OUT_CLKSEL_IDIVE (16 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVE */
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/* Bits 29-31: Reserved */
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/* Output stage 25 control register (BASE_APLL_CLK) */
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#define BASE_APLL_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
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/* Bits 1-10: Reserved */
|
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#define BASE_APLL_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
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#define BASE_APLL_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_APLL_CLK_CLKSEL_MASK (31 << BASE_APLL_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_APLL_CLKSEL_32KHZOSC (0 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_APLL_CLKSEL_IRC (1 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_APLL_CLKSEL_ENET_RXCLK (2 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_APLL_CLKSEL_ENET_TXCLK (3 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_APLL_CLKSEL_GPCLKIN (4 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_APLL_CLKSEL_XTAL (6 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_APLL_CLKSEL_PLL0AUDIO (8 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_APLL_CLKSEL_PLL1 (9 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_APLL_CLKSEL_IDIVA (12 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_APLL_CLKSEL_IDIVB (13 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_APLL_CLKSEL_IDIVC (14 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_APLL_CLKSEL_IDIVD (15 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_APLL_CLKSEL_IDIVE (16 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
/* Output stage 26/27 control register (BASE_CGU_OUT0/1_CLK) */
|
||||
/* NOTE: Clocks 26-27 are identical */
|
||||
|
||||
#define BASE_CGU_CLK_PD (1 << 0) /* Bit 0: Output stage power down */
|
||||
/* Bits 1-10: Reserved */
|
||||
#define BASE_CGU_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */
|
||||
/* Bits 12-23: Reserved */
|
||||
#define BASE_CGU_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */
|
||||
#define BASE_CGU_CLK_CLKSEL_MASK (31 << BASE_CGU_CLK_CLKSEL_SHIFT)
|
||||
# define BASE_CGU_CLKSEL_32KHZOSC (0 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */
|
||||
# define BASE_CGU_CLKSEL_IRC (1 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IRC (default) */
|
||||
# define BASE_CGU_CLKSEL_ENET_RXCLK (2 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */
|
||||
# define BASE_CGU_CLKSEL_ENET_TXCLK (3 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */
|
||||
# define BASE_CGU_CLKSEL_GPCLKIN (4 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */
|
||||
# define BASE_CGU_CLKSEL_XTAL (6 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */
|
||||
# define BASE_CGU_CLKSEL_PLL0USB (7 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0USB */
|
||||
# define BASE_CGU_CLKSEL_PLL0AUDIO (8 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */
|
||||
# define BASE_CGU_CLKSEL_PLL1 (9 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL1 */
|
||||
# define BASE_CGU_CLKSEL_IDIVA (12 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVA */
|
||||
# define BASE_CGU_CLKSEL_IDIVB (13 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVB */
|
||||
# define BASE_CGU_CLKSEL_IDIVC (14 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVC */
|
||||
# define BASE_CGU_CLKSEL_IDIVD (15 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVD */
|
||||
# define BASE_CGU_CLKSEL_IDIVE (16 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVE */
|
||||
/* Bits 29-31: Reserved */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H */
|
||||
Loading…
Reference in New Issue