Add header files for PINSEL and SPI
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@1031 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -181,23 +181,25 @@
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#define LPC214X_AD_ADDR7_OFFSET 0x2c /* A/D Chanel 0 Data Register */
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#define LPC214X_AD_ADSTAT_OFFSET 0x30 /* A/D Status Register */
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/* Pin function select registers (these are normally referenced as offsets) */
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/* SPI0 register offsets */
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#define LPC214X_PINSEL0 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET)
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#define LPC214X_PINSEL1 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET)
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#define LPC214X_PINSEL2 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET)
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#define LPC214X_SPI0_CR_OFFSET 0x00 /* Control Register 0 */
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#define LPC214X_SPI0_SR_OFFSET 0x04 /* Control Register 1 */
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#define LPC214X_SPI0_DR_OFFSET 0x08 /* Data Register */
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#define LPC214X_SPI0_CCR_OFFSET 0x0c /* Status Register */
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#define LPC214X_SPI0_INT_OFFSET 0x1c /* Clock Pre-Scale Regisrer */
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/* SPI register offsets */
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/* SPI1 register offsets */
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#define LPC214X_SPI_CR0_OFFSET 0x00 /* Control Register 0 */
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#define LPC214X_SPI_CR1_OFFSET 0x04 /* Control Register 1 */
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#define LPC214X_SPI_DR_OFFSET 0x08 /* Data Register */
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#define LPC214X_SPI_SR_OFFSET 0x0c /* Status Register */
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#define LPC214X_SPI_CPSR_OFFSET 0x10 /* Clock Pre-Scale Regisrer */
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#define LPC214X_SPI_IMSC_OFFSET 0x14 /* Interrupt Mask Set and Clear Register */
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#define LPC214X_SPI_RIS_OFFSET 0x18 /* Raw Interrupt Status Register */
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#define LPC214X_SPI_MIS_OFFSET 0x1c /* Masked Interrupt Status Register */
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#define LPC214X_SPI_ICR_OFFSET 0x20 /* Interrupt Clear Register */
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#define LPC214X_SPI1_CR0_OFFSET 0x00 /* Control Register 0 */
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#define LPC214X_SPI1_CR1_OFFSET 0x04 /* Control Register 1 */
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#define LPC214X_SPI1_DR_OFFSET 0x08 /* Data Register */
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#define LPC214X_SPI1_SR_OFFSET 0x0c /* Status Register */
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#define LPC214X_SPI1_CPSR_OFFSET 0x10 /* Clock Pre-Scale Regisrer */
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#define LPC214X_SPI1_IMSC_OFFSET 0x14 /* Interrupt Mask Set and Clear Register */
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#define LPC214X_SPI1_RIS_OFFSET 0x18 /* Raw Interrupt Status Register */
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#define LPC214X_SPI1_MIS_OFFSET 0x1c /* Masked Interrupt Status Register */
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#define LPC214X_SPI1_ICR_OFFSET 0x20 /* Interrupt Clear Register */
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/* RTC register offsets */
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@ -43,6 +43,7 @@
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#include "chip.h"
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#include "lpc214x_pll.h"
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#include "lpc214x_apb.h"
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#include "lpc214x_pinsel.h"
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#include "up_internal.h"
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#include "up_arch.h"
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@ -40,6 +40,7 @@
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#include <nuttx/config.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "lpc214x_pinsel.h"
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#include "lpc214x_uart.h"
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/**************************************************************************
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/************************************************************************************
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* arch/arm/src/lpc214x/lpc214x_pinsl.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef _ARCH_ARM_SRC_LPC214X_PINSEL_H
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#define _ARCH_ARM_SRC_LPC214X_PINSEL_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register address definitions *****************************************************/
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#define LPC214X_PINSEL0 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET)
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#define LPC214X_PINSEL1 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET)
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#define LPC214X_PINSEL2 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET)
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/* Register bit definitions *********************************************************/
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#define LPC214X_PINSEL0_P00_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P00_TXD0 (0x00000001)
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#define LPC214X_PINSEL0_P00_PWM1 (0x00000002)
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#define LPC214X_PINSEL0_P00_RSVD3 (0x00000003)
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#define LPC214X_PINSEL0_P00_MASK (0x00000003)
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#define LPC214X_PINSEL0_P01_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P01_RXD0 (0x00000004)
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#define LPC214X_PINSEL0_P01_PWM3 (0x00000008)
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#define LPC214X_PINSEL0_P01_EINT0 (0x0000000c)
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#define LPC214X_PINSEL0_P01_MASK (0x0000000c)
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#define LPC214X_PINSEL0_P02_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P02_SCL0 (0x00000010)
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#define LPC214X_PINSEL0_P02_CAP00 (0x00000020)
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#define LPC214X_PINSEL0_P02_RSVD3 (0x00000030)
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#define LPC214X_PINSEL0_P02_MASK (0x00000030)
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#define LPC214X_PINSEL0_P03_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P03_SDA0 (0x00000040)
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#define LPC214X_PINSEL0_P03_MAT00 (0x00000080)
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#define LPC214X_PINSEL0_P03_EINT1 (0x000000c0)
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#define LPC214X_PINSEL0_P03_MASK (0x000000c0)
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#define LPC214X_PINSEL0_P04_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P04_SCK0 (0x00000100)
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#define LPC214X_PINSEL0_P04_CAP01 (0x00000200)
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#define LPC214X_PINSEL0_P04_RSVD3 (0x00000300)
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#define LPC214X_PINSEL0_P04_MASK (0x00000300)
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#define LPC214X_PINSEL0_P05_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P05_MISO0 (0x00000400)
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#define LPC214X_PINSEL0_P05_MAT01 (0x00000800)
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#define LPC214X_PINSEL0_P05_AD06 (0x00000c00)
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#define LPC214X_PINSEL0_P05_MASK (0x00000c00)
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#define LPC214X_PINSEL0_P06_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P06_MOSI0 (0x00001000)
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#define LPC214X_PINSEL0_P06_CAP02 (0x00002000)
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#define LPC214X_PINSEL0_P06_AD10 (0x00003000)
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#define LPC214X_PINSEL0_P06_MASK (0x00003000)
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#define LPC214X_PINSEL0_P07_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P07_SSEL0 (0x00004000)
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#define LPC214X_PINSEL0_P07_PWM2 (0x00008000)
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#define LPC214X_PINSEL0_P07_EINT2 (0x0000c000)
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#define LPC214X_PINSEL0_P07_MASK (0x0000c000)
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#define LPC214X_PINSEL0_P08_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P08_TXD1 (0x00010000)
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#define LPC214X_PINSEL0_P08_PWM4 (0x00020000)
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#define LPC214X_PINSEL0_P08_AD11 (0x00030000)
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#define LPC214X_PINSEL0_P08_MASK (0x00030000)
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#define LPC214X_PINSEL0_P09_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P09_RXD1 (0x00040000)
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#define LPC214X_PINSEL0_P09_PWM6 (0x00080000)
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#define LPC214X_PINSEL0_P09_EINT3 (0x000c0000)
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#define LPC214X_PINSEL0_P09_MASK (0x000c0000)
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#define LPC214X_PINSEL0_P010_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P010_RTS1 (0x00100000)
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#define LPC214X_PINSEL0_P010_CAP10 (0x00200000)
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#define LPC214X_PINSEL0_P010_AD12 (0x00300000)
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#define LPC214X_PINSEL0_P010_MASK (0x00300000)
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#define LPC214X_PINSEL0_P011_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P011_CTS1 (0x00400000)
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#define LPC214X_PINSEL0_P011_CAP11 (0x00800000)
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#define LPC214X_PINSEL0_P011_SCL1 (0x00c00000)
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#define LPC214X_PINSEL0_P011_MASK (0x00c00000)
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#define LPC214X_PINSEL0_P012_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P012_DSR1 (0x01000000)
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#define LPC214X_PINSEL0_P012_MAT10 (0x02000000)
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#define LPC214X_PINSEL0_P012_AD13 (0x03000000)
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#define LPC214X_PINSEL0_P012_MASK (0x03000000)
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#define LPC214X_PINSEL0_P013_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P013_DTR1 (0x04000000)
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#define LPC214X_PINSEL0_P013_MAT11 (0x08000000)
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#define LPC214X_PINSEL0_P013_AD14 (0x0c000000)
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#define LPC214X_PINSEL0_P013_MASK (0x0c000000)
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#define LPC214X_PINSEL0_P014_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P014_DCD1 (0x10000000)
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#define LPC214X_PINSEL0_P014_EINT1 (0x20000000)
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#define LPC214X_PINSEL0_P014_SDA1 (0x30000000)
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#define LPC214X_PINSEL0_P014_MASK (0x30000000)
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#define LPC214X_PINSEL0_P015_GPIO (0x00000000)
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#define LPC214X_PINSEL0_P015_RI1 (0x40000000)
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#define LPC214X_PINSEL0_P015_EINT2 (0x80000000)
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#define LPC214X_PINSEL0_P015_AD15 (0xc0000000)
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#define LPC214X_PINSEL0_P015_MASK (0xc0000000)
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#define LPC214X_PINSEL1_P016_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P016_EINT0 (0x00000001)
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#define LPC214X_PINSEL1_P016_MAT02 (0x00000002)
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#define LPC214X_PINSEL1_P016_CAP02 (0x00000003)
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#define LPC214X_PINSEL1_P016_MASK (0x00000003)
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#define LPC214X_PINSEL1_P017_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P017_CAP12 (0x00000004)
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#define LPC214X_PINSEL1_P017_SCK1 (0x00000008)
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#define LPC214X_PINSEL1_P017_MAT12 (0x0000000c)
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#define LPC214X_PINSEL1_P017_MASK (0x0000000c)
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#define LPC214X_PINSEL1_P018_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P018_CAP13 (0x00000010)
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#define LPC214X_PINSEL1_P018_MISO1 (0x00000020)
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#define LPC214X_PINSEL1_P018_MAT13 (0x00000030)
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#define LPC214X_PINSEL1_P018_MASK (0x00000030)
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#define LPC214X_PINSEL1_P019_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P019_MAT12 (0x00000040)
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#define LPC214X_PINSEL1_P019_MOSI1 (0x00000080)
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#define LPC214X_PINSEL1_P019_CAP12 (0x000000c0)
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#define LPC214X_PINSEL1_P019_MASK (0x000000c0)
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#define LPC214X_PINSEL1_P020_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P020_MAT13 (0x00000100)
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#define LPC214X_PINSEL1_P020_SSEL1 (0x00000200)
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#define LPC214X_PINSEL1_P020_EINT3 (0x00000300)
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#define LPC214X_PINSEL1_P020_MASK (0x00000300)
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#define LPC214X_PINSEL1_P021_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P021_PWM5 (0x00000400)
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#define LPC214X_PINSEL1_P021_AD16 (0x00000800)
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#define LPC214X_PINSEL1_P021_CAP13 (0x00000c00)
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#define LPC214X_PINSEL1_P021_MASK (0x00000c00)
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#define LPC214X_PINSEL1_P022_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P022_AD17 (0x00001000)
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#define LPC214X_PINSEL1_P022_CAP00 (0x00002000)
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#define LPC214X_PINSEL1_P022_MAT00 (0x00003000)
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#define LPC214X_PINSEL1_P022_MASK (0x00003000)
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#define LPC214X_PINSEL1_P023_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P023_VBUS (0x00004000)
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#define LPC214X_PINSEL1_P023_RSVD2 (0x00008000)
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#define LPC214X_PINSEL1_P023_RSVD3 (0x0000c000)
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#define LPC214X_PINSEL1_P023_MASK (0x0000c000)
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#define LPC214X_PINSEL1_P024_RSVD0 (0x00000000)
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#define LPC214X_PINSEL1_P024_RSVD1 (0x00010000)
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#define LPC214X_PINSEL1_P024_RSVD2 (0x00020000)
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#define LPC214X_PINSEL1_P024_RSVD3 (0x00030000)
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#define LPC214X_PINSEL1_P024_MASK (0x00030000)
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#define LPC214X_PINSEL1_P025_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P025_AD04 (0x00040000)
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#define LPC214X_PINSEL1_P025_AOUT (0x00080000)
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#define LPC214X_PINSEL1_P025_RSVD3 (0x000c0000)
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#define LPC214X_PINSEL1_P025_MASK (0x000c0000)
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#define LPC214X_PINSEL1_P026_RSVD0 (0x00000000)
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#define LPC214X_PINSEL1_P026_RSVD1 (0x00100000)
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#define LPC214X_PINSEL1_P026_RSVD2 (0x00200000)
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#define LPC214X_PINSEL1_P026_RSVD3 (0x00300000)
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#define LPC214X_PINSEL1_P026_MASK (0x00300000)
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#define LPC214X_PINSEL1_P027_RSVD0 (0x00000000)
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#define LPC214X_PINSEL1_P027_RSVD1 (0x00400000)
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#define LPC214X_PINSEL1_P027_RSVD2 (0x00800000)
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#define LPC214X_PINSEL1_P027_RSVD3 (0x00c00000)
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#define LPC214X_PINSEL1_P027_MASK (0x00c00000)
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#define LPC214X_PINSEL1_P028_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P028_AD01 (0x01000000)
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#define LPC214X_PINSEL1_P028_CAP02 (0x02000000)
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#define LPC214X_PINSEL1_P028_MAT02 (0x03000000)
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#define LPC214X_PINSEL1_P028_MASK (0x03000000)
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#define LPC214X_PINSEL1_P029_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P029_AD02 (0x04000000)
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#define LPC214X_PINSEL1_P029_CAP03 (0x08000000)
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#define LPC214X_PINSEL1_P029_MAT03 (0x0c000000)
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#define LPC214X_PINSEL1_P029_MASK (0x0c000000)
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#define LPC214X_PINSEL1_P030_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P030_AD03 (0x10000000)
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#define LPC214X_PINSEL1_P030_EINT3 (0x20000000)
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#define LPC214X_PINSEL1_P030_CAP00 (0x30000000)
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#define LPC214X_PINSEL1_P030_MASK (0x30000000)
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#define LPC214X_PINSEL1_P031_GPIO (0x00000000)
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#define LPC214X_PINSEL1_P031_UPLED (0x40000000)
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#define LPC214X_PINSEL1_P031_CONNECT (0x80000000)
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#define LPC214X_PINSEL1_P031_RSVD3 (0xc0000000)
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#define LPC214X_PINSEL1_P031_MASK (0xc0000000)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* _ARCH_ARM_SRC_LPC214X_PINSEL_H */
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#include "os_internal.h"
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#include "up_internal.h"
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#include "lpc214x_pinsel.h"
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#include "lpc214x_uart.h"
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#ifdef CONFIG_USE_SERIALDRIVER
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/************************************************************************************
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* arch/arm/src/lpc214x/lpc214x_spi.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef _ARCH_ARM_SRC_LPC214X_SPI_H
|
||||
#define _ARCH_ARM_SRC_LPC214X_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register address definitions *****************************************************/
|
||||
|
||||
/* SPI absolute register addresses */
|
||||
|
||||
#define LPC214X_SPI0_CR (LPC214X_SPI0_BASE+LPC214X_SPI0_CR_OFFSET) /* 16-bits wide */
|
||||
#define LPC214X_SPI0_SR (LPC214X_SPI0_BASE+LPC214X_SPI0_SR_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI0_DR (LPC214X_SPI0_BASE+LPC214X_SPI0_DR_OFFSET) /* 16-bits wide */
|
||||
#define LPC214X_SPI0_CCR (LPC214X_SPI0_BASE+LPC214X_SPI0_CCR_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI0_INT (LPC214X_SPI0_BASE+LPC214X_SPI0_INT_OFFSET) /* 8-bits wide */
|
||||
|
||||
#define LPC214X_SPI1_CR0 (LPC214X_SPI1_BASE+LPC214X_SPI1_CR0_OFFSET) /* 16-bits wide */
|
||||
#define LPC214X_SPI1_CR1 (LPC214X_SPI1_BASE+LPC214X_SPI1_CR1_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI1_DR (LPC214X_SPI1_BASE+LPC214X_SPI1_DR_OFFSET) /* 16-bits wide */
|
||||
#define LPC214X_SPI1_SR (LPC214X_SPI1_BASE+LPC214X_SPI1_SR_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI1_CPSR (LPC214X_SPI1_BASE+LPC214X_SPI1_IMSC_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI1_IMSC (LPC214X_SPI1_BASE+LPC214X_SPI1_IMSC_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI1_RIS (LPC214X_SPI1_BASE+LPC214X_SPI1_RIS_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI1_MIS (LPC214X_SPI1_BASE+LPC214X_SPI1_ICR_OFFSET) /* 8-bits wide */
|
||||
#define LPC214X_SPI1_ICR (LPC214X_SPI1_BASE+LPC214X_SPI1_ICR_OFFSET) /* 8-bits wide */
|
||||
|
||||
/* SPI0 register bit definitions ****************************************************/
|
||||
|
||||
/* Control Register (CR) for SPI0 */
|
||||
|
||||
#define LPC214X_SPI0CR0_BITSENB (0x0004) /* Bit 2=0: 8-bits, else see bits 8-11 */
|
||||
#define LPC214X_SPI0CR0_CPHA (0x0008) /* Bit 3: Clock phase control */
|
||||
#define LPC214X_SPI0CR0_CPOL (0x0010) /* Bit 4: Clock polarity control */
|
||||
#define LPC214X_SPI0CR0_MSTR (0x0020) /* Bit 5=1: Master 0: Slave */
|
||||
#define LPC214X_SPI0CR0_LSBF (0x0040) /* Bit 6=1: Shift LSB first */
|
||||
#define LPC214X_SPI0CR0_SPIE (0x0080) /* Bit 7=1: SPI interrupt enable */
|
||||
#define LPC214X_SPI0CR0_BITSMASK (0x0f00) /* Bits 8-11: Number of bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS8 (0x0800) /* 8-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS9 (0x0900) /* 9-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS10 (0x0a00) /* 10-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS11 (0x0b00) /* 11-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS12 (0x0c00) /* 12-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS13 (0x0d00) /* 13-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS14 (0x0e00) /* 14-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS15 (0x0f00) /* 15-bits per transfer */
|
||||
#define LPC214X_SPI0CR0_BITS16 (0x0000) /* 16-bits per transfer */
|
||||
|
||||
/* Status Regiser (SR) for SPI0 */
|
||||
|
||||
#define LPC214X_SPI0SR_ABRT (0x08) /* Bit 3=1: Slave abort */
|
||||
#define LPC214X_SPI0SR_MODF (0x10) /* Bit 4=1: Mode fault */
|
||||
#define LPC214X_SPI0SR_ROVR (0x20) /* Bit 5=1: Read overrun */
|
||||
#define LPC214X_SPI0SR_WCOL (0x40) /* Bit 6=1: Write collision */
|
||||
#define LPC214X_SPI0SR_SPIF (0x80) /* Bit 7=1: SPI transfer complete */
|
||||
|
||||
/* Interrupt Register for SPI0 */
|
||||
|
||||
#define LPC214X_SPO0INT_SPI (0x01) /* Bit 0=1: SPI interrupt */
|
||||
|
||||
/* SPI1 register bit definitions ****************************************************/
|
||||
|
||||
/* Control Register 0 (CR0) for SPI1 */
|
||||
|
||||
#define LPC214X_SPI1CR0_DSSMASK (0x000f) /* Bits 0-3: Data size select mask */
|
||||
#define LPC214X_SPI1CR0_DSS4BIT (0x0003) /* 4-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS5BIT (0x0004) /* 5-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS6BIT (0x0005) /* 6-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS7BIT (0x0006) /* 7-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS8BIT (0x0007) /* 8-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS9BIT (0x0008) /* 9-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS10BIT (0x0009) /* 10-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS11BIT (0x000a) /* 11-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS12BIT (0x000b) /* 12-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS13BIT (0x000c) /* 13-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS14BIT (0x000d) /* 14-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS15BIT (0x000e) /* 15-bit transfer */
|
||||
#define LPC214X_SPI1CR0_DSS16BIT (0x000f) /* 16-bit transfer */
|
||||
#define LPC214X_SPI1CR0_FRFMASK (0x0030) /* Bits 4-5: Frame format mask */
|
||||
#define LPC214X_SPI1CR0_FRFSPI (0x0000) /* SPI */
|
||||
#define LPC214X_SPI1CR0_FRFSSI (0x0010) /* SSI */
|
||||
#define LPC214X_SPI1CR0_FRFMW (0x0020) /* Microwire */
|
||||
#define LPC214X_SPI1CR0_CPOL (0x0040) /* Bit 6: Clock polarity control */
|
||||
#define LPC214X_SPI1CR0_CPHA (0x0080) /* Bit 7: Clock phase control */
|
||||
#define LPC214X_SPI1CR0_SCR (0xff00) /* Bits 8-15: Serial clock reate */
|
||||
|
||||
/* Control Register 1 (CR1) */
|
||||
|
||||
#define LPC214X_SPI1CR1_LBM (0x01) /* Bit 0: 1=Loopback mode */
|
||||
#define LPC214X_SPI1CR1_SSE (0x02) /* Bit 1: 1=SSP enable */
|
||||
#define LPC214X_SPI1CR1_MS (0x04) /* Bit 2: 1=Controller is slave */
|
||||
#define LPC214X_SPI1CR1_SOD (0x08) /* Bit 3: 1=Slave output disable */
|
||||
|
||||
/* SSP Status Register (SR) */
|
||||
|
||||
#define LPC214X_SPI1SR_TFE (0x01) /* Bit 0: 1=Transmit FIFO Empty */
|
||||
#define LPC214X_SPI1SR_TNF (0x02) /* Bit 1: 1=Transmit FIFO not full */
|
||||
#define LPC214X_SPI1SR_RNE (0x04) /* Bit 2: 1=Receive FIFO not empty */
|
||||
#define LPC214X_SPI1SR_RFF (0x08) /* Bit 3: 1=Receive FIFO full */
|
||||
#define LPC214X_SPI1SR_BSY (0x10) /* Bit 4: 1=Busy */
|
||||
|
||||
/* Interrupt set/clear/status/mask registers (can't clear RXIM or TXIM) */
|
||||
|
||||
#define LPC214X_SP1INT_ROR (0x01) /* Bit 0: 1=Recieve Overrun */
|
||||
#define LPC214X_SP1INT_RTIM (0x02) /* Bit 1: 1=Recieve Timeout */
|
||||
#define LPC214X_SP1INT_RXIM (0x04) /* Bit 2: 1=RX FIFO at least half full */
|
||||
#define LPC214X_SP1INT_TXIM (0x08) /* Bit 3: 1=TX FIFO at least half empty */
|
||||
|
||||
/* SPI1 supports an 8-frame FIFO */
|
||||
|
||||
#define LPC214X_SPI1_FIFOSZ (8)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* _ARCH_ARM_SRC_LPC214X_SPI_H */
|
||||
Loading…
Reference in New Issue