Add LPC3154 OTP header file
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3646 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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/************************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_cgu.h
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*
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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@ -1456,6 +1456,11 @@
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#define CGU_NANDECCRST_RESET (1 << 0) /* Bit 0: Reset for ECC clock domain of Nandflash Controller */
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/* NANDFLASH_CTRL_AES_RESET_N_SOFT register, address 0x13004cc8 (LPC3154 only) */
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#define CGU_NANDAECRST_RESET (1 << 0) /* Bit 0: Reset for AES clock domain of
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Nandflash Controller */
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/* NANDFLASH_CTRL_NAND_RESET_N_SOFT register, address 0x13004ccc */
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#define CGU_NANDCTRLRST_RESET (1 << 0) /* Bit 0: Reset for Nandflash Controller */
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#define LPC31_APB0_SYSCREG_OFFSET 0x00002800 /* SYSCREG block */
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#define LPC31_APB0_IOCONFIG_OFFSET 0x00003000 /* IOCONFIG */
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#define LPC31_APB0_GCU_OFFSET 0x00004000 /* GCU */
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#define LPC31_APB0_OTP_OFFSET 0x00005000 /* USB OTG */
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#define LPC31_APB0_OTP_OFFSET 0x00005000 /* USB OTG (LPC315x only) */
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#define LPC31_APB0_RNG_OFFSET 0x00006000 /* RNG */
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#define LPC31_APB1_TIMER0_OFFSET 0x00000000 /* TIMER0 */
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/************************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_otp.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_OTP_H
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#define __ARCH_ARM_SRC_LPC31XX_LPC31_OTP_H
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "lpc31_memorymap.h"
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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/* Virtual and physical base address of the OTG register group **********************************/
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#define LPC31_OTG_VBASE (LPC31_APB0_VADDR+LPC31_APB0_OTP_OFFSET)
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#define LPC31_OTG_PBASE (LPC31_APB0_PADDR+LPC31_APB0_OTP_OFFSET)
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/* OTP register offsets (with respect to the RNG base) ******************************************/
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#define LPC31_OTP_CON_OFFSET 0x000 /* Control Register */
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#define LPC31_OTP_RPROT_OFFSET 0x004 /* Read-protect Register */
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#define LPC31_OTP_WPROT_OFFSET 0x008 /* Write-protect Register */
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#define LPC31_OTP_DATA_OFFSET(n) (0x00c + ((n) << 2)
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#define LPC31_OTP_DATA0_OFFSET 0x00c /* Fuse-output data register 0 */
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#define LPC31_OTP_DATA1_OFFSET 0x010 /* Fuse-output data register 1 */
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#define LPC31_OTP_DATA2_OFFSET 0x014 /* Fuse-output data register 2 */
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#define LPC31_OTP_DATA3_OFFSET 0x018 /* Fuse-output data register 3 */
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#define LPC31_OTP_DATA4_OFFSET 0x01c /* Fuse-output data register 4 */
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#define LPC31_OTP_DATA5_OFFSET 0x020 /* Fuse-output data register 5 */
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#define LPC31_OTP_DATA6_OFFSET 0x024 /* Fuse-output data register 6 */
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#define LPC31_OTP_DATA7_OFFSET 0x028 /* Fuse-output data register 7 */
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#define LPC31_OTP_DATA8_OFFSET 0x02c /* Fuse-output data register 8 */
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#define LPC31_OTP_DATA9_OFFSET 0x030 /* Fuse-output data register 9 */
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#define LPC31_OTP_DATA10_OFFSET 0x034 /* Fuse-output data register 10 */
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#define LPC31_OTP_DATA11_OFFSET 0x038 /* Fuse-output data register 11 */
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#define LPC31_OTP_DATA12_OFFSET 0x03c /* Fuse-output data register 12 */
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#define LPC31_OTP_DATA13_OFFSET 0x040 /* Fuse-output data register 13 */
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#define LPC31_OTP_DATA14_OFFSET 0x044 /* Fuse-output data register 14 */
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#define LPC31_OTP_DATA15_OFFSET 0x048 /* Fuse-output data register 15 */
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/* OTP register (virtual) addresses *************************************************************/
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#define LPC31_OTP_CON (LPC31_OTG_VBASE+LPC31_OTP_CON_OFFSET)
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#define LPC31_OTP_RPROT (LPC31_OTG_VBASE+LPC31_OTP_RPROT_OFFSET)
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#define LPC31_OTP_WPROT (LPC31_OTG_VBASE+LPC31_OTP_WPROT_OFFSET)
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#define LPC31_OTP_DATA(n) (LPC31_OTG_VBASE+LPC31_OTP_DATA_OFFSET(n))
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#define LPC31_OTP_DATA0 (LPC31_OTG_VBASE+LPC31_OTP_DATA0_OFFSET)
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#define LPC31_OTP_DATA1 (LPC31_OTG_VBASE+LPC31_OTP_DATA1_OFFSET)
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#define LPC31_OTP_DATA2 (LPC31_OTG_VBASE+LPC31_OTP_DATA2_OFFSET)
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#define LPC31_OTP_DATA3 (LPC31_OTG_VBASE+LPC31_OTP_DATA3_OFFSET)
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#define LPC31_OTP_DATA4 (LPC31_OTG_VBASE+LPC31_OTP_DATA4_OFFSET)
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#define LPC31_OTP_DATA5 (LPC31_OTG_VBASE+LPC31_OTP_DATA5_OFFSET)
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#define LPC31_OTP_DATA6 (LPC31_OTG_VBASE+LPC31_OTP_DATA6_OFFSET)
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#define LPC31_OTP_DATA7 (LPC31_OTG_VBASE+LPC31_OTP_DATA7_OFFSET)
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#define LPC31_OTP_DATA8 (LPC31_OTG_VBASE+LPC31_OTP_DATA8_OFFSET)
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#define LPC31_OTP_DATA9 (LPC31_OTG_VBASE+LPC31_OTP_DATA9_OFFSET)
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#define LPC31_OTP_DATA10 (LPC31_OTG_VBASE+LPC31_OTP_DATA10_OFFSET)
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#define LPC31_OTP_DATA11 (LPC31_OTG_VBASE+LPC31_OTP_DATA11_OFFSET)
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#define LPC31_OTP_DATA12 (LPC31_OTG_VBASE+LPC31_OTP_DATA12_OFFSET)
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#define LPC31_OTP_DATA13 (LPC31_OTG_VBASE+LPC31_OTP_DATA13_OFFSET)
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#define LPC31_OTP_DATA14 (LPC31_OTG_VBASE+LPC31_OTP_DATA14_OFFSET)
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#define LPC31_OTP_DATA15 (LPC31_OTG_VBASE+LPC31_OTP_DATA15_OFFSET)
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/* RNG register bit definitions *****************************************************************/
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/* Control Register */
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#define OTP_CON_ADRS_SHIFT (0) /* Bits 0-8: Address bits for accessing fuse data */
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#define OTP_CON_ADRS_MASK (0x1ff << OTP_CON_ADRS_SHIFT)
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#define OTP_CON_MODE_SHIFT (16) /* Bits 16-17: Selects: Idle, Copy and Write mode */
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#define OTP_CON_MODE_MASK (3 << OTP_CON_MODE_SHIFT)
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#define OTP_CON_JTAGEN (1 << 31) /* Bit 31: Enable ARM_JTAG clock */
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/* Read-protect Register */
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#define OTP_RPROT_PROT_SHIFT (0) /* Bits 0-15: Indicates which data registers are read-protected */
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#define OTP_RPROT_PROT_MASK (0xffff << OTP_RPROT_PROT_SHIFT)
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# define OTP_RPROT_PROT(n) ((1 << (n)) << TP_RPROT_PROT_SHIFT)
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#define OTP_RPROT_LOCK (1 << 31) /* Bit 31: Register values are 'sticky' */
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/* Write-protect Register */
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#define OTP_WPROT_PROT_SHIFT (0) /* Bits 0-15: Indicates which data registers are write-protected */
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#define OTP_WPROT_PROT_MASK (0xffff << OTP_RPROT_PROT_SHIFT)
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# define OTP_WPROT_PROT(n) ((1 << (n)) << TP_RPROT_PROT_SHIFT)
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#define OTP_WPROT_LOCK (1 << 31) /* Bit 31: Register values are 'sticky' */
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/* Fuse-output data register 0-15: Fuse output 0-511 (32 per data register, 32*16 = 512) */
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/************************************************************************************************
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* Public Types
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************************************************************************************************/
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/************************************************************************************************
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* Public Data
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************************************************************************************************/
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/************************************************************************************************
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* Public Functions
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************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_OTP_H */
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