More STM32 quadrature encoder code
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4391 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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@ -1,7 +1,7 @@
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32_tim.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -43,18 +43,68 @@
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#include <errno.h>
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/irq.h>
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#include <nuttx/sensors/qencoder.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "stm32_internal.h"
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#include "stm32_gpio.h"
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#include "stm32_tim.h"
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#include "stm32_qencoder.h"
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#ifdef CONFIG_QENCODER
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Debug ****************************************************************************/
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/* Non-standard debug that may be enabled just for testing QENCODER */
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#ifndef CONFIG_DEBUG
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# undef CONFIG_DEBUG_QENCODER
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#endif
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#ifdef CONFIG_DEBUG_QENCODER
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# define qedbg dbg
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# define qelldbg lldbg
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# ifdef CONFIG_DEBUG_VERBOSE
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# define qevdbg vdbg
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# define qellvdbg llvdbg
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# define stm32_dumpgpio(p,m) stm32_dumpgpio(p,m)
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# else
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# define qelldbg(x...)
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# define qellvdbg(x...)
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# define stm32_dumpgpio(p,m)
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# endif
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#else
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# define qedbg(x...)
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# define qelldbg(x...)
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# define qevdbg(x...)
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# define qellvdbg(x...)
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# define stm32_dumpgpio(p,m)
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#endif
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/* Constant configuration structure that is retained in FLASH */
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struct stm32_qeconfig_s
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{
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uint8_t timid; /* Timer ID {1,2,3,4,5,8} */
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uint8_t irq; /* Timer update IRQ */
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uint32_t base; /* Register base address */
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xcpt_t handler; /* Interrupt handler for this IRQ */
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};
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/* Overall, RAM-based state structure */
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struct stm32_lowerhalf_s
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{
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/* The first field of this state structure must be a pointer to the lower-
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@ -64,11 +114,52 @@ struct stm32_lowerhalf_s
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FAR const struct qe_ops_s *ops; /* Lower half callback structure */
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/* STM32 driver-specific fields: */
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FAR const struct stm32_qeconfig_s *config; /* static onfiguration */
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bool inuse; /* True: The lower-half driver is in-use */
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volatile int32_t position; /* The current position offset */
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};
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/************************************************************************************
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* Private Function Prototypes
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************************************************************************************/
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/* Helper functions */
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static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset);
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static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value);
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static uint32_t stm32_getreg32(FAR struct stm32_lowerhalf_s *priv, int offset);
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static void stm32_putreg32(FAR struct stm32_lowerhalf_s *priv, int offset, uint32_t value);
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#if defined(CONFIG_DEBUG_QENCODER) && defined(CONFIG_DEBUG_VERBOSE)
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static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, FAR const char *msg);
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#else
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# define stm32_dumpregs(priv,msg)
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#endif
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static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim);
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/* Interrupt handling */
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static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv);
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#ifdef CONFIG_STM32_TIM1
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static int stm32_tim1interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM2
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static int stm32_tim2interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM3
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static int stm32_tim3interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM4
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static int stm32_tim4interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM5
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static int stm32_tim5interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_STM32_TIM8
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static int stm32_tim8interrupt(int irq, FAR void *context);
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#endif
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/* Lower-half Quadrature Encoder Driver Methods */
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@ -78,12 +169,12 @@ static int stm32_position(FAR struct qe_lowerhalf_s *lower, int32_t *pos);
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static int stm32_reset(FAR struct qe_lowerhalf_s *lower);
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static int stm32_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned long arg);
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/************************************************************************************
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/* The lower half callback structure */
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FAR const struct qe_ops_s g_qecallbacks =
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static const struct qe_ops_s g_qecallbacks =
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{
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.setup = stm32_setup,
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.shutdown = stm32_shutdown,
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@ -92,10 +183,383 @@ FAR const struct qe_ops_s g_qecallbacks =
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.ioctl = stm32_ioctl,
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};
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/* Per-timer state structures */
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#ifdef CONFIG_STM32_TIM1
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static const struct stm32_qeconfig_s g_tim1config =
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{
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.timid = 1,
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.irq = STM32_IRQ_TIM1UP,
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.base = STM32_TIM1_BASE,
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.handler = stm32_tim1interrupt,
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};
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static struct stm32_lowerhalf_s g_tim1lower =
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{
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.ops = &g_qecallbacks,
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.config = &g_tim1config,
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.inuse = false,
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};
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#endif
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#ifdef CONFIG_STM32_TIM2
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static const struct stm32_qeconfig_s g_tim2config =
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{
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.timid = 2,
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.irq = STM32_IRQ_TIM2,
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.base = STM32_TIM2_BASE,
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.handler = stm32_tim2interrupt,
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};
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static struct stm32_lowerhalf_s g_tim2lower =
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{
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.ops = &g_qecallbacks,
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.config = &g_tim2config,
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.inuse = false,
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};
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#endif
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#ifdef CONFIG_STM32_TIM3
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static const struct stm32_qeconfig_s g_tim3config =
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{
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.timid = 3,
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.irq = STM32_IRQ_TIM3,
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.base = STM32_TIM3_BASE,
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.handler = stm32_tim3interrupt,
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};
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static struct stm32_lowerhalf_s g_tim3lower =
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{
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.ops = &g_qecallbacks,
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.config = &g_tim3config,
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.inuse = false,
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};
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#endif
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#ifdef CONFIG_STM32_TIM4
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static const struct stm32_qeconfig_s g_tim4config =
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{
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.timid = 4,
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.irq = STM32_IRQ_TIM4,
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.base = STM32_TIM4_BASE,
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.handler = stm32_tim4interrupt,
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};
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static struct stm32_lowerhalf_s g_tim4lower =
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{
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.ops = &g_qecallbacks,
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.config = &g_tim4config,
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.inuse = false,
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};
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#endif
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#ifdef CONFIG_STM32_TIM5
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static const struct stm32_qeconfig_s g_tim5config =
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{
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.timid = 5,
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.irq = STM32_IRQ_TIM5,
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.base = STM32_TIM5_BASE,
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.handler = stm32_tim5interrupt,
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};
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static struct stm32_lowerhalf_s g_tim5lower =
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{
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.ops = &g_qecallbacks,
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.config = &g_tim5config,
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.inuse = false,
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};
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#endif
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#ifdef CONFIG_STM32_TIM8
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static const struct stm32_qeconfig_s g_tim8config =
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{
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.timid = 8,
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.irq = STM32_IRQ_TIM8UP,
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.base = STM32_TIM8_BASE,
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.handler = stm32_tim8interrupt,
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};
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static struct stm32_lowerhalf_s g_tim8lower =
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{
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.ops = &g_qecallbacks,
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.config = &g_tim8config
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.inuse = false,
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};
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#endif
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_getreg16
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*
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* Description:
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* Read the value of a 16-bit timer register.
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*
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* Input Parameters:
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* priv - A reference to the lower half status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* The current contents of the specified register
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*
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************************************************************************************/
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static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset)
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{
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return getreg16(priv->config->base + offset);
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}
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/************************************************************************************
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* Name: stm32_putreg16
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*
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* Description:
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* Write a value to a 16-bit timer register.
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*
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* Input Parameters:
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* priv - A reference to the lower half status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value)
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{
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putreg16(value, priv->config->base + offset);
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}
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/************************************************************************************
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* Name: stm32_getreg32
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*
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* Description:
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* Read the value of a 32-bit timer register. This applies only for the STM32 F4
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* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but works OK
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* with the 16-bit TIM1,8 and F1 registers).
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*
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* Input Parameters:
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* priv - A reference to the lower half status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* The current contents of the specified register
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*
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************************************************************************************/
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static uint32_t stm32_getreg32(FAR struct stm32_lowerhalf_s *priv, int offset)
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{
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return getreg32(priv->config->base + offset);
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}
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/************************************************************************************
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* Name: stm32_putreg16
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*
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* Description:
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* Write a value to a 32-bit timer register. This applies only for the STM32 F4
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* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but works OK
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* with the 16-bit TIM1,8 and F1 registers).
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*
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* Input Parameters:
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* priv - A reference to the lower half status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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static void stm32_putreg32(FAR struct stm32_lowerhalf_s *priv, int offset, uint32_t value)
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{
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putreg32(value, priv->config->base + offset);
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}
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/****************************************************************************
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* Name: stm32_dumpregs
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*
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* Description:
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* Dump all timer registers.
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*
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* Input parameters:
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* priv - A reference to the QENCODER block status
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#if defined(CONFIG_DEBUG_QENCODER) && defined(CONFIG_DEBUG_VERBOSE)
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static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, FAR const char *msg)
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{
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qevdbg("%s:\n", msg);
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qevdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
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stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET));
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qevdbg(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
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stm32_getreg16(priv, STM32_GTIM_SR_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET));
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qevdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
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stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET));
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qevdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
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stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET));
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#if defined(CONFIG_STM32_TIM1_QENCODER) || defined(CONFIG_STM32_TIM8_QENCODER)
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if (priv->timtype == TIMTYPE_ADVANCED)
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{
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qevdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
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stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET),
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stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET),
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stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET),
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stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET));
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}
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else
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#endif
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{
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qevdbg(" DCR: %04x DMAR: %04x\n",
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stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET),
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stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET));
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}
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}
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#endif
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/************************************************************************************
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* Name: stm32_tim2lower
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*
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* Description:
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* Map a timer number to a device structure
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*
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************************************************************************************/
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static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim)
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{
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switch (tim)
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{
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#ifdef CONFIG_STM32_TIM1
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case 1:
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return &g_tim1lower;
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#endif
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#ifdef CONFIG_STM32_TIM2
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case 2:
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return &g_tim2lower;
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#endif
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#ifdef CONFIG_STM32_TIM3
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case 3:
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#endif
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#ifdef CONFIG_STM32_TIM4
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case 4:
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return &g_tim4lower;
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#endif
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#ifdef CONFIG_STM32_TIM5
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case 5:
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return &g_tim5lower;
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#endif
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#ifdef CONFIG_STM32_TIM8
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case 8:
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return &g_tim8lower;
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#endif
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default:
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return NULL;
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}
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}
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/************************************************************************************
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* Name: stm32_setup
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*
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* Description:
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* Common timer interrupt handling
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*
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************************************************************************************/
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static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv)
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{
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uint16_t regval;
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/* Verify that this is an update interrupt. Nothing else is expected. */
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regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET);
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DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
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/* Clear the UIF interrupt bit */
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stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF);
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/* Check the direction bit in the CR1 register and add or subtract the
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* maximum value, as appropriate.
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*/
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regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET);
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if ((regval & ATIM_CR1_DIR) != 0)
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{
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priv->position -= (int32_t)0x0000fff0;
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}
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else
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{
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priv->position += (int32_t)0x0000fff0;
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}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_intNinterrupt
|
||||
*
|
||||
* Description:
|
||||
* TIMN interrupt handler
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_TIM1
|
||||
static int stm32_tim1interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_interrupt(&g_tim1lower);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM2
|
||||
static int stm32_tim2interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_interrupt(&g_tim2lower);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM3
|
||||
static int stm32_tim3interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_interrupt(&g_tim3lower);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM4
|
||||
static int stm32_tim4interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_interrupt(&g_tim4lower);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM5
|
||||
static int stm32_tim5interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_interrupt(&g_tim5lower);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM8
|
||||
static int stm32_tim8interrupt(int irq, FAR void *context)
|
||||
{
|
||||
return stm32_interrupt(&g_tim8lower);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_setup
|
||||
*
|
||||
|
|
@ -138,8 +602,33 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
|
|||
|
||||
static int stm32_position(FAR struct qe_lowerhalf_s *lower, int32_t *pos)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
|
||||
int32_t position;
|
||||
int32_t verify;
|
||||
uint32_t count;
|
||||
|
||||
DEBUGASSERT(lower && priv->inuse);
|
||||
|
||||
/* Loop until we are certain that no interrupt occurred between samples */
|
||||
|
||||
do
|
||||
{
|
||||
/* Don't let another task pre-empt us until we get the measurement. The timer
|
||||
* interrupt may still be processed
|
||||
*/
|
||||
|
||||
sched_lock();
|
||||
position = priv->position;
|
||||
count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET);
|
||||
verify = priv->position;
|
||||
sched_unlock();
|
||||
}
|
||||
while (position != verify);
|
||||
|
||||
/* Return the position measurement */
|
||||
|
||||
*pos = position + (int32_t)count;
|
||||
return OK;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
|
|
@ -152,8 +641,20 @@ static int stm32_position(FAR struct qe_lowerhalf_s *lower, int32_t *pos)
|
|||
|
||||
static int stm32_reset(FAR struct qe_lowerhalf_s *lower)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
|
||||
irqstate_t flags;
|
||||
|
||||
DEBUGASSERT(lower && priv->inuse);
|
||||
|
||||
/* Reset the timer and the counter. Interrupts are disabled to make this atomic
|
||||
* (if possible)
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0);
|
||||
priv->position = 0;
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
|
|
@ -184,38 +685,44 @@ static int stm32_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned long
|
|||
*
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
|
||||
* tim - The timer number to used. time must be an element of {1,2,3,4,5,8}
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; A negated errno value is returned on failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_qeinitialize(FAR const char *devpath)
|
||||
int stm32_qeinitialize(FAR const char *devpath, int tim)
|
||||
{
|
||||
FAR struct stm32_lowerhalf_s *lower;
|
||||
FAR struct stm32_lowerhalf_s *priv;
|
||||
int ret;
|
||||
|
||||
/* Allocate an instance to the device-specific, lower-half state structure */
|
||||
/* Find the pre-allocated timer state structure corresponding to this timer */
|
||||
|
||||
lower = (FAR struct stm32_lowerhalf_s *)kmalloc(sizeof(struct stm32_lowerhalf_s));
|
||||
if (lower)
|
||||
priv = stm32_tim2lower(tim);
|
||||
if (priv)
|
||||
{
|
||||
return -ENOMEM;
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* Initialize the allocated state structure */
|
||||
/* Make sure that it is available */
|
||||
|
||||
lower->ops = &g_qecallbacks;
|
||||
if (priv->inuse)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Register the lower-half driver */
|
||||
/* Register the priv-half driver */
|
||||
|
||||
ret = qe_register(devpath, (FAR struct qe_lowerhalf_s *)lower);
|
||||
ret = qe_register(devpath, (FAR struct qe_lowerhalf_s *)priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
kfree(lower);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* The driver is now in-use */
|
||||
|
||||
priv->inuse = true;
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -46,6 +46,47 @@
|
|||
|
||||
#ifdef CONFIG_QENCODER
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
/* Timer devices may be used for different purposes. One special purpose is as
|
||||
* a quadrature encoder input device. If CONFIG_STM32_TIMn is defined then the
|
||||
* CONFIG_STM32_TIMn_QE must also be defined to indicate that timer "n" is intended
|
||||
* to be used for as a quadrature encoder.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_STM32_TIM1
|
||||
# undef CONFIG_STM32_TIM1_QE
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM2
|
||||
# undef CONFIG_STM32_TIM2_QE
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM3
|
||||
# undef CONFIG_STM32_TIM3_QE
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM4
|
||||
# undef CONFIG_STM32_TIM4_QE
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM5
|
||||
# undef CONFIG_STM32_TIM5_QE
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM8
|
||||
# undef CONFIG_STM32_TIM8_QE
|
||||
#endif
|
||||
|
||||
/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder (at least for the
|
||||
* STM32 F4)
|
||||
*/
|
||||
|
||||
#undef CONFIG_STM32_TIM6_QE
|
||||
#undef CONFIG_STM32_TIM7_QE
|
||||
#undef CONFIG_STM32_TIM9_QE
|
||||
#undef CONFIG_STM32_TIM10_QE
|
||||
#undef CONFIG_STM32_TIM11_QE
|
||||
#undef CONFIG_STM32_TIM12_QE
|
||||
#undef CONFIG_STM32_TIM13_QE
|
||||
#undef CONFIG_STM32_TIM14_QE
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
|
@ -59,13 +100,14 @@
|
|||
*
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the driver to register. E.g., "/dev/qe0"
|
||||
* tim - The timer number to used. time must be an element of {1,2,3,4,5,8}
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; A negated errno value is returned on failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_qeinitialize(FAR const char *devpath);
|
||||
int stm32_qeinitialize(FAR const char *devpath, int tim);
|
||||
|
||||
#endif /* CONFIG_QENCODER */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_QENCODER_H */
|
||||
|
|
|
|||
|
|
@ -81,49 +81,67 @@
|
|||
* CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" is intended
|
||||
* to be used for that purpose.
|
||||
*
|
||||
* - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then
|
||||
* CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" is intended
|
||||
* to be used for that purpose.
|
||||
*
|
||||
* In any of these cases, the timer will not be used by this timer module.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || defined(CONFIG_STM32_TIM1_DAC)
|
||||
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \
|
||||
defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE)
|
||||
# undef CONFIG_STM32_TIM1
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || defined(CONFIG_STM32_TIM2_DAC)
|
||||
#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \
|
||||
defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE)
|
||||
# undef CONFIG_STM32_TIM2
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || defined(CONFIG_STM32_TIM3_DAC)
|
||||
#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \
|
||||
defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE)
|
||||
# undef CONFIG_STM32_TIM3
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || defined(CONFIG_STM32_TIM4_DAC)
|
||||
#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \
|
||||
defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE)
|
||||
# undef CONFIG_STM32_TIM4
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || defined(CONFIG_STM32_TIM5_DAC)
|
||||
#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \
|
||||
defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE)
|
||||
# undef CONFIG_STM32_TIM5
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || defined(CONFIG_STM32_TIM6_DAC)
|
||||
#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
|
||||
defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE)
|
||||
# undef CONFIG_STM32_TIM6
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || defined(CONFIG_STM32_TIM7_DAC)
|
||||
#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \
|
||||
defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE)
|
||||
# undef CONFIG_STM32_TIM7
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || defined(CONFIG_STM32_TIM8_DAC)
|
||||
#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \
|
||||
defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE)
|
||||
# undef CONFIG_STM32_TIM8
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || defined(CONFIG_STM32_TIM9_DAC)
|
||||
#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \
|
||||
defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE)
|
||||
# undef CONFIG_STM32_TIM9
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || defined(CONFIG_STM32_TIM10_DAC)
|
||||
#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \
|
||||
defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE)
|
||||
# undef CONFIG_STM32_TIM10
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || defined(CONFIG_STM32_TIM11_DAC)
|
||||
#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \
|
||||
defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE)
|
||||
# undef CONFIG_STM32_TIM11
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || defined(CONFIG_STM32_TIM12_DAC)
|
||||
#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \
|
||||
defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE)
|
||||
# undef CONFIG_STM32_TIM12
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || defined(CONFIG_STM32_TIM13_DAC)
|
||||
#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \
|
||||
defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE)
|
||||
# undef CONFIG_STM32_TIM13
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || defined(CONFIG_STM32_TIM14_DAC)
|
||||
#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \
|
||||
defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE)
|
||||
# undef CONFIG_STM32_TIM14
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue