Add network bit definitions
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3272 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -108,29 +108,63 @@
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/* Register Bit-Field Definitions ***************************************************/
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/* Network Control (8-bit) */
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#define EMAC_NETCTL_
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#define EMAC_NETCTL_FDX (1 << 1) /* Bit 1: Full Duplex */
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#define EMAC_NETCTL_MLB (1 << 2) /* Bit 2: MAC Loopback */
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#define EMAC_NETCTL_EXTPHY (1 << 3) /* Bit 3: External PHY */
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#define EMAC_NETCTL_ESWAI (1 << 4) /* Bit 4: EMAC Disabled during Wait Mode */
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#define EMAC_NETCTL_EMACE (1 << 7) /* Bit 7: EMAC Enable */
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/* Receive Control and Status (8-bit) */
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#define EMAC_RXCTS_
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#define EMAC_RXCTS_BCREJ (1 << 0) /* Bit 0: Broadcast Reject */
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#define EMAC_RXCTS_CONMC (1 << 1) /* Bit 1: Conditional Multicast */
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#define EMAC_RXCTS_PROM (1 << 2) /* Bit 2: Promiscuous Mode */
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#define EMAC_RXCTS_RFCE (1 << 4) /* Bit 4: Reception Flow Control Enable */
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#define EMAC_RXCTS_RXACT (1 << 7) /* Bit 7: Receiver Active Status */
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/* Transmit Control and Status (8-bit) */
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#define EMAC_TXCTS_
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#define EMAC_TXCTS_TCMD_SHIFT (0) /* Bits 0-1: Transmit Command */
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#define EMAC_TXCTS_TCMD_MASK (3)
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# define EMAC_TXCTS_TCMD_START (1) /* Transmit buffer frame */
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# define EMAC_TXCTS_TCMD_PAUSE (2) /* Transmit PAUSE frame (full-duplex mode only) */
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# define EMAC_TXCTS_TCMD_ABORT (3) /* Abort transmission */
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#define EMAC_TXCTS_SSB (1 << 3) /* Bit 3: Single Slot Backoff */
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#define EMAC_TXCTS_PTRC (1 << 4) /* Bit 4: PAUSE Timer Register Control */
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#define EMAC_TXCTS_CSLF (1 << 5) /* Bit 5: Carrier Sense Lost Flag */
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#define EMAC_TXCTS_TXACT (1 << 7) /* Bit 7: Transmitter Active Status */
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/* Ethertype Control (8-bit) */
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#define EMAC_ETCTL_
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#define EMAC_ETCTL_FIEEE (1 << 0) /* Bit 0: IEEE802.3 Length Field Ethertype */
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#define EMAC_ETCTL_FIPV4 (1 << 1) /* Bit 1: Internet Protocol Version 4 (IPv4) Ethertype */
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#define EMAC_ETCTL_FARP (1 << 2) /* Bit 2: Address Resolution Protocol (ARP) Ethertype */
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#define EMAC_ETCTL_FIPV6 (1 << 3) /* Bit 3: Internet Protocol Version 6 (IPv6) Ethertype */
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#define EMAC_ETCTL_FEMW (1 << 4) /* Bit 4: Emware Ethertype */
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#define EMAC_ETCTL_FPET (1 << 7) /* Bit 7: Programmable Ethertype */
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/* Programmable Ethertype (16-bit) -- 16-bit Ethernet type data */
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/* PAUSE Timer Value and Counter (16-bit) -- 16-bit PAUSER timer value */
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/* Interrupt Event (16-bit) */
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#define EMAC_IEVENT_
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/* Interrupt Mask (16-bit) */
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#define EMAC_IMASK_
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#define EMAC_INT_TXCI (1 << 1) /* Bit 1: Frame Transmission Complete Interrupt */
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#define EMAC_INT_ECI (1 << 4) /* Bit 4: Excessive Collision Interrupt */
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#define EMAC_INT_LCI (1 << 5) /* Bit 5: Late Collision Interrupt */
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#define EMAC_INT_MMCI (1 << 7) /* Bit 7: MII Management Transfer Complete Interrupt */
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#define EMAC_INT_RXBCI (1 << 8) /* Bit 8: Valid Frame Reception to Receive Buffer B Complete Interrupt */
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#define EMAC_INT_RXACI (1 << 9) /* Bit 9: Valid Frame Reception to Receive Buffer A Complete Interrupt */
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#define EMAC_INT_RXBOI (1 << 10) /* Bit 10: Receive Buffer B Overrun Interrupt */
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#define EMAC_INT_RXAOI (1 << 11) /* Bit 11: Receive Buffer A Overrun Interrupt */
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#define EMAC_INT_RXEI (1 << 12) /* Bit 12: Receive Error Interrupt */
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#define EMAC_INT_BREI (1 << 13) /* Bit 13: Babbling Receive Error Interrupt */
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#define EMAC_INT_RFCI (1 << 15) /* Bit 15: Receive Flow Control Interrupt */
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/* Software Reset (8-bit) */
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#define EMAC_SWRST_MACRST (1<< 7) /* Bit 7: EMAC is reset */
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#define EMAC_SWRST_MACRST (1 << 7) /* Bit 7: EMAC is reset */
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/* MII Management PHY Address (8-bit) */
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@ -144,10 +178,28 @@
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/* MII Management Read Data (16-bit) -- 16-bit read data */
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/* MII Management Command and Status (8-bit) */
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#define EMAC_MCMST_
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#define EMAC_MCMST_MDCSEL_SHIFT (0) /* Bits 0-3: Management Clock Rate Sel */
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#define EMAC_MCMST_MDCSEL_MASK (15) /* MDC frequency = Bus clock frequency / (2 * MDCSEL) */
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#define EMAC_MCMST_NOPRE (1 << 4) /* Bit 4: No Preamble */
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#define EMAC_MCMST_BUSY (1 << 5) /* Bit 5: Operation in Progress */
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#define EMAC_MCMST_OP_SHIFT (6) /* Bits 6-7: Operation Code */
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#define EMAC_MCMST_OP_MASK (3 << EMAC_MCMST_OP_SHIFT)
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# define EMAC_MCMST_OP_IGNORE (0 << EMAC_MCMST_OP_SHIFT)
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# define EMAC_MCMST_OP_WRITE (1 << EMAC_MCMST_OP_SHIFT)
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# define EMAC_MCMST_OP_READ (2 << EMAC_MCMST_OP_SHIFT)
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/* Ethernet Buffer Configuration (16-bit) */
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#define EMAC_BUFCFG_
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#define EMAC_BUFCFG_MAXFL_SHIFT (0) /* Bits 0-10 Receive Maximum Frame Length */
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#define EMAC_BUFCFG_MAXFL_MASK (0x07ff)
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#define EMAC_BUFCFG_BUFMAP_SHIFT (12) /* Bits 12-14: Buffer Size and Starting Address Mapping */
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#define EMAC_BUFCFG_BUFMAP_SHIFT (7 << EMAC_BUFCFG_BUFMAP_SHIFT)
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# define EMAC_BUFCFG_BUFMAP_128 (0 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 128 bytes */
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# define EMAC_BUFCFG_BUFMAP_256 (1 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 256 bytes */
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# define EMAC_BUFCFG_BUFMAP_512 (2 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 512 bytes */
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# define EMAC_BUFCFG_BUFMAP_1024 (3 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 1Kb */
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# define EMAC_BUFCFG_BUFMAP_1536 (4 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 1.5Kb */
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/* Receive A End-of-Frame Pointer (16-bit) */
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@ -171,7 +223,15 @@
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/* MAC Unicast AAddress 0-15 (16-bit) -- 16-bits of address */
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/* Miscellaneous (16-bit) */
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#define EMAC_EMISC_
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#define EMAC_EMISC_SHIFT (0) /* Bits 0-10: Misc data */
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#define EMAC_EMISC_MASK (0x07ff)
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#define EMAC_EMISC_INDEX_SHIFT (13) /* Bits 13-15: Miscellaneous Index */
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#define EMAC_EMISC_INDEX_MASK (7 << EMAC_EMISC_INDEX_SHIFT)
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# define EMAC_EMISC_INDEX_TXBYT (3 << EMAC_EMISC_INDEX_SHIFT) /* Transmit Frame Byte Counter */
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# define EMAC_EMISC_INDEX_BSLOT (4 << EMAC_EMISC_INDEX_SHIFT) /* Backoff Slot Time Counter */
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# define EMAC_EMISC_INDEX_RETX (5 << EMAC_EMISC_INDEX_SHIFT) /* Retransmission Counter */
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# define EMAC_EMISC_INDEX_RANDOM (6 << EMAC_EMISC_INDEX_SHIFT) /* Backoff Random Number */
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/************************************************************************************
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* Public Types
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_phyv2.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -62,13 +62,25 @@
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/* Register Bit-Field Definitions ***************************************************/
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/* Ethernet Physical Transceiver Control Register 0 */
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#define PHY_EPHYCTL0_
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#define PHY_EPHYCTL0_EPHYIEN (1 << 0) /* Bit 0: EPHY Interrupt Enable */
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#define PHY_EPHYCTL0_EPHYWAI (1 << 2) /* Bit 2: EPHY Module Stops While in Wait */
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#define PHY_EPHYCTL0_LEDEN (1 << 3) /* Bit 3: LED Drive Enable */
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#define PHY_EPHYCTL0_DIS10 (1 << 4) /* Bit 4: Disable 10BASE-T PLL */
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#define PHY_EPHYCTL0_DIS100 (1 << 5) /* Bit 5: Disable 100 BASE-TX PLL */
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#define PHY_EPHYCTL0_ANDIS (1 << 6) /* Bit 6: Auto Negotiation Disable */
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#define PHY_EPHYCTL0_EPHYEN (1 << 7) /* Bit 7: EPHY Enable */
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/* Ethernet Physical Transceiver Control Register 1 */
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#define PHY_EPHYCTL1_
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#define PHY_EPHYCTL1_PHYADD_SHIFT (0) /* Bits 0-4: EPHY Address for MII Requests */
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#define PHY_EPHYCTL1_PHYADD_MASK (0x1f)
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/* Ethernet Physical Transceiver Status Register */
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#define PHY_EPHYSR_
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#define PHY_EPHYSR_EPHYI (1 << 0) /* Bit 0: EPHY Interrupt Flag */
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#define PHY_EPHYSR_10DIS (1 << 4) /* Bit 4: EPHY Port 10BASE-T mode status */
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#define PHY_EPHYSR_100DIS (1 << 5) /* Bit 5: EPHY Port 100BASE-TX mode status */
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/************************************************************************************
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* Public Types
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