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@ -0,0 +1,852 @@
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/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx-spi.c
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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#include <nuttx/spi.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "pic32mx-internal.h"
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#include "pic32mx-spi.h"
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#if defined(CONFIG_PIC32MX_SPI1) || defined(CONFIG_PIC32MX_SPI2) || \
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defined(CONFIG_PIC32MX_SPI3) || defined(CONFIG_PIC32MX_SPI4)
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Enables non-standard debug output from this file */
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#ifndef CONFIG_DEBUG
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# undef CONFIG_DEBUG_SPI
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#endif
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#ifdef CONFIG_DEBUG_SPI
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# define spidbg lldbg
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# ifdef CONFIG_DEBUG_VERBOSE
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# define spivdbg lldbg
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# else
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# define spivdbg(x...)
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# endif
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#else
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# undef CONFIG_DEBUG_VERBOSE
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# define spidbg(x...)
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# define spivdbg(x...)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure descibes the state of the SSP driver */
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struct pic32mx_dev_s
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{
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struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
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uint32_t base; /* SPI register base address */
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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uint8_t vector; /* Interrupt vector number(for attaching) */
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uint8_t eirq; /* SPI fault interrupt number */
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uint8_t rxirq; /* SPI receive done interrupt number */
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uint8_t txirq; /* SPI transfer done interrupt number */
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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sem_t exclsem; /* Held while chip is selected for mutual exclusion */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint8_t nbits; /* Width of word in bits (8 to 16) */
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uint8_t mode; /* Mode 0,1,2,3 */
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#endif
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Low-level register access */
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static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv,
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unsigned int offset);
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static void spi_putreg(FAR struct pic32mx_dev_s *priv,
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unsigned int offset, uint32_t value);
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/* SPI methods */
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#ifndef CONFIG_SPI_OWNBUS
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static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
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#endif
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static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
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static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
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static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
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static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
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static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
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static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_PIC32MX_SPI1
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static const struct spi_ops_s g_spi1ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = spi_lock,
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#endif
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.select = pic32mx_spi1select,
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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.status = pic32mx_spi1status,
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#ifdef CONFIG_SPI_CMDDATA
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.cmddata = pic32mx_spi1cmddata,
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#endif
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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#ifdef CONFIG_SPI_CALLBACK
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.registercallback = pic32mx_spi1register, /* Provided externally */
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#else
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.registercallback = 0, /* Not implemented */
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#endif
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};
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static struct pic32mx_dev_s g_spi1dev =
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{
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.spidev = { &g_spi1ops },
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.base = PIC32MX_SPI1_K1BASE,
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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.vector = PIC32MX_IRQ_SPI1,
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.eirq = PIC32MX_IRQSRC_SPI1E,
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.rxirq = PIC32MX_IRQSRC_SPI1RX,
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.txirq = PIC32MX_IRQSRC_SPI1TX,
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#endif
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};
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#endif
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#ifdef CONFIG_PIC32MX_SPI2
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static const struct spi_ops_s g_spi2ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = spi_lock,
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#endif
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.select = pic32mx_spi2select,
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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.status = pic32mx_spi2status,
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#ifdef CONFIG_SPI_CMDDATA
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.cmddata = pic32mx_spi2cmddata,
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#endif
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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#ifdef CONFIG_SPI_CALLBACK
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.registercallback = pic32mx_spi2register, /* Provided externally */
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#else
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.registercallback = 0, /* Not implemented */
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#endif
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};
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static struct pic32mx_dev_s g_spi2dev =
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{
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.spidev = { &g_spi2ops },
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.base = PIC32MX_SPI2_K1BASE,
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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.vector = PIC32MX_IRQ_SPI2,
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.eirq = PIC32MX_IRQSRC_SPI2E,
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.rxirq = PIC32MX_IRQSRC_SPI2RX,
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.txirq = PIC32MX_IRQSRC_SPI2TX,
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#endif
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};
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#endif
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#ifdef CONFIG_PIC32MX_SPI3
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static const struct spi_ops_s g_spi3ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = spi_lock,
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#endif
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.select = pic32mx_spi3select,
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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.status = pic32mx_spi3status,
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#ifdef CONFIG_SPI_CMDDATA
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.cmddata = pic32mx_spi3cmddata,
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#endif
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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#ifdef CONFIG_SPI_CALLBACK
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.registercallback = pic32mx_spi3register, /* Provided externally */
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#else
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.registercallback = 0, /* Not implemented */
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#endif
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};
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static struct pic32mx_dev_s g_spi3dev =
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{
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.spidev = { &g_spi3ops },
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.base = PIC32MX_SPI3_K1BASE,
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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.vector = PIC32MX_IRQ_SPI4,
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.eirq = PIC32MX_IRQSRC_SPI3E,
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.rxirq = PIC32MX_IRQSRC_SPI3RX,
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.txirq = PIC32MX_IRQSRC_SPI3TX,
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#endif
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};
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#endif
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#ifdef CONFIG_PIC32MX_SPI4
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static const struct spi_ops_s g_spi4ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = spi_lock,
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#endif
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.select = pic32mx_spi4select,
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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.status = pic32mx_spi4status,
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#ifdef CONFIG_SPI_CMDDATA
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.cmddata = pic32mx_spi4cmddata,
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#endif
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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#ifdef CONFIG_SPI_CALLBACK
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.registercallback = pic32mx_spi4register, /* Provided externally */
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#else
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.registercallback = 0, /* Not implemented */
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#endif
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};
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static struct pic32mx_dev_s g_spi4dev =
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{
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.spidev = { &g_spi4ops },
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.base = PIC32MX_SPI4_K1BASE,
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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.vector = PIC32MX_IRQ_SPI4,
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.eirq = PIC32MX_IRQSRC_SPI4E,
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.rxirq = PIC32MX_IRQSRC_SPI4RX,
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.txirq = PIC32MX_IRQSRC_SPI4TX,
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#endif
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};
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: spi_getreg
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*
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* Description:
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* Return the contents of one, 32-bit SPI register
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*
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* Input Parameters:
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* priv - A pointer to a PIC32MX SPI state structure
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* offset - Offset from the SPI base address to the register of interest
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*
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* Returned Value:
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* The current contents of the register
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*
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****************************************************************************/
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static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
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{
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return getreg32(priv->base + offset);
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}
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/****************************************************************************
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* Name: spi_getreg
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*
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* Description:
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* Write a value to one, 32-bit SPI register
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*
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* Input Parameters:
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* priv - A pointer to a PIC32MX SPI state structure
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* offset - Offset from the SPI base address to the register of interest
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* value - The value to write to the SPI register
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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|
static void spi_putreg(FAR struct pic32mx_dev_s *priv, unsigned int offset,
|
|
|
|
|
uint32_t value)
|
|
|
|
|
{
|
|
|
|
|
putreg32(value, priv->base + offset);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Name: spi_lock
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* On SPI busses where there are multiple devices, it will be necessary to
|
|
|
|
|
* lock SPI to have exclusive access to the busses for a sequence of
|
|
|
|
|
* transfers. The bus should be locked before the chip is selected. After
|
|
|
|
|
* locking the SPI bus, the caller should then also call the setfrequency,
|
|
|
|
|
* setbits, and setmode methods to make sure that the SPI is properly
|
|
|
|
|
* configured for the device. If the SPI buss is being shared, then it
|
|
|
|
|
* may have been left in an incompatible state.
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* lock - true: Lock spi bus, false: unlock SPI bus
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* None
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
|
|
|
|
|
{
|
|
|
|
|
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
|
|
|
|
|
|
|
|
|
|
if (lock)
|
|
|
|
|
{
|
|
|
|
|
/* Take the semaphore (perhaps waiting) */
|
|
|
|
|
|
|
|
|
|
while (sem_wait(&priv->exclsem) != 0)
|
|
|
|
|
{
|
|
|
|
|
/* The only case that an error should occur here is if the wait was awakened
|
|
|
|
|
* by a signal.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
ASSERT(errno == EINTR);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
(void)sem_post(&priv->exclsem);
|
|
|
|
|
}
|
|
|
|
|
return OK;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Name: spi_setfrequency
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* Set the SPI frequency.
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* frequency - The SPI frequency requested
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* Returns the actual frequency selected
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
|
|
|
|
|
{
|
|
|
|
|
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
|
|
|
|
|
uint32_t divisor;
|
|
|
|
|
uint32_t actual;
|
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
|
|
/* Check if the requested frequency is the same as the frequency selection */
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
if (priv->frequency == frequency)
|
|
|
|
|
{
|
|
|
|
|
/* We are already at this frequency. Return the actual. */
|
|
|
|
|
|
|
|
|
|
return priv->actual;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Calculate the divisor
|
|
|
|
|
*
|
|
|
|
|
* frequency = BOARD_PBCLOCK / (2 * divisor), or
|
|
|
|
|
* divisor = (BOARD_PBCLOCK / 2) / frequency
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
divisor = (BOARD_PBCLOCK / 2) / frequency;
|
|
|
|
|
|
|
|
|
|
/* The a BRG register value is that divisor minus one
|
|
|
|
|
*
|
|
|
|
|
* frequency = BOARD_PBCLOCK /(2 * (BRG + 1)), or
|
|
|
|
|
* BRG = (BOARD_PBCLOCK / 2) / frequency - 1
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
regval = divisor;
|
|
|
|
|
if (regval > 0)
|
|
|
|
|
{
|
|
|
|
|
regval--;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Save the new BRG value */
|
|
|
|
|
|
|
|
|
|
spi_putreg(priv, PIC32MX_SPI_BRG_OFFSET, regval);
|
|
|
|
|
|
|
|
|
|
/* Calculate the new actual frequency"
|
|
|
|
|
*
|
|
|
|
|
* frequency = BOARD_PBCLOCK / (2 * divisor)
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
actual = (BOARD_PBCLOCK / 2) / divisor;
|
|
|
|
|
|
|
|
|
|
/* Save the frequency setting */
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
priv->frequency = frequency;
|
|
|
|
|
priv->actual = actual;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
spidbg("Frequency %d->%d\n", frequency, actual);
|
|
|
|
|
return actual;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Name: spi_setmode
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* Set the SPI mode. Optional. See enum spi_mode_e for mode definitions
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* mode - The SPI mode requested
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* none
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
|
|
|
|
{
|
|
|
|
|
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
|
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
|
|
/* Has the mode changed? */
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
if (mode != priv->mode)
|
|
|
|
|
{
|
|
|
|
|
#endif
|
|
|
|
|
/* Yes... Set CR appropriately */
|
|
|
|
|
|
|
|
|
|
regval = spi_getreg(priv, PIC32MX_SPI_CON_OFFSET);
|
|
|
|
|
regval &= ~(SPI_CON_CKP|SPI_CON_SMP);
|
|
|
|
|
|
|
|
|
|
switch (mode)
|
|
|
|
|
{
|
|
|
|
|
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
|
|
|
|
|
regval |= SPI_CON_SMP;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
|
|
|
|
|
regval |= SPI_CON_CKP;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
|
|
|
|
|
regval |= (SPI_CON_CKP|SPI_CON_SMP);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
DEBUGASSERT(FALSE);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spi_putreg(priv, PIC32MX_SPI_CON_OFFSET, regval);
|
|
|
|
|
|
|
|
|
|
/* Save the mode so that subsequent re-configuratins will be faster */
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
priv->mode = mode;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Name: spi_setbits
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* Set the number if bits per word.
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* nbits - The number of bits requests
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* none
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
|
|
|
|
|
{
|
|
|
|
|
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
|
|
|
|
|
uint32_t mode;
|
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
|
|
/* Has the number of bits changed? */
|
|
|
|
|
|
|
|
|
|
DEBUGASSERT(priv && nbits > 7 && nbits < 17);
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
if (nbits != priv->nbits)
|
|
|
|
|
{
|
|
|
|
|
#endif
|
|
|
|
|
/* Yes... Set the CON register appropriately */
|
|
|
|
|
|
|
|
|
|
if (nbits == 8)
|
|
|
|
|
{
|
|
|
|
|
mode = SPI_CON_MODE_8BIT;
|
|
|
|
|
}
|
|
|
|
|
else if (nbits == 16)
|
|
|
|
|
{
|
|
|
|
|
mode = SPI_CON_MODE_8BIT;
|
|
|
|
|
}
|
|
|
|
|
else if (nbits == 32)
|
|
|
|
|
{
|
|
|
|
|
mode = SPI_CON_MODE_8BIT;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
spidbg("Unsupported nbits: %d\n", nbits);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
regval = spi_getreg(priv, PIC32MX_SPI_CON_OFFSET);
|
|
|
|
|
regval &= ~SPI_CON_MODE_MASK;
|
|
|
|
|
regval |= mode;
|
|
|
|
|
regval = spi_getreg(priv, PIC32MX_SPI_CON_OFFSET);
|
|
|
|
|
|
|
|
|
|
/* Save the selection so the subsequence re-configurations will be faster */
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
|
priv->nbits = nbits;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Name: spi_send
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* Exchange one word on SPI
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* wd - The word to send. the size of the data is determined by the
|
|
|
|
|
* number of bits selected for the SPI interface.
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* response
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
|
|
|
|
|
{
|
|
|
|
|
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
|
|
|
|
|
|
|
|
|
|
/* Write the data to transmitted to the SPI Data Register */
|
|
|
|
|
|
|
|
|
|
spi_putreg(priv, PIC32MX_SPI_BUF_OFFSET, (uint32_t)wd);
|
|
|
|
|
|
|
|
|
|
/* Wait for the SPITBE bit in the SPI Status Register to be set to 1. The
|
|
|
|
|
* SPITBE bit will be set when the receive buffer is not empty.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPITBE) == 0);
|
|
|
|
|
|
|
|
|
|
/* Return the SPI data */
|
|
|
|
|
|
|
|
|
|
return (uint16_t)spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*************************************************************************
|
|
|
|
|
* Name: spi_sndblock
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* Send a block of data on SPI
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* buffer - A pointer to the buffer of data to be sent
|
|
|
|
|
* nwords - the length of data to send from the buffer in number of words.
|
|
|
|
|
* The wordsize is determined by the number of bits-per-word
|
|
|
|
|
* selected for the SPI interface. If nbits <= 8, the data is
|
|
|
|
|
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* None
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
|
|
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
|
|
|
|
|
{
|
|
|
|
|
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
|
|
|
|
|
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
|
|
|
|
|
uint32_t regval;
|
|
|
|
|
uint8_t data;
|
|
|
|
|
|
|
|
|
|
spidbg("nwords: %d\n", nwords);
|
|
|
|
|
while (nwords)
|
|
|
|
|
{
|
|
|
|
|
/* Write the data to transmitted to the SPI Data Register */
|
|
|
|
|
|
|
|
|
|
data = *ptr++;
|
|
|
|
|
spi_putreg(priv, PIC32MX_SPI_BUF_OFFSET, (uint32_t)data);
|
|
|
|
|
|
|
|
|
|
/* Wait for the SPITBE bit in the SPI Status Register to be set to 1.
|
|
|
|
|
* The SPITBE bit will be set when the receive buffer is not empty.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPITBE) == 0);
|
|
|
|
|
|
|
|
|
|
/* Read from the buffer register to clear the status bit */
|
|
|
|
|
|
|
|
|
|
regval = spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
|
|
|
|
|
nwords--;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
|
* Name: spi_recvblock
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
|
|
|
|
* Revice a block of data from SPI
|
|
|
|
|
*
|
|
|
|
|
* Input Parameters:
|
|
|
|
|
* dev - Device-specific state data
|
|
|
|
|
* buffer - A pointer to the buffer in which to recieve data
|
|
|
|
|
* nwords - the length of data that can be received in the buffer in number
|
|
|
|
|
* of words. The wordsize is determined by the number of bits-per-word
|
|
|
|
|
* selected for the SPI interface. If nbits <= 8, the data is
|
|
|
|
|
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
|
|
|
|
|
*
|
|
|
|
|
* Returned Value:
|
|
|
|
|
* None
|
|
|
|
|
*
|
|
|
|
|
****************************************************************************/
|
|
|
|
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static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
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{
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FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
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FAR uint8_t *ptr = (FAR uint8_t*)buffer;
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spidbg("nwords: %d\n", nwords);
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while (nwords)
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{
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/* Write some dummy data to the SPI Data Register in order to clock the
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* read data.
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*/
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spi_putreg(priv, PIC32MX_SPI_BUF_OFFSET, 0xff);
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/* Wait for the SPITBE bit in the SPI Status Register to be set to 1.
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* The SPITBE bit will be set when the receive buffer is not empty.
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*/
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while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPITBE) == 0);
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/* Read the received data from the SPI Data Register */
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*ptr++ = (uint8_t)spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
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nwords--;
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_spiinitialize
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*
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* Description:
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* Initialize the selected SPI port
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*
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* Input Parameter:
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* Port number (for hardware that has mutiple SPI interfaces)
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*
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* Returned Value:
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* Valid SPI device structure reference on succcess; a NULL on failure
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*
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****************************************************************************/
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FAR struct spi_dev_s *up_spiinitialize(int port)
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{
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FAR struct pic32mx_dev_s *priv;
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irqstate_t flags;
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uint32_t regval;
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/* Select the SPI state structure for this port */
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#ifdef CONFIG_PIC32MX_SPI1
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if (port == 1)
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{
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priv = &g_spi1dev;
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}
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else
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#endif
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#ifdef CONFIG_PIC32MX_SPI2
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if (port == 2)
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{
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priv = &g_spi2dev;
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}
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else
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#endif
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#ifdef CONFIG_PIC32MX_SPI3
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if (port == 3)
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{
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priv = &g_spi3dev;
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}
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else
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#endif
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#ifdef CONFIG_PIC32MX_SPI4
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if (port == 4)
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{
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priv = &g_spi4dev;
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}
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else
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#endif
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{
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spidbg("Unsuppport port: %d\n", port);
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return NULL;
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}
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/* Disable SPI interrupts */
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flags = irqsave();
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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up_disable_irq(priv->eirq);
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up_disable_irq(priv->txirq);
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up_disable_irq(priv->rxirq);
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#endif
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/* Stop and reset the SPI module by clearing the ON bit in the CON register. */
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spi_putreg(priv, PIC32MX_SPI_CON_OFFSET, 0);
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/* Clear the receive buffer by reading from the BUF register */
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regval = spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
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/* Set the ENHBUF bit if using Enhanced Buffer mode. */
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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/* Attach the interrupt vector */
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ret = irq_attach(priv->vector, spi_interrupt);
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if (ret < 0)
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{
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spidbg("Failed to attach vector: %d port: %d\n", priv->vector, port);
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goto errout;
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}
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/* Enable SPI interrupts */
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up_enable_irq(priv->eirq);
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up_enable_irq(priv->txirq);
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up_enable_irq(priv->rxirq);
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/* Set the interrupt priority */
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ret = up_prioritize_irq(priv->vector, CONFIG_PIC32MX_SPI_PRIORITY)
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if (ret < 0)
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{
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spidbg("up_prioritize_irq failed: %d\n", ret);
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goto errout;
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}
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#endif
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/* Select a default frequency of approx. 400KHz */
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spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
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/* Clear the SPIROV overflow bit (SPIxSTAT:6). */
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spi_putreg(priv, PIC32MX_SPI_STATCLR_OFFSET, SPI_STAT_SPIROV);
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/* Initial settings 8 bit + master mode + mode 0*/
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regval = (SPI_CON_MSTEN | SPI_CON_MODE_8BIT | SPI_CON_ON);
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#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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regval |= (SPI_CON_RTXISEL_HALF | SPI_CON_STXISEL_HALF);
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#endif
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spi_putreg(priv, PIC32MX_SPI_CON_OFFSET, regval);
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/* Set the initial SPI configuration */
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#ifndef CONFIG_SPI_OWNBUS
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priv->nbits = 8;
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priv->mode = SPIDEV_MODE0;
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#endif
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/* Initialize the SPI semaphore that enforces mutually exclusive access */
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#ifndef CONFIG_SPI_OWNBUS
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sem_init(&priv->exclsem, 0, 1);
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|
#endif
|
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|
|
irqrestore(flags);
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|
return &priv->spidev;
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|
|
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
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|
errout:
|
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|
|
irqrestore(flags);
|
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|
|
return NULL;
|
|
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|
|
#endif
|
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|
|
}
|
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|
#endif /* CONFIG_PIC32MX_SPI */
|
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patacongo