Add z180 interrupt initialization logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5433 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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0cfc4cf403
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1d7cb63254
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@ -111,14 +111,10 @@
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*
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* Normal vector interrupts use a vector table with 16 entries (2 bytes
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* per entry). Each entry holds the address of the interrupt handler.
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*
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* The vector table address is determined by 11-bits from the I and IL
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* registers. The vector table must be aligned on 32-byte address
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* boundaries.
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* - Traps vector to logic address 0x0000 which may or may not be the same
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* as the RST 0.
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* - INT0
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/* Interrupt vectors (offsets) for Z180 internal interrupts */
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*/
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#define Z180_INT1 (9) /* Vector offset 0: External /INT1 */
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#define Z180_INT2 (10) /* Vector offset 2: External /INT2 */
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@ -38,10 +38,16 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "chip/switch.h"
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#include <arch/io.h>
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#include "switch.h"
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#include "z180_iomap.h"
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#include "up_internal.h"
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/****************************************************************************
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@ -66,6 +72,12 @@ volatile chipreg_t *current_regs;
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uint8_t current_cbr;
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/* The interrupt vector table is exported by z180_vectors.asm or
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* z180_romvectors.asm with the name up_vectors:
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*/
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extern uintptr_t up_vectors[16];
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -74,6 +86,22 @@ uint8_t current_cbr;
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: z180_seti
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*
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* Description:
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* Input byte from port p
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*
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****************************************************************************/
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static void z180_seti(uint8_t value) __naked
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{
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__asm
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ld a, 4(ix) ;value
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ld l, a
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__endasm;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -119,3 +147,37 @@ statedisable:
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ret ; and return
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__endasm;
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}
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/****************************************************************************
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* Name: up_irqinitialize
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*
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* Description:
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* Initialize and enable interrupts
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*
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****************************************************************************/
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void up_irqinitialize(void)
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{
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uint16_t vectaddr = (uint16_t)up_vectors;
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uint8_t regval;
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/* Initialize the I and IL registers so that the interrupt vector table
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* is used.
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*/
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regval = (uint8_t)(vectaddr >> 8);
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z180_seti(regval);
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regval = (uint8_t)(vectaddr & IL_MASK);
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outp(Z180_INT_IL, regval);
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/* Disable external interrupts */
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outp(Z180_INT_ITC, 0);
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/* And finally, enable interrupts (including the timer) */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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irqrestore(Z180_C_FLAG);
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#endif
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}
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@ -54,12 +54,6 @@
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.globl _up_asci0 ; Vector offset 14: Async channel 0
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.globl _up_asci1 ; Vector offset 16: Async channel 1
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.globl _up_unused ; Vector offset 18: Unused
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.globl _up_unused ; Vector offset 20: Unused
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.globl _up_unused ; Vector offset 22: Unused
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.globl _up_unused ; Vector offset 24: Unused
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.globl _up_unused ; Vector offset 26: Unused
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.globl _up_unused ; Vector offset 28: Unused
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.globl _up_unused ; Vector offset 30: Unused
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;**************************************************************************
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; Interrupt Vector Table
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@ -71,19 +65,19 @@
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.area _VECTORS
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_up_vectors::
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.dw up_int1 ; Vector offset 0: External /INT1
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.dw up_int2 ; Vector offset 2: External /INT2
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.dw up_prt0 ; Vector offset 4: PRT channel 0
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.dw up_prt1 ; Vector offset 6: PRT channel 1
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.dw up_dma0 ; Vector offset 8: DMA channel 0
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.dw up_dma1 ; Vector offset 8: DMA channel 1
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.dw up_csio ; Vector offset 12: Clocked serial I/O
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.dw up_asci0 ; Vector offset 14: Async channel 0
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.dw up_asci1 ; Vector offset 16: Async channel 1
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.dw up_unused ; Vector offset 18: Unused
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.dw up_unused ; Vector offset 20: Unused
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.dw up_unused ; Vector offset 22: Unused
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.dw up_unused ; Vector offset 24: Unused
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.dw up_unused ; Vector offset 26: Unused
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.dw up_unused ; Vector offset 28: Unused
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.dw up_unused ; Vector offset 30: Unused
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.dw _up_int1 ; Vector offset 0: External /INT1
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.dw _up_int2 ; Vector offset 2: External /INT2
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.dw _up_prt0 ; Vector offset 4: PRT channel 0
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.dw _up_prt1 ; Vector offset 6: PRT channel 1
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.dw _up_dma0 ; Vector offset 8: DMA channel 0
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.dw _up_dma1 ; Vector offset 8: DMA channel 1
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.dw _up_csio ; Vector offset 12: Clocked serial I/O
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.dw _up_asci0 ; Vector offset 14: Async channel 0
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.dw _up_asci1 ; Vector offset 16: Async channel 1
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.dw _up_unused ; Vector offset 18: Unused
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.dw _up_unused ; Vector offset 20: Unused
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.dw _up_unused ; Vector offset 22: Unused
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.dw _up_unused ; Vector offset 24: Unused
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.dw _up_unused ; Vector offset 26: Unused
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.dw _up_unused ; Vector offset 28: Unused
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.dw _up_unused ; Vector offset 30: Unused
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@ -58,14 +58,13 @@
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.globl _up_doirq ; Interrupt decoding logic
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;**************************************************************************
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; Vector Handlers
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;**************************************************************************
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.area _CODE
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up_int1:: ; Vector offset 0: External /INT1
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_up_int1:: ; Vector offset 0: External /INT1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -73,7 +72,7 @@ up_int1:: ; Vector offset 0: External /INT1
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ld a, #9 ; 9 = Z180_INT1
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jr _up_vectcommon ; Remaining RST handling is common
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up_int2:: ; Vector offset 2: External /INT2
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_up_int2:: ; Vector offset 2: External /INT2
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -81,7 +80,7 @@ up_int2:: ; Vector offset 2: External /INT2
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ld a, #10 ; 10 = Z180_INT2
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jr _up_vectcommon ; Remaining RST handling is common
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up_prt0:: ; Vector offset 4: PRT channel 0
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_up_prt0:: ; Vector offset 4: PRT channel 0
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -89,7 +88,7 @@ up_prt0:: ; Vector offset 4: PRT channel 0
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ld a, #11 ; 11 = Z180_PRT0
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jr _up_vectcommon ; Remaining RST handling is common
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up_prt1:: ; Vector offset 6: PRT channel 1
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_up_prt1:: ; Vector offset 6: PRT channel 1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -97,7 +96,7 @@ up_prt1:: ; Vector offset 6: PRT channel 1
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ld a, #12 ; 12 = Z180_PRT1
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jr _up_vectcommon ; Remaining RST handling is common
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up_dma0:: ; Vector offset 8: DMA channel 0
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_up_dma0:: ; Vector offset 8: DMA channel 0
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -105,7 +104,7 @@ up_dma0:: ; Vector offset 8: DMA channel 0
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ld a, #13 ; 13 = Z180_DMA0
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jr _up_vectcommon ; Remaining RST handling is common
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up_dma1:: ; Vector offset 8: DMA channel 1
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_up_dma1:: ; Vector offset 8: DMA channel 1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -113,7 +112,7 @@ up_dma1:: ; Vector offset 8: DMA channel 1
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ld a, #14 ; 14 = Z180_DMA1
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jr _up_vectcommon ; Remaining RST handling is common
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up_csio:: ; Vector offset 12: Clocked serial I/O
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_up_csio:: ; Vector offset 12: Clocked serial I/O
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -121,7 +120,7 @@ up_csio:: ; Vector offset 12: Clocked serial I/O
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ld a, #15 ; 15 = Z180_CSIO
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jr _up_vectcommon ; Remaining RST handling is common
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up_asci0:: ; Vector offset 14: Async channel 0
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_up_asci0:: ; Vector offset 14: Async channel 0
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -129,7 +128,7 @@ up_asci0:: ; Vector offset 14: Async channel 0
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ld a, #16 ; 16 = Z180_ASCI0
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jr _up_vectcommon ; Remaining RST handling is common
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up_asci1:: ; Vector offset 16: Async channel 1
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_up_asci1:: ; Vector offset 16: Async channel 1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -137,7 +136,7 @@ up_asci1:: ; Vector offset 16: Async channel 1
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ld a, #17 ; 17 = Z180_ASCI1
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jr _up_vectcommon ; Remaining RST handling is common
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up_unused:: ; Vector offset 18: Unused
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_up_unused:: ; Vector offset 18: Unused
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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@ -54,12 +54,6 @@
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.globl _up_asci0 ; Vector offset 14: Async channel 0
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.globl _up_asci1 ; Vector offset 16: Async channel 1
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.globl _up_unused ; Vector offset 18: Unused
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.globl _up_unused ; Vector offset 20: Unused
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.globl _up_unused ; Vector offset 22: Unused
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.globl _up_unused ; Vector offset 24: Unused
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.globl _up_unused ; Vector offset 26: Unused
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.globl _up_unused ; Vector offset 28: Unused
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.globl _up_unused ; Vector offset 30: Unused
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;**************************************************************************
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; Interrupt Vector Table
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@ -72,19 +66,19 @@
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.org 0x0040
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_up_vectors::
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.dw up_int1 ; Vector offset 0: External /INT1
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.dw up_int2 ; Vector offset 2: External /INT2
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.dw up_prt0 ; Vector offset 4: PRT channel 0
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.dw up_prt1 ; Vector offset 6: PRT channel 1
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.dw up_dma0 ; Vector offset 8: DMA channel 0
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.dw up_dma1 ; Vector offset 8: DMA channel 1
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.dw up_csio ; Vector offset 12: Clocked serial I/O
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.dw up_asci0 ; Vector offset 14: Async channel 0
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.dw up_asci1 ; Vector offset 16: Async channel 1
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.dw up_unused ; Vector offset 18: Unused
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.dw up_unused ; Vector offset 20: Unused
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.dw up_unused ; Vector offset 22: Unused
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.dw up_unused ; Vector offset 24: Unused
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.dw up_unused ; Vector offset 26: Unused
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.dw up_unused ; Vector offset 28: Unused
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.dw up_unused ; Vector offset 30: Unused
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.dw _up_int1 ; Vector offset 0: External /INT1
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.dw _up_int2 ; Vector offset 2: External /INT2
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.dw _up_prt0 ; Vector offset 4: PRT channel 0
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.dw _up_prt1 ; Vector offset 6: PRT channel 1
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.dw _up_dma0 ; Vector offset 8: DMA channel 0
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.dw _up_dma1 ; Vector offset 8: DMA channel 1
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.dw _up_csio ; Vector offset 12: Clocked serial I/O
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.dw _up_asci0 ; Vector offset 14: Async channel 0
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.dw _up_asci1 ; Vector offset 16: Async channel 1
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.dw _up_unused ; Vector offset 18: Unused
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.dw _up_unused ; Vector offset 20: Unused
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.dw _up_unused ; Vector offset 22: Unused
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.dw _up_unused ; Vector offset 24: Unused
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.dw _up_unused ; Vector offset 26: Unused
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.dw _up_unused ; Vector offset 28: Unused
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.dw _up_unused ; Vector offset 30: Unused
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