Cortex-M7: Add cache operations
This commit is contained in:
Gregory Nutt
parent
f81c68fe11
commit
1d476abe05
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@ -5,6 +5,24 @@
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comment "ARMV7M Configuration Options"
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config ARMV7M_HAVE_ICACHE
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bool
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default n
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config ARMV7M_HAVE_DCACHE
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bool
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default n
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config ARMV7M_ICACHE
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bool "Use I-Cache"
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default n
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depends on ARMV7M_HAVE_ICACHE
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config ARMV7M_DCACHE
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bool "Use D-Cache"
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default n
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depends on ARMV7M_HAVE_DCACHE
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choice
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prompt "Toolchain Selection"
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default ARMV7M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
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@ -1,9 +1,14 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/armv7-m/cache.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Some logic in this header file derives from the ARM CMSIS core_cm7.h
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* header file which has a compatible 3-clause BSD license:
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*
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* Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -14,7 +19,7 @@
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* 3. Neither the name ARM, NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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@ -31,27 +36,228 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_M_CACHE_H
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#define __ARCH_ARM_SRC_ARMV7_M_CACHE_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#include "up_arch.h"
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#include "nvic.h"
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Cache Size ID (CCSIDR) register macros used by inline function s*/
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#define CCSIDR_WAYS(n) \
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(((n) & NVIC_CCSIDR_ASSOCIATIVITY_MASK) >> NVIC_CCSIDR_ASSOCIATIVITY_SHIFT)
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#define CCSIDR_SETS(n) \
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(((n) & NVIC_CCSIDR_NUMSETS_MASK) >> NVIC_CCSIDR_NUMSETS_SHIFT)
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#define CCSIDR_LSSHIFT(n) \
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(((n) & NVIC_CCSIDR_LINESIZE_MASK) >> NVIC_CCSIDR_LINESIZE_SHIFT)
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/* intrinsics are used in these inline functions */
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#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
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#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
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#define ARM_DSB() arm_dsb(15)
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#define ARM_ISB() arm_isb(15)
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/****************************************************************************
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* Inline Functions
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************************************************************************************/
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Name: arm_clz
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*
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* Description:
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* Access to CLZ instructions
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*
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* Input Parameters:
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* value - The value to perform the CLZ operation on
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline uint32_t arm_clz(unsigned int value)
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{
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uint32_t ret;
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__asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(value));
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return ret;
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}
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/****************************************************************************
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* Name: arch_enable_icache
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*
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* Description:
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* Enable the I-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void arch_enable_icache(void)
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{
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#ifdef CONFIG_ARMV7M_ICACHE
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uint32_t regval;
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ARM_DSB();
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ARM_ISB();
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/* Invalidate the entire I-Cache */
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putreg32(0, NVIC_ICIALLU);
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/* Enable the I-Cache */
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regval = getreg32(NVIC_CFGCON);
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regval |= NVIC_CFGCON_IC;
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putreg32(regval, NVIC_CFGCON);
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ARM_DSB();
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ARM_ISB();
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#endif
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}
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/****************************************************************************
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* Name: arch_disable_icache
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*
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* Description:
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* Disable the I-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void arch_disable_icache(void)
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{
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#ifdef CONFIG_ARMV7M_ICACHE
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uint32_t regval;
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ARM_DSB();
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ARM_ISB();
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/* Disable the I-Cache */
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regval = getreg32(NVIC_CFGCON);
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regval &= ~NVIC_CFGCON_IC;
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putreg32(regval, NVIC_CFGCON);
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/* Invalidate the entire I-Cache */
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putreg32(0, NVIC_ICIALLU);
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ARM_DSB();
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ARM_ISB();
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#endif
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}
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/****************************************************************************
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* Name: arch_invalidate_icache_all
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*
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* Description:
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* Invalidate the entire contents of I cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void arch_invalidate_icache_all(void)
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{
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#ifdef CONFIG_ARMV7M_ICACHE
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ARM_DSB();
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ARM_ISB();
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/* Invalidate the entire I-Cache */
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putreg32(0, NVIC_ICIALLU);
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ARM_DSB();
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ARM_ISB();
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#endif
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}
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: arch_enable_dcache
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*
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* Description:
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* Enable the D-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_enable_dcache(void);
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#else
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# define arch_enable_dcache()
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#endif
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/****************************************************************************
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* Name: arch_disable_dcache
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*
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* Description:
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* Disable the D-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_disable_dcache(void);
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#else
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# define arch_disable_dcache()
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#endif
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/****************************************************************************
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* Name: arch_invalidate_dcache
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*
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@ -74,10 +280,13 @@
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*
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****************************************************************************/
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static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end)
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{
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#warning Missing logic
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}
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#if 0 /* Not implemented */
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_invalidate_dcache(uintptr_t start, uintptr_t end);
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#else
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# define arch_invalidate_dcache(s,e)
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#endif
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#endif
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/****************************************************************************
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* Name: arch_invalidate_dcache_all
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* Description:
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* Invalidate the entire contents of D cache.
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*
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* NOTE: This function forces L1 and L2 cache operations to be atomic
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* by disabling interrupts.
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*
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* Input Parameters:
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* None
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*
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*
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****************************************************************************/
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static inline void arch_invalidate_dcache_all(void)
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{
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#warning Missing logic
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}
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_invalidate_dcache_all(void);
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#else
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# define arch_invalidate_dcache_all()
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#endif
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/****************************************************************************
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* Name: arch_clean_dcache
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@ -122,10 +329,39 @@ static inline void arch_invalidate_dcache_all(void)
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*
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****************************************************************************/
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static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
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{
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#warning Missing logic
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}
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#if 0 /* Not implemented */
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_clean_dcache(uintptr_t start, uintptr_t end);
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#else
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# define arch_clean_dcache(s,e)
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#endif
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#endif
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/****************************************************************************
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* Name: arch_clean_dcache_all
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*
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* Description:
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* Clean the entire data cache within the specified region by flushing the
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* contents of the data cache to memory.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_clean_dcache_all(void);
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#else
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# define arch_clean_dcache_all()
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#endif
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/****************************************************************************
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* Name: arch_flush_dcache
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@ -148,27 +384,39 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end)
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*
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****************************************************************************/
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static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
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{
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#warning Missing logic
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}
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#if 0 /* Not implemented */
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_flush_dcache(uintptr_t start, uintptr_t end);
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#else
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#define EXTERN extern
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# define arch_flush_dcache(s,e)
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#endif
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#endif
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/****************************************************************************
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* Public Function Prototypes
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* Name: arch_flush_dcache_all
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*
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* Description:
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* Flush the entire data cache by cleaning and invalidating the D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_DCACHE
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void arch_flush_dcache_all(void);
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#else
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# define arch_flush_dcache_all()
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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@ -202,6 +202,10 @@
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#define NVIC_ISAR2_OFFSET 0x0d68 /* ISA feature register 2 */
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#define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */
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#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
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#define NVIC_CLIDR_OFFSET 0x0d78 /* Cache Level ID register (Cortex-M7) */
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#define NVIC_CTR_OFFSET 0x0d7c /* Cache Type register (Cortex-M7) */
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#define NVIC_CCSIDR_OFFSET 0x0d80 /* Cache Size ID Register (Cortex-M7) */
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#define NVIC_CSSELR_OFFSET 0x0d84 /* Cache Size Selection Register (Cortex-M7) */
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#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
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#define NVIC_DHCSR_OFFSET 0x0df0 /* Debug Halting Control and Status Register */
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#define NVIC_DCRSR_OFFSET 0x0df4 /* Debug Core Register Selector Register */
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@ -213,6 +217,16 @@
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#define NVIC_FPDSCR_OFFSET 0x0f3c /* Floating-point Default Status Control Register */
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#define NVIC_MVFR0_OFFSET 0x0f40 /* Media and VFP Feature Register 0 */
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#define NVIC_MVFR1_OFFSET 0x0f44 /* Media and VFP Feature Register 1 */
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#define NVIC_MVFR2_OFFSET 0x0f48 /* Media and VFP Feature Register 2 */
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#define NVIC_ICIALLU_OFFSET 0x0f50 /* I-Cache Invalidate All to PoU (Cortex-M7) */
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#define NVIC_ICIMVAU_OFFSET 0x0f58 /* I-Cache Invalidate by MVA to PoU (Cortex-M7) */
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#define NVIC_DCIMVAU_OFFSET 0x0f5c /* D-Cache Invalidate by MVA to PoC (Cortex-M7) */
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#define NVIC_DCISW_OFFSET 0x0f60 /* D-Cache Invalidate by Set-way (Cortex-M7) */
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#define NVIC_DCCMVAU_OFFSET 0x0f64 /* D-Cache Clean by MVA to PoU (Cortex-M7) */
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#define NVIC_DCCMVAC_OFFSET 0x0f68 /* D-Cache Clean by MVA to PoC (Cortex-M7) */
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#define NVIC_DCCSW_OFFSET 0x0f62 /* D-Cache Clean by Set-way (Cortex-M7) */
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#define NVIC_DCCIMVAC_OFFSET 0x0f70 /* D-Cache Clean and Invalidate by MVA to PoC (Cortex-M7) */
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#define NVIC_DCCISW_OFFSET 0x0f74 /* D-Cache Clean and Invalidate by Set-way (Cortex-M7) */
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#define NVIC_PID4_OFFSET 0x0fd0 /* Peripheral identification register (PID4) */
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#define NVIC_PID5_OFFSET 0x0fd4 /* Peripheral identification register (PID5) */
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#define NVIC_PID6_OFFSET 0x0fd8 /* Peripheral identification register (PID6) */
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@ -375,6 +389,10 @@
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#define NVIC_ISAR2 (ARMV7M_NVIC_BASE + NVIC_ISAR2_OFFSET)
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#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
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#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
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#define NVIC_CLIDR (ARMV7M_NVIC_BASE + NVIC_CLIDR_OFFSET)
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#define NVIC_CTR (ARMV7M_NVIC_BASE + NVIC_CTR_OFFSET)
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#define NVIC_CCSIDR (ARMV7M_NVIC_BASE + NVIC_CCSIDR_OFFSET)
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#define NVIC_CSSELR (ARMV7M_NVIC_BASE + NVIC_CSSELR_OFFSET)
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#define NVIC_CPACR (ARMV7M_NVIC_BASE + NVIC_CPACR_OFFSET)
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#define NVIC_DHCSR (ARMV7M_NVIC_BASE + NVIC_DHCSR_OFFSET)
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#define NVIC_DCRSR (ARMV7M_NVIC_BASE + NVIC_DCRSR_OFFSET)
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@ -382,6 +400,15 @@
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#define NVIC_DEMCR (ARMV7M_NVIC_BASE + NVIC_DEMCR_OFFSET)
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#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
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#define NVIC_FPCCR (ARMV7M_NVIC_BASE + NVIC_FPCCR_OFFSET)
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#define NVIC_ICIALLU (ARMV7M_NVIC_BASE + NVIC_ICIALLU_OFFSET)
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#define NVIC_ICIMVAU (ARMV7M_NVIC_BASE + NVIC_ICIMVAU_OFFSET)
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#define NVIC_DCIMVAU (ARMV7M_NVIC_BASE + NVIC_DCIMVAU_OFFSET)
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#define NVIC_DCISW (ARMV7M_NVIC_BASE + NVIC_DCISW_OFFSET)
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#define NVIC_DCCMVAU (ARMV7M_NVIC_BASE + NVIC_DCCMVAU_OFFSET)
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#define NVIC_DCCMVAC (ARMV7M_NVIC_BASE + NVIC_DCCMVAC_OFFSET)
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#define NVIC_DCCSW (ARMV7M_NVIC_BASE + NVIC_DCCSW_OFFSET)
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#define NVIC_DCCIMVAC (ARMV7M_NVIC_BASE + NVIC_DCCIMVAC_OFFSET)
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#define NVIC_DCCISW (ARMV7M_NVIC_BASE + NVIC_DCCISW_OFFSET)
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||||
#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
|
||||
#define NVIC_PID5 (ARMV7M_NVIC_BASE + NVIC_PID5_OFFSET)
|
||||
#define NVIC_PID6 (ARMV7M_NVIC_BASE + NVIC_PID6_OFFSET)
|
||||
|
|
@ -449,6 +476,19 @@
|
|||
#define NVIC_SYSCON_SEVONPEND (1 << 4) /* Bit 4: Send Event on Pending bit */
|
||||
/* Bits 5-31: Reserved */
|
||||
|
||||
/* Configuration control register (CFGCON) */
|
||||
|
||||
#define NVIC_CFGCON_NONBASETHRDENA (1 << 0) /* Bit 0: How processor enters thread mode */
|
||||
#define NVIC_CFGCON_USERSETMPEND (1 << 1) /* Bit 1: Enables unprivileged access to STIR */
|
||||
#define NVIC_CFGCON_UNALIGNTRP (1 << 3) /* Bit 3: Enables unaligned access traps */
|
||||
#define NVIC_CFGCON_DIV0TRP (1 << 4) /* Bit 4: Enables fault on divide-by-zero */
|
||||
#define NVIC_CFGCON_BFHFNMIGN (1 << 8) /* Bit 8: Disables data bus faults */
|
||||
#define NVIC_CFGCON_STKALIGN (1 << 9) /* Bit 9: Indicates stack alignment on exeption */
|
||||
/* Cortex-M7: */
|
||||
#define NVIC_CFGCON_DC (1 << 16) /* Bit 16: Data cache enable */
|
||||
#define NVIC_CFGCON_IC (1 << 17) /* Bit 17: Instruction cache enable */
|
||||
#define NVIC_CFGCON_BP (1 << 18) /* Bit 18: Branch prediction enable */
|
||||
|
||||
/* System handler 4-7 priority register */
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_PR4_SHIFT 0
|
||||
|
|
@ -520,6 +560,57 @@
|
|||
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
|
||||
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
|
||||
|
||||
/* Cache Level ID register (Cortex-M7) */
|
||||
|
||||
#define NVIC_CLIDR_L1CT_SHIFT (0) /* Bits 0-2: Level 1 cache type */
|
||||
#define NVIC_CLIDR_L1CT_MASK (7 << NVIC_CLIDR_L1CT_SHIFT)
|
||||
# define NVIC_CLIDR_L1CT_ICACHE (1 << NVIC_CLIDR_LOC_SHIFT)
|
||||
# define NVIC_CLIDR_L1CT_DCACHE (2 << NVIC_CLIDR_LOC_SHIFT)
|
||||
#define NVIC_CLIDR_LOC_SHIFT (24) /* Bits 24-26: Level of Coherency */
|
||||
#define NVIC_CLIDR_LOC_MASK (7 << NVIC_CLIDR_LOC_SHIFT)
|
||||
# define NVIC_CLIDR_LOC_IMPLEMENTED (1 << NVIC_CLIDR_LOC_SHIFT)
|
||||
# define NVIC_CLIDR_LOC_UNIMPLEMENTED (0 << NVIC_CLIDR_LOC_SHIFT)
|
||||
#define NVIC_CLIDR_LOUU_SHIFT (27) /* Bits 27-29: Level of Unification Uniprocessor */
|
||||
#define NVIC_CLIDR_LOUU_MASK (7 << NVIC_CLIDR_LOUU_SHIFT)
|
||||
# define NVIC_CLIDR_LOUU_IMPLEMENTED (1 << NVIC_CLIDR_LOUU_SHIFT)
|
||||
# define NVIC_CLIDR_LOUU_UNIMPLEMENTED (0 << NVIC_CLIDR_LOUU_SHIFT)
|
||||
|
||||
/* Cache Type register (Cortex-M7) */
|
||||
|
||||
#define NVIC_CTR_IMINLINE_SHIFT (0) /* Bits 0-3: ImInLine */
|
||||
#define NVIC_CTR_IMINLINE_MASK (15 << NVIC_CTR_IMINLINE_SHIFT)
|
||||
#define NVIC_CTR_DMINLINE_SHIFT (16) /* Bits 16-19: DmInLine */
|
||||
#define NVIC_CTR_DMINLINE_MASK (15 << NVIC_CTR_DMINLINE_SHIFT)
|
||||
#define NVIC_CTR_ERG_SHIFT (20) /* Bits 20-23: ERG */
|
||||
#define NVIC_CTR_ERG_MASK (15 << NVIC_CTR_ERG_SHIFT)
|
||||
#define NVIC_CTR_CWG_SHIFT (24) /* Bits 24-27: ERG */
|
||||
#define NVIC_CTR_CWG_MASK (15 << NVIC_CTR_CWG_SHIFT)
|
||||
#define NVIC_CTR_FORMAT_SHIFT (29) /* Bits 29-31: Format */
|
||||
#define NVIC_CTR_FORMAT_MASK (7 << NVIC_CTR_FORMAT_SHIFT)
|
||||
|
||||
/* Cache Size ID Register (Cortex-M7) */
|
||||
|
||||
#define NVIC_CCSIDR_LINESIZE_SHIFT (0) /* Bits 0-2: Number of words in each cache line */
|
||||
#define NVIC_CCSIDR_LINESIZE_MASK (7 << NVIC_CCSIDR_LINESIZE_SHIFT)
|
||||
#define NVIC_CCSIDR_ASSOCIATIVITY_SHIFT (3) /* Bits 3-12: Number of ways - 1 */
|
||||
#define NVIC_CCSIDR_ASSOCIATIVITY_MASK (0x3ff << NVIC_CCSIDR_ASSOCIATIVITY_SHIFT)
|
||||
#define NVIC_CCSIDR_NUMSETS_SHIFT (13) /* Bits 13-27: Number of sets - 1 */
|
||||
#define NVIC_CCSIDR_NUMSETS_MASK (0x7fff << NVIC_CCSIDR_NUMSETS_SHIFT)
|
||||
#define NVIC_CCSIDR_WA_SHIFT (1 << 28) /* Bits 28: Write Allocation support */
|
||||
#define NVIC_CCSIDR_RA_SHIFT (1 << 29) /* Bits 29: Read Allocation support */
|
||||
#define NVIC_CCSIDR_WB_SHIFT (1 << 30) /* Bits 30: Write-Back support */
|
||||
#define NVIC_CCSIDR_WT_SHIFT (1 << 31) /* Bits 31: Write-Through support */
|
||||
|
||||
/* Cache Size Selection Register (Cortex-M7) */
|
||||
|
||||
#define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */
|
||||
# define NVIC_CSSELR_IND_ICACHE (0 << 0) /* 0=Instructin Cache */
|
||||
# define NVIC_CSSELR_IND_DCACHE (1 << 0) /* 1=Data Cache */
|
||||
|
||||
#define NVIC_CSSELR_LEVEL_SHIFT (1) /* Bit 1-3: Selects cache level */
|
||||
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)
|
||||
#define NVIC_CSSELR_LEVEL_1 (0 << NVIC_CSSELR_LEVEL_SHIFT)
|
||||
|
||||
/* Debug Exception and Monitor Control Register (DEMCR) */
|
||||
|
||||
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */
|
||||
|
|
|
|||
|
|
@ -54,6 +54,8 @@ endchoice # Atmel SAMV7 Chip Selection
|
|||
config ARCH_CHIP_SAMV71
|
||||
bool
|
||||
default n
|
||||
select ARMV7M_HAVE_ICACHE
|
||||
select ARMV7M_HAVE_DCACHE
|
||||
|
||||
config ARCH_CHIP_SAMV71Q
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -64,6 +64,10 @@ endif
|
|||
CMN_CSRCS += up_vectors.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
|
||||
CMN_CSRCS += up_dcache.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
|
||||
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "cache.h"
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
# include "nvic.h"
|
||||
#endif
|
||||
|
|
@ -325,7 +326,9 @@ void __start(void)
|
|||
showprogress('A');
|
||||
|
||||
/* Enable I- and D-Caches */
|
||||
#warning Missing Logic
|
||||
|
||||
arch_enable_icache();
|
||||
arch_enable_dcache();
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
|
|
|
|||
|
|
@ -1086,16 +1086,26 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
|
|||
|
||||
xdmach->lltail = descr;
|
||||
|
||||
#if 0 /* REVISIT */
|
||||
/* Assume that we will be doing multiple buffer transfers and that
|
||||
* that hardware will be accessing the descriptor via DMA.
|
||||
*/
|
||||
|
||||
arch_clean_dcache((uintptr_t)descr,
|
||||
(uintptr_t)descr + sizeof(struct chnext_view1_s));
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if 1 /* REVISIT */
|
||||
/* Assume that we will be doing multiple buffer transfers and that
|
||||
* that hardware will be accessing the descriptors via DMA.
|
||||
*/
|
||||
|
||||
arch_clean_dcache_all();
|
||||
#endif
|
||||
|
||||
/* Because we hold a count from the counting semaphore, the above
|
||||
* search loop should always be successful.
|
||||
*/
|
||||
|
|
@ -1492,10 +1502,12 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result)
|
|||
* to force reloads from memory.
|
||||
*/
|
||||
|
||||
#if 0 /* Revisit */
|
||||
if (xdmach->rx)
|
||||
{
|
||||
arch_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Perform the DMA complete callback */
|
||||
|
||||
|
|
@ -1856,7 +1868,11 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
|||
|
||||
/* Clean caches associated with the DMA memory */
|
||||
|
||||
#if 0 /* REVISIT */
|
||||
arch_clean_dcache(maddr, maddr + nbytes);
|
||||
#else
|
||||
arch_clean_dcache_all();
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1937,7 +1953,11 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
|||
|
||||
/* Clean caches associated with the DMA memory */
|
||||
|
||||
#if 0 /* REVISIT */
|
||||
arch_clean_dcache(maddr, maddr + nbytes);
|
||||
#else
|
||||
arch_clean_dcache_all();
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -116,6 +116,10 @@ CONFIG_ARMV7M_CMNVECTOR=y
|
|||
#
|
||||
# ARMV7M Configuration Options
|
||||
#
|
||||
CONFIG_ARMV7M_HAVE_ICACHE=y
|
||||
CONFIG_ARMV7M_HAVE_DCACHE=y
|
||||
# CONFIG_ARMV7M_ICACHE is not set
|
||||
# CONFIG_ARMV7M_DCACHE is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
|
||||
|
|
|
|||
Loading…
Reference in New Issue