Add logic to control CAN bit rate via the .config file
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4266 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@ -2346,3 +2346,5 @@
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(Contributed by Mike Smith)
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* configs/stm3240g-eval/src: Add APIs support to support user access to the
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LEDs
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* arch/arm/src/lpc17xx/lpc17_can.c: Add logic to change the CAN bit rate based
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on the NuttX configuration.
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@ -96,6 +96,12 @@
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# define canllvdbg(x...)
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#endif
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/* Timing *******************************************************************/
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/* CAN clocking is provided at CCLK/4 (hardcoded in lpc17_caninitialize()) */
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#define CAN_CCLK_DIVISOR 4
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#define CAN_CLOCK_FREQUENCY (LPC17_CCLK / CAN_CCLK_DIVISOR)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -139,9 +145,15 @@ static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id);
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static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg);
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static bool can_txempty(FAR struct can_dev_s *dev);
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/* CAN interrupts */
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static void can_interrupt(FAR struct can_dev_s *dev);
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static int can12_interrupt(int irq, void *context);
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/* Initialization */
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static int can_bittiming(struct up_dev_s *priv);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -400,19 +412,30 @@ static void can_reset(FAR struct can_dev_s *dev)
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{
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FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv;
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uint32_t baud;
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int ret;
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irqstate_t flags;
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canvdbg("CAN%d\n", priv->port);
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#warning "BTR setting must be calculated from priv->baud"
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baud = 0x25c003;
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flags = irqsave();
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/* Disable the CAN and stop ongong transmissions */
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can_putreg(priv, LPC17_CAN_MOD_OFFSET, CAN_MOD_RM); /* Enter Reset Mode */
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can_putreg(priv, LPC17_CAN_IER_OFFSET, 0); /* Disable interrupts */
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can_putreg(priv, LPC17_CAN_GSR_OFFSET, 0); /* Clear status bits */
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can_putreg(priv, LPC17_CAN_CMR_OFFSET, CAN_CMR_AT); /* Abort transmission */
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can_putreg(priv, LPC17_CAN_BTR_OFFSET, baud); /* Set bit timing */
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/* Set bit timing */
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ret = can_bittiming(priv);
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if (ret != OK)
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{
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candbg("ERROR: Failed to set bit timing: %d\n", ret);
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}
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/* Restart the CAN */
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#ifdef CONFIG_CAN_LOOPBACK
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can_putreg(priv, LPC17_CAN_MOD_OFFSET, CAN_MOD_STM); /* Leave Reset Mode, enter Test Mode */
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#else
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@ -873,6 +896,146 @@ static int can12_interrupt(int irq, void *context)
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return OK;
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}
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/****************************************************************************
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* Name: can_bittiming
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*
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* Description:
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* Set the CAN bit timing register (BTR) based on the configured BAUD.
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*
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* The bit timing logic monitors the serial bus-line and performs sampling
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* and adjustment of the sample point by synchronizing on the start-bit edge
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* and resynchronizing on the following edges.
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*
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* Its operation may be explained simply by splitting nominal bit time into
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* three segments as follows:
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*
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* 1. Synchronization segment (SYNC_SEG): a bit change is expected to occur
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* within this time segment. It has a fixed length of one time quantum
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* (1 x tCAN).
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* 2. Bit segment 1 (BS1): defines the location of the sample point. It
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* includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration
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* is programmable between 1 and 16 time quanta but may be automatically
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* lengthened to compensate for positive phase drifts due to differences
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* in the frequency of the various nodes of the network.
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* 3. Bit segment 2 (BS2): defines the location of the transmit point. It
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* represents the PHASE_SEG2 of the CAN standard. Its duration is
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* programmable between 1 and 8 time quanta but may also be automatically
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* shortened to compensate for negative phase drifts.
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*
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* Pictorially:
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*
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* |<----------------- NOMINAL BIT TIME ----------------->|
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* |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>|
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* |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>|
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*
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* Where
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* Tbs1 is the duration of the BS1 segment
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* Tbs2 is the duration of the BS2 segment
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* Tq is the "Time Quantum"
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*
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* Relationships:
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*
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* baud = 1 / bit_time
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* bit_time = Tq + Tbs1 + Tbs2
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* Tbs1 = Tq * ts1
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* Tbs2 = Tq * ts2
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* Tq = brp * Tpclk1
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*
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* Where:
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* Tpclk1 is the period of the APB clock (PCLK = CCLK / 4).
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*
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* Input Parameter:
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* priv - A reference to the CAN block status
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*
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* Returned Value:
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* Zero on success; a negated errno on failure
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*
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****************************************************************************/
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static int can_bittiming(struct up_dev_s *priv)
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{
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uint32_t canbtr;
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uint32_t brp;
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uint32_t ts1;
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uint32_t ts2;
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uint32_t sjw;
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canllvdbg("CAN%d PCLK1: %d baud: %d\n", priv->port, CAN_CLOCK_FREQUENCY, priv->baud);
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/* Try to get 14 quanta in one bit_time. That is based on the idea that the ideal
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* would be ts1=6 nd ts2=7 and (1 + ts1 + ts2) = 14.
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*
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* bit_time = Tq*(1 +ts1 + ts2)
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* nquanta = bit_time/Tq
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* nquanta = (1 +ts1 + ts2)
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*
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* bit_time = brp * Tpclk1 * (1 + ts1 + ts2)
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* nquanta = bit_time / brp / Tpclk1
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* = PCLK1 / baud / brp
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* brp = PCLK1 / baud / nquanta;
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*
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* Example:
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* PCLK1 = 42,000,000 baud = 1,000,000 nquanta = 14 : brp = 3
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* PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4
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*/
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canbtr = CAN_CLOCK_FREQUENCY / priv->baud;
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if (canbtr < 14)
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{
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/* At the smallest brp value (1), there are already fewer bit times
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* (CAN_CLOCK / baud) is already smaller than our goal. brp must be one
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* and we need make some reasonalble guesses about ts1 and ts2.
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*/
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brp = 1;
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/* In this case, we have to guess a good value for ts1 and ts2 */
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ts1 = (canbtr - 1) >> 1;
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ts2 = canbtr - ts1 - 1;
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if (ts1 == ts2 && ts1 > 1 && ts2 < 16)
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{
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ts1--;
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ts2++;
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}
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}
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/* Otherwise, nquanta is 14, ts1 is 6, ts2 is 7 and we calculate brp to
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* achieve 14 quanta in the bit time
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*/
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else
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{
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ts1 = 6;
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ts2 = 7;
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brp = (canbtr + 7) / 14;
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DEBUGASSERT(brp >=1 && brp < 1024);
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}
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sjw = 1;
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canllvdbg("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
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/* Configure bit timing */
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canbtr = ((brp - 1) << CAN_BTR_BRP_SHIFT) |
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((ts1 - 1) << CAN_BTR_TESG1_SHIFT) |
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((ts2 - 1) << CAN_BTR_TESG2_SHIFT) |
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((sjw - 1) << CAN_BTR_SJW_SHIFT);
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#ifdef CONFIG_CAN_SAM
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/* The bus is sampled 3 times (recommended for low to medium speed buses
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* to spikes on the bus-line).
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*/
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canbtr |= CAN_BTR_SAM;
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#endif
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canllvdbg("Setting CANxBTR= 0x%08x\n", canbtr);
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can_putreg(priv, LPC17_CAN_BTR_OFFSET, canbtr); /* Set bit timing */
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -910,7 +1073,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
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can_putcommon(LPC17_SYSCON_PCONP, regval);
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/* Enable clocking to the CAN module (not necessary... already done
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* in low level clock configuration logic.
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* in low level clock configuration logic).
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*/
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regval = can_getcommon(LPC17_SYSCON_PCLKSEL0);
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@ -937,7 +1100,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
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can_putcommon(LPC17_SYSCON_PCONP, regval);
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/* Enable clocking to the CAN module (not necessary... already done
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* in low level clock configuration logic.
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* in low level clock configuration logic).
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*/
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regval = can_getcommon(LPC17_SYSCON_PCLKSEL0);
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@ -1,8 +1,8 @@
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/**************************************************************************
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* arch/arm/src/lpc17xx/lpc17_lowputc.c
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*
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* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -130,7 +130,7 @@
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#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
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UART_FCR_RXRST | UART_FCR_FIFOEN)
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/* Select a CCLK divider to produce the UART PCLK. The stratey is to select the
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/* Select a CCLK divider to produce the UART PCLK. The strategy is to select the
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* smallest divisor that results in an solution within range of the 16-bit
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* DLM and DLL divisor:
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*
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