Enhance VXLAN dissector
* Fix modelines (no CR after modelines) * Add UDP Port (Attributed in draft 04 Port 4789) * Update link to last draft (no specify change) Change-Id: I4cd89719ae00eb64ce4c234c39b9e18cdc1b8b93 Reviewed-on: https://code.wireshark.org/review/613 Reviewed-by: Alexis La Goutte <alexis.lagoutte@gmail.com> Tested-by: Alexis La Goutte <alexis.lagoutte@gmail.com> Reviewed-by: Evan Huus <eapache@gmail.com>
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@ -21,7 +21,7 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Protocol ref:
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* http://tools.ietf.org/html/draft-mahalingam-dutt-dcops-vxlan-00
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* http://tools.ietf.org/html/draft-mahalingam-dutt-dcops-vxlan-08
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*/
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@ -29,6 +29,8 @@
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#include <epan/packet.h>
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#define UDP_PORT_VXLAN 4789
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void proto_register_vxlan(void);
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void proto_reg_handoff_vxlan(void);
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@ -218,7 +220,9 @@ proto_reg_handoff_vxlan(void)
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eth_handle = find_dissector("eth");
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vxlan_handle = create_dissector_handle(dissect_vxlan, proto_vxlan);
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dissector_add_uint("udp.port", UDP_PORT_VXLAN, vxlan_handle);
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dissector_add_handle("udp.port", vxlan_handle); /* For 'Decode As' */
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}
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/*
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@ -233,5 +237,3 @@ proto_reg_handoff_vxlan(void)
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* vi: set shiftwidth=4 tabstop=8 expandtab:
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* :indentSize=4:tabSize=8:noTabs=true:
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*/
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