mirror of https://gerrit.osmocom.org/libosmocore
502 lines
16 KiB
C
502 lines
16 KiB
C
/*! \file conv_acc_sse_impl.h
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* Accelerated Viterbi decoder implementation:
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* Actual definitions which are being included
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* from both conv_acc_sse.c and conv_acc_sse_avx.c. */
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/*
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* Copyright (C) 2013, 2014 Thomas Tsou <tom@tsou.cc>
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*
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* All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Some distributions (notably Alpine Linux) for some strange reason
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* don't have this #define */
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#ifndef __always_inline
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#define __always_inline inline __attribute__((always_inline))
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#endif
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extern int sse41_supported;
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/* Octo-Viterbi butterfly
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* Compute 8-wide butterfly generating 16 path decisions and 16 accumulated
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* sums. Inputs all packed 16-bit integers in three 128-bit XMM registers.
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* Two intermediate registers are used and results are set in the upper 4
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* registers.
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*
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* Input:
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* M0 - Path metrics 0 (packed 16-bit integers)
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* M1 - Path metrics 1 (packed 16-bit integers)
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* M2 - Branch metrics (packed 16-bit integers)
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*
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* Output:
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* M2 - Selected and accumulated path metrics 0
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* M4 - Selected and accumulated path metrics 1
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* M3 - Path selections 0
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* M1 - Path selections 1
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*/
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#define SSE_BUTTERFLY(M0, M1, M2, M3, M4) \
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{ \
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M3 = _mm_adds_epi16(M0, M2); \
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M4 = _mm_subs_epi16(M1, M2); \
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M0 = _mm_subs_epi16(M0, M2); \
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M1 = _mm_adds_epi16(M1, M2); \
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M2 = _mm_max_epi16(M3, M4); \
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M3 = _mm_or_si128(_mm_cmpgt_epi16(M3, M4), _mm_cmpeq_epi16(M3, M4)); \
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M4 = _mm_max_epi16(M0, M1); \
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M1 = _mm_or_si128(_mm_cmpgt_epi16(M0, M1), _mm_cmpeq_epi16(M0, M1)); \
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}
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/* Two lane deinterleaving K = 5:
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* Take 16 interleaved 16-bit integers and deinterleave to 2 packed 128-bit
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* registers. The operation summarized below. Four registers are used with
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* the lower 2 as input and upper 2 as output.
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*
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* In - 10101010 10101010 10101010 10101010
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* Out - 00000000 11111111 00000000 11111111
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*
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* Input:
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* M0:1 - Packed 16-bit integers
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*
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* Output:
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* M2:3 - Deinterleaved packed 16-bit integers
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*/
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#define _I8_SHUFFLE_MASK 15, 14, 11, 10, 7, 6, 3, 2, 13, 12, 9, 8, 5, 4, 1, 0
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#define SSE_DEINTERLEAVE_K5(M0, M1, M2, M3) \
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{ \
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M2 = _mm_set_epi8(_I8_SHUFFLE_MASK); \
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M0 = _mm_shuffle_epi8(M0, M2); \
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M1 = _mm_shuffle_epi8(M1, M2); \
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M2 = _mm_unpacklo_epi64(M0, M1); \
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M3 = _mm_unpackhi_epi64(M0, M1); \
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}
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/* Two lane deinterleaving K = 7:
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* Take 64 interleaved 16-bit integers and deinterleave to 8 packed 128-bit
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* registers. The operation summarized below. 16 registers are used with the
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* lower 8 as input and upper 8 as output.
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*
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* In - 10101010 10101010 10101010 10101010 ...
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* Out - 00000000 11111111 00000000 11111111 ...
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*
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* Input:
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* M0:7 - Packed 16-bit integers
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*
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* Output:
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* M8:15 - Deinterleaved packed 16-bit integers
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*/
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#define SSE_DEINTERLEAVE_K7(M0, M1, M2, M3, M4, M5, M6, M7, \
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M8, M9, M10, M11, M12, M13, M14, M15) \
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{ \
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M8 = _mm_set_epi8(_I8_SHUFFLE_MASK); \
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M0 = _mm_shuffle_epi8(M0, M8); \
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M1 = _mm_shuffle_epi8(M1, M8); \
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M2 = _mm_shuffle_epi8(M2, M8); \
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M3 = _mm_shuffle_epi8(M3, M8); \
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M4 = _mm_shuffle_epi8(M4, M8); \
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M5 = _mm_shuffle_epi8(M5, M8); \
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M6 = _mm_shuffle_epi8(M6, M8); \
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M7 = _mm_shuffle_epi8(M7, M8); \
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M8 = _mm_unpacklo_epi64(M0, M1); \
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M9 = _mm_unpackhi_epi64(M0, M1); \
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M10 = _mm_unpacklo_epi64(M2, M3); \
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M11 = _mm_unpackhi_epi64(M2, M3); \
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M12 = _mm_unpacklo_epi64(M4, M5); \
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M13 = _mm_unpackhi_epi64(M4, M5); \
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M14 = _mm_unpacklo_epi64(M6, M7); \
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M15 = _mm_unpackhi_epi64(M6, M7); \
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}
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/* Generate branch metrics N = 2:
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* Compute 16 branch metrics from trellis outputs and input values.
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*
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* Input:
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* M0:3 - 16 x 2 packed 16-bit trellis outputs
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* M4 - Expanded and packed 16-bit input value
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*
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* Output:
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* M6:7 - 16 computed 16-bit branch metrics
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*/
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#define SSE_BRANCH_METRIC_N2(M0, M1, M2, M3, M4, M6, M7) \
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{ \
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M0 = _mm_sign_epi16(M4, M0); \
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M1 = _mm_sign_epi16(M4, M1); \
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M2 = _mm_sign_epi16(M4, M2); \
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M3 = _mm_sign_epi16(M4, M3); \
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M6 = _mm_hadds_epi16(M0, M1); \
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M7 = _mm_hadds_epi16(M2, M3); \
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}
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/* Generate branch metrics N = 4:
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* Compute 8 branch metrics from trellis outputs and input values. This
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* macro is reused for N less than 4 where the extra soft input bits are
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* padded.
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*
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* Input:
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* M0:3 - 8 x 4 packed 16-bit trellis outputs
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* M4 - Expanded and packed 16-bit input value
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*
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* Output:
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* M5 - 8 computed 16-bit branch metrics
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*/
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#define SSE_BRANCH_METRIC_N4(M0, M1, M2, M3, M4, M5) \
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{ \
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M0 = _mm_sign_epi16(M4, M0); \
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M1 = _mm_sign_epi16(M4, M1); \
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M2 = _mm_sign_epi16(M4, M2); \
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M3 = _mm_sign_epi16(M4, M3); \
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M0 = _mm_hadds_epi16(M0, M1); \
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M1 = _mm_hadds_epi16(M2, M3); \
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M5 = _mm_hadds_epi16(M0, M1); \
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}
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/* Horizontal minimum
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* Compute horizontal minimum of packed unsigned 16-bit integers and place
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* result in the low 16-bit element of the source register. Only SSE 4.1
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* has a dedicated minpos instruction. One intermediate register is used
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* if SSE 4.1 is not available. This is a destructive operation and the
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* source register is overwritten.
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*
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* Input:
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* M0 - Packed unsigned 16-bit integers
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*
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* Output:
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* M0 - Minimum value placed in low 16-bit element
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*/
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#if defined(HAVE_SSE4_1) || defined(HAVE_SSE41)
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#define SSE_MINPOS(M0, M1) \
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{ \
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if (sse41_supported) { \
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M0 = _mm_minpos_epu16(M0); \
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} else { \
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M1 = _mm_shuffle_epi32(M0, _MM_SHUFFLE(0, 0, 3, 2)); \
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M0 = _mm_min_epi16(M0, M1); \
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M1 = _mm_shufflelo_epi16(M0, _MM_SHUFFLE(0, 0, 3, 2)); \
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M0 = _mm_min_epi16(M0, M1); \
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M1 = _mm_shufflelo_epi16(M0, _MM_SHUFFLE(0, 0, 0, 1)); \
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M0 = _mm_min_epi16(M0, M1); \
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} \
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}
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#else
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#define SSE_MINPOS(M0, M1) \
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{ \
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M1 = _mm_shuffle_epi32(M0, _MM_SHUFFLE(0, 0, 3, 2)); \
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M0 = _mm_min_epi16(M0, M1); \
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M1 = _mm_shufflelo_epi16(M0, _MM_SHUFFLE(0, 0, 3, 2)); \
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M0 = _mm_min_epi16(M0, M1); \
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M1 = _mm_shufflelo_epi16(M0, _MM_SHUFFLE(0, 0, 0, 1)); \
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M0 = _mm_min_epi16(M0, M1); \
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}
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#endif
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/* Normalize state metrics K = 5:
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* Compute 16-wide normalization by subtracting the smallest value from
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* all values. Inputs are 16 packed 16-bit integers across 2 XMM registers.
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* Two intermediate registers are used and normalized results are placed
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* in the originating locations.
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*
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* Input:
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* M0:1 - Path metrics 0:1 (packed 16-bit integers)
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*
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* Output:
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* M0:1 - Normalized path metrics 0:1
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*/
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#define SSE_NORMALIZE_K5(M0, M1, M2, M3) \
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{ \
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M2 = _mm_min_epi16(M0, M1); \
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SSE_MINPOS(M2, M3) \
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SSE_BROADCAST(M2) \
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M0 = _mm_subs_epi16(M0, M2); \
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M1 = _mm_subs_epi16(M1, M2); \
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}
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/* Normalize state metrics K = 7:
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* Compute 64-wide normalization by subtracting the smallest value from
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* all values. Inputs are 8 registers of accumulated sums and 4 temporary
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* registers. Normalized results are returned in the originating locations.
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*
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* Input:
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* M0:7 - Path metrics 0:7 (packed 16-bit integers)
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*
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* Output:
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* M0:7 - Normalized path metrics 0:7
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*/
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#define SSE_NORMALIZE_K7(M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11) \
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{ \
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M8 = _mm_min_epi16(M0, M1); \
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M9 = _mm_min_epi16(M2, M3); \
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M10 = _mm_min_epi16(M4, M5); \
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M11 = _mm_min_epi16(M6, M7); \
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M8 = _mm_min_epi16(M8, M9); \
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M10 = _mm_min_epi16(M10, M11); \
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M8 = _mm_min_epi16(M8, M10); \
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SSE_MINPOS(M8, M9) \
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SSE_BROADCAST(M8) \
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M0 = _mm_subs_epi16(M0, M8); \
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M1 = _mm_subs_epi16(M1, M8); \
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M2 = _mm_subs_epi16(M2, M8); \
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M3 = _mm_subs_epi16(M3, M8); \
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M4 = _mm_subs_epi16(M4, M8); \
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M5 = _mm_subs_epi16(M5, M8); \
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M6 = _mm_subs_epi16(M6, M8); \
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M7 = _mm_subs_epi16(M7, M8); \
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}
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/* Combined BMU/PMU (K=5, N=2)
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* Compute branch metrics followed by path metrics for half rate 16-state
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* trellis. 8 butterflies are computed. Accumulated path sums are not
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* preserved and read and written into the same memory location. Normalize
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* sums if requires.
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*/
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__always_inline static void _sse_metrics_k5_n2(const int16_t *val,
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const int16_t *out, int16_t *sums, int16_t *paths, int norm)
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{
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__m128i m0, m1, m2, m3, m4, m5, m6;
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/* (BMU) Load input sequence */
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m2 = _mm_castpd_si128(_mm_loaddup_pd((double const *) val));
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/* (BMU) Load trellis outputs */
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m0 = _mm_load_si128((__m128i *) &out[0]);
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m1 = _mm_load_si128((__m128i *) &out[8]);
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/* (BMU) Compute branch metrics */
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m0 = _mm_sign_epi16(m2, m0);
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m1 = _mm_sign_epi16(m2, m1);
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m2 = _mm_hadds_epi16(m0, m1);
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/* (PMU) Load accumulated path metrics */
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m0 = _mm_load_si128((__m128i *) &sums[0]);
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m1 = _mm_load_si128((__m128i *) &sums[8]);
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SSE_DEINTERLEAVE_K5(m0, m1, m3, m4)
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/* (PMU) Butterflies: 0-7 */
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SSE_BUTTERFLY(m3, m4, m2, m5, m6)
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if (norm)
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SSE_NORMALIZE_K5(m2, m6, m0, m1)
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_mm_store_si128((__m128i *) &sums[0], m2);
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_mm_store_si128((__m128i *) &sums[8], m6);
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_mm_store_si128((__m128i *) &paths[0], m5);
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_mm_store_si128((__m128i *) &paths[8], m4);
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}
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/* Combined BMU/PMU (K=5, N=3 and N=4)
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* Compute branch metrics followed by path metrics for 16-state and rates
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* to 1/4. 8 butterflies are computed. The input sequence is read four 16-bit
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* values at a time, and extra values should be set to zero for rates other
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* than 1/4. Normally only rates 1/3 and 1/4 are used as there is a
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* dedicated implementation of rate 1/2.
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*/
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__always_inline static void _sse_metrics_k5_n4(const int16_t *val,
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const int16_t *out, int16_t *sums, int16_t *paths, int norm)
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{
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__m128i m0, m1, m2, m3, m4, m5, m6;
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/* (BMU) Load input sequence */
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m4 = _mm_castpd_si128(_mm_loaddup_pd((double const *) val));
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/* (BMU) Load trellis outputs */
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m0 = _mm_load_si128((__m128i *) &out[0]);
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m1 = _mm_load_si128((__m128i *) &out[8]);
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m2 = _mm_load_si128((__m128i *) &out[16]);
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m3 = _mm_load_si128((__m128i *) &out[24]);
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SSE_BRANCH_METRIC_N4(m0, m1, m2, m3, m4, m2)
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/* (PMU) Load accumulated path metrics */
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m0 = _mm_load_si128((__m128i *) &sums[0]);
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m1 = _mm_load_si128((__m128i *) &sums[8]);
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SSE_DEINTERLEAVE_K5(m0, m1, m3, m4)
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/* (PMU) Butterflies: 0-7 */
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SSE_BUTTERFLY(m3, m4, m2, m5, m6)
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if (norm)
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SSE_NORMALIZE_K5(m2, m6, m0, m1)
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_mm_store_si128((__m128i *) &sums[0], m2);
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_mm_store_si128((__m128i *) &sums[8], m6);
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_mm_store_si128((__m128i *) &paths[0], m5);
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_mm_store_si128((__m128i *) &paths[8], m4);
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}
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/* Combined BMU/PMU (K=7, N=2)
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* Compute branch metrics followed by path metrics for half rate 64-state
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* trellis. 32 butterfly operations are computed. Deinterleaving path
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* metrics requires usage of the full SSE register file, so separate sums
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* before computing branch metrics to avoid register spilling.
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*/
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__always_inline static void _sse_metrics_k7_n2(const int16_t *val,
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const int16_t *out, int16_t *sums, int16_t *paths, int norm)
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{
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__m128i m0, m1, m2, m3, m4, m5, m6, m7, m8,
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m9, m10, m11, m12, m13, m14, m15;
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/* (PMU) Load accumulated path metrics */
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m0 = _mm_load_si128((__m128i *) &sums[0]);
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m1 = _mm_load_si128((__m128i *) &sums[8]);
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m2 = _mm_load_si128((__m128i *) &sums[16]);
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m3 = _mm_load_si128((__m128i *) &sums[24]);
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m4 = _mm_load_si128((__m128i *) &sums[32]);
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m5 = _mm_load_si128((__m128i *) &sums[40]);
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m6 = _mm_load_si128((__m128i *) &sums[48]);
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m7 = _mm_load_si128((__m128i *) &sums[56]);
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/* (PMU) Deinterleave to even-odd registers */
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SSE_DEINTERLEAVE_K7(m0, m1, m2, m3 ,m4 ,m5, m6, m7,
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m8, m9, m10, m11, m12, m13, m14, m15)
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/* (BMU) Load input symbols */
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m7 = _mm_castpd_si128(_mm_loaddup_pd((double const *) val));
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/* (BMU) Load trellis outputs */
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m0 = _mm_load_si128((__m128i *) &out[0]);
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m1 = _mm_load_si128((__m128i *) &out[8]);
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m2 = _mm_load_si128((__m128i *) &out[16]);
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m3 = _mm_load_si128((__m128i *) &out[24]);
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SSE_BRANCH_METRIC_N2(m0, m1, m2, m3, m7, m4, m5)
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m0 = _mm_load_si128((__m128i *) &out[32]);
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m1 = _mm_load_si128((__m128i *) &out[40]);
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m2 = _mm_load_si128((__m128i *) &out[48]);
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m3 = _mm_load_si128((__m128i *) &out[56]);
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SSE_BRANCH_METRIC_N2(m0, m1, m2, m3, m7, m6, m7)
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/* (PMU) Butterflies: 0-15 */
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SSE_BUTTERFLY(m8, m9, m4, m0, m1)
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SSE_BUTTERFLY(m10, m11, m5, m2, m3)
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_mm_store_si128((__m128i *) &paths[0], m0);
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_mm_store_si128((__m128i *) &paths[8], m2);
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_mm_store_si128((__m128i *) &paths[32], m9);
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_mm_store_si128((__m128i *) &paths[40], m11);
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/* (PMU) Butterflies: 17-31 */
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SSE_BUTTERFLY(m12, m13, m6, m0, m2)
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SSE_BUTTERFLY(m14, m15, m7, m9, m11)
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_mm_store_si128((__m128i *) &paths[16], m0);
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_mm_store_si128((__m128i *) &paths[24], m9);
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_mm_store_si128((__m128i *) &paths[48], m13);
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_mm_store_si128((__m128i *) &paths[56], m15);
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|
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if (norm)
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SSE_NORMALIZE_K7(m4, m1, m5, m3, m6, m2,
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m7, m11, m0, m8, m9, m10)
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|
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_mm_store_si128((__m128i *) &sums[0], m4);
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_mm_store_si128((__m128i *) &sums[8], m5);
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_mm_store_si128((__m128i *) &sums[16], m6);
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_mm_store_si128((__m128i *) &sums[24], m7);
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_mm_store_si128((__m128i *) &sums[32], m1);
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_mm_store_si128((__m128i *) &sums[40], m3);
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_mm_store_si128((__m128i *) &sums[48], m2);
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_mm_store_si128((__m128i *) &sums[56], m11);
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}
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|
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/* Combined BMU/PMU (K=7, N=3 and N=4)
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* Compute branch metrics followed by path metrics for half rate 64-state
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* trellis. 32 butterfly operations are computed. Deinterleave path
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* metrics before computing branch metrics as in the half rate case.
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*/
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__always_inline static void _sse_metrics_k7_n4(const int16_t *val,
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const int16_t *out, int16_t *sums, int16_t *paths, int norm)
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{
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__m128i m0, m1, m2, m3, m4, m5, m6, m7;
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__m128i m8, m9, m10, m11, m12, m13, m14, m15;
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|
|
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/* (PMU) Load accumulated path metrics */
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m0 = _mm_load_si128((__m128i *) &sums[0]);
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m1 = _mm_load_si128((__m128i *) &sums[8]);
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m2 = _mm_load_si128((__m128i *) &sums[16]);
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m3 = _mm_load_si128((__m128i *) &sums[24]);
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m4 = _mm_load_si128((__m128i *) &sums[32]);
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m5 = _mm_load_si128((__m128i *) &sums[40]);
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m6 = _mm_load_si128((__m128i *) &sums[48]);
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|
m7 = _mm_load_si128((__m128i *) &sums[56]);
|
|
|
|
/* (PMU) Deinterleave into even and odd packed registers */
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|
SSE_DEINTERLEAVE_K7(m0, m1, m2, m3 ,m4 ,m5, m6, m7,
|
|
m8, m9, m10, m11, m12, m13, m14, m15)
|
|
|
|
/* (BMU) Load and expand 8-bit input out to 16-bits */
|
|
m7 = _mm_castpd_si128(_mm_loaddup_pd((double const *) val));
|
|
|
|
/* (BMU) Load and compute branch metrics */
|
|
m0 = _mm_load_si128((__m128i *) &out[0]);
|
|
m1 = _mm_load_si128((__m128i *) &out[8]);
|
|
m2 = _mm_load_si128((__m128i *) &out[16]);
|
|
m3 = _mm_load_si128((__m128i *) &out[24]);
|
|
|
|
SSE_BRANCH_METRIC_N4(m0, m1, m2, m3, m7, m4)
|
|
|
|
m0 = _mm_load_si128((__m128i *) &out[32]);
|
|
m1 = _mm_load_si128((__m128i *) &out[40]);
|
|
m2 = _mm_load_si128((__m128i *) &out[48]);
|
|
m3 = _mm_load_si128((__m128i *) &out[56]);
|
|
|
|
SSE_BRANCH_METRIC_N4(m0, m1, m2, m3, m7, m5)
|
|
|
|
m0 = _mm_load_si128((__m128i *) &out[64]);
|
|
m1 = _mm_load_si128((__m128i *) &out[72]);
|
|
m2 = _mm_load_si128((__m128i *) &out[80]);
|
|
m3 = _mm_load_si128((__m128i *) &out[88]);
|
|
|
|
SSE_BRANCH_METRIC_N4(m0, m1, m2, m3, m7, m6)
|
|
|
|
m0 = _mm_load_si128((__m128i *) &out[96]);
|
|
m1 = _mm_load_si128((__m128i *) &out[104]);
|
|
m2 = _mm_load_si128((__m128i *) &out[112]);
|
|
m3 = _mm_load_si128((__m128i *) &out[120]);
|
|
|
|
SSE_BRANCH_METRIC_N4(m0, m1, m2, m3, m7, m7)
|
|
|
|
/* (PMU) Butterflies: 0-15 */
|
|
SSE_BUTTERFLY(m8, m9, m4, m0, m1)
|
|
SSE_BUTTERFLY(m10, m11, m5, m2, m3)
|
|
|
|
_mm_store_si128((__m128i *) &paths[0], m0);
|
|
_mm_store_si128((__m128i *) &paths[8], m2);
|
|
_mm_store_si128((__m128i *) &paths[32], m9);
|
|
_mm_store_si128((__m128i *) &paths[40], m11);
|
|
|
|
/* (PMU) Butterflies: 17-31 */
|
|
SSE_BUTTERFLY(m12, m13, m6, m0, m2)
|
|
SSE_BUTTERFLY(m14, m15, m7, m9, m11)
|
|
|
|
_mm_store_si128((__m128i *) &paths[16], m0);
|
|
_mm_store_si128((__m128i *) &paths[24], m9);
|
|
_mm_store_si128((__m128i *) &paths[48], m13);
|
|
_mm_store_si128((__m128i *) &paths[56], m15);
|
|
|
|
if (norm)
|
|
SSE_NORMALIZE_K7(m4, m1, m5, m3, m6, m2,
|
|
m7, m11, m0, m8, m9, m10)
|
|
|
|
_mm_store_si128((__m128i *) &sums[0], m4);
|
|
_mm_store_si128((__m128i *) &sums[8], m5);
|
|
_mm_store_si128((__m128i *) &sums[16], m6);
|
|
_mm_store_si128((__m128i *) &sums[24], m7);
|
|
_mm_store_si128((__m128i *) &sums[32], m1);
|
|
_mm_store_si128((__m128i *) &sums[40], m3);
|
|
_mm_store_si128((__m128i *) &sums[48], m2);
|
|
_mm_store_si128((__m128i *) &sums[56], m11);
|
|
}
|