forked from osmocom/wireshark
ORAN: eAxC ID flexible bit allocations
This commit is contained in:
KATAOKA, Toshihiro
Martin Mathieson
parent
9c2cbc842a
commit
c41a27b96d
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@ -167,6 +167,7 @@ static expert_field ei_oran_invalid_sample_bit_width = EI_INIT;
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static expert_field ei_oran_reserved_numBundPrb = EI_INIT;
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static expert_field ei_oran_extlen_wrong = EI_INIT;
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static expert_field ei_oran_extlen_zero = EI_INIT;
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static expert_field ei_oran_invalid_eaxc_bit_width = EI_INIT;
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/* These are the message types handled by this dissector */
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@ -175,6 +176,11 @@ static expert_field ei_oran_extlen_zero = EI_INIT;
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/* Preference settings. */
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static guint pref_du_port_id_bits = 2;
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static guint pref_bandsector_id_bits = 6;
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static guint pref_cc_id_bits = 4;
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static guint pref_ru_port_id_bits = 4;
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static guint pref_sample_bit_width_uplink = 14;
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static guint pref_sample_bit_width_downlink = 14;
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@ -486,23 +492,34 @@ addPcOrRtcid(tvbuff_t *tvb, proto_tree *tree, gint *offset, const char *name)
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/* Subtree */
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proto_item *item;
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proto_tree *oran_pcid_tree = proto_tree_add_subtree(tree, tvb, *offset, 2, ett_oran_ecpri_pcid, &item, name);
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guint32 duPortId, aCellId, ccId, ruPortId = 0;
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guint64 duPortId, bandSectorId, ccId, ruPortId = 0;
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gint id_offset = *offset;
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/* DU Port ID */
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proto_tree_add_item_ret_uint(oran_pcid_tree, hf_oran_du_port_id, tvb, *offset, 1, ENC_NA, &duPortId);
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/* BandSector ID */
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proto_tree_add_item_ret_uint(oran_pcid_tree, hf_oran_bandsector_id, tvb, *offset, 1, ENC_NA, &aCellId);
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*offset += 1;
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/* CC ID */
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proto_tree_add_item_ret_uint(oran_pcid_tree, hf_oran_cc_id, tvb, *offset, 1, ENC_NA, &ccId);
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/* RU Port ID */
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proto_tree_add_item_ret_uint(oran_pcid_tree, hf_oran_ru_port_id, tvb, *offset, 1, ENC_NA, &ruPortId);
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*offset += 1;
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if (!((pref_du_port_id_bits > 0) && (pref_bandsector_id_bits > 0) && (pref_cc_id_bits > 0) && (pref_ru_port_id_bits > 0) && ((pref_du_port_id_bits + pref_bandsector_id_bits + pref_cc_id_bits + pref_ru_port_id_bits) == 16))) {
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expert_add_info(NULL, tree, &ei_oran_invalid_eaxc_bit_width);
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*offset += 2;
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return;
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}
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proto_item_append_text(item, " (DU_Port_ID: %d, A_Cell_ID: %d, CC_ID: %d, RU_Port_ID: %d)", duPortId, aCellId, ccId, ruPortId);
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guint bit_offset = *offset * 8;
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/* DU Port ID */
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proto_tree_add_bits_ret_val(oran_pcid_tree, hf_oran_du_port_id, tvb, bit_offset, pref_du_port_id_bits, &duPortId, ENC_BIG_ENDIAN);
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bit_offset += pref_du_port_id_bits;
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/* BandSector ID */
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proto_tree_add_bits_ret_val(oran_pcid_tree, hf_oran_bandsector_id, tvb, bit_offset, pref_bandsector_id_bits, &bandSectorId, ENC_BIG_ENDIAN);
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bit_offset += pref_bandsector_id_bits;
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/* CC ID */
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proto_tree_add_bits_ret_val(oran_pcid_tree, hf_oran_cc_id, tvb, bit_offset, pref_cc_id_bits, &ccId, ENC_BIG_ENDIAN);
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bit_offset += pref_cc_id_bits;
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/* RU Port ID */
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proto_tree_add_bits_ret_val(oran_pcid_tree, hf_oran_ru_port_id, tvb, bit_offset, pref_ru_port_id_bits, &ruPortId, ENC_BIG_ENDIAN);
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bit_offset += pref_ru_port_id_bits;
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*offset += 2;
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proto_item_append_text(item, " (DU_Port_ID: %d, BandSector_ID: %d, CC_ID: %d, RU_Port_ID: %d)", (int)duPortId, (int)bandSectorId, (int)ccId, (int)ruPortId);
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char id[16];
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snprintf(id, 16, "%1x:%2.2x:%1x:%1x", duPortId, aCellId, ccId, ruPortId);
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snprintf(id, 16, "%x:%x:%x:%x", (int)duPortId, (int)bandSectorId, (int)ccId, (int)ruPortId);
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proto_item *pi = proto_tree_add_string(oran_pcid_tree, hf_oran_c_eAxC_ID, tvb, id_offset, 2, id);
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proto_item_set_generated(pi);
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}
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@ -1680,32 +1697,32 @@ proto_register_oran(void)
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/* Section 3.1.3.1.6 */
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{ &hf_oran_du_port_id,
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{ "DU Port ID", "oran_fh_cus.du_port_id",
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FT_UINT8, BASE_DEC,
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NULL, 0xc0,
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FT_UINT16, BASE_DEC,
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NULL, 0x0,
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NULL, HFILL }
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},
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/* Section 3.1.3.1.6 */
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{ &hf_oran_bandsector_id,
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{ "BandSector ID", "oran_fh_cus.bandsector_id",
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FT_UINT8, BASE_DEC,
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NULL, 0x3f,
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FT_UINT16, BASE_DEC,
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NULL, 0x0,
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NULL, HFILL }
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},
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/* Section 3.1.3.1.6 */
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{ &hf_oran_cc_id,
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{ "CC ID", "oran_fh_cus.cc_id",
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FT_UINT8, BASE_DEC,
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NULL, 0xf0,
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FT_UINT16, BASE_DEC,
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NULL, 0x0,
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NULL, HFILL }
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},
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/* Section 3.1.3.1.6 */
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{ &hf_oran_ru_port_id,
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{ "RU Port ID", "oran_fh_cus.ru_port_id",
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FT_UINT8, BASE_DEC,
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NULL, 0x0f,
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FT_UINT16, BASE_DEC,
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NULL, 0x0,
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NULL, HFILL }
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},
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@ -2690,6 +2707,7 @@ proto_register_oran(void)
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{ &ei_oran_invalid_sample_bit_width, { "oran_fh_cus.invalid_sample_bit_width", PI_UNDECODED, PI_ERROR, "Unsupported sample bit width", EXPFILL }},
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{ &ei_oran_reserved_numBundPrb, { "oran_fh_cus.reserved_numBundPrb", PI_MALFORMED, PI_ERROR, "Reserved value of numBundPrb", EXPFILL }},
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{ &ei_oran_extlen_wrong, { "oran_fh_cus.extlen_wrong", PI_MALFORMED, PI_ERROR, "extlen doesn't match number of dissected bytes", EXPFILL }},
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{ &ei_oran_invalid_eaxc_bit_width, { "oran_fh_cus.invalid_exac_bit_width", PI_UNDECODED, PI_ERROR, "Inconsistent eAxC bit width", EXPFILL }},
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{ &ei_oran_extlen_zero, { "oran_fh_cus.extlen_zero", PI_MALFORMED, PI_ERROR, "extlen - zero is reserved value", EXPFILL }}
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};
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@ -2709,6 +2727,15 @@ proto_register_oran(void)
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module_t * oran_module = prefs_register_protocol(proto_oran, NULL);
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/* Register bit width/compression preferences separately by direction. */
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prefs_register_uint_preference(oran_module, "oran.du_port_id_bits", "DU Port ID bits [a]",
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"The bit width of DU Port ID, sum of a,b,c&d must be 16", 10, &pref_du_port_id_bits);
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prefs_register_uint_preference(oran_module, "oran.bandsector_id_bits", "BandSector ID bits [b]",
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"The bit width of BandSector ID, sum of a,b,c&d must be 16", 10, &pref_bandsector_id_bits);
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prefs_register_uint_preference(oran_module, "oran.cc_id_bits", "CC ID bits [c]",
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"The bit width of CC ID, sum of a,b,c&d must be 16", 10, &pref_cc_id_bits);
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prefs_register_uint_preference(oran_module, "oran.ru_port_id_bits", "RU Port ID bits [d]",
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"The bit width of RU Port ID, sum of a,b,c&d must be 16", 10, &pref_ru_port_id_bits);
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prefs_register_uint_preference(oran_module, "oran.iq_bitwidth_up", "IQ Bitwidth Uplink",
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"The bit width of a sample in the Uplink", 10, &pref_sample_bit_width_uplink);
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prefs_register_enum_preference(oran_module, "oran.ud_comp_up", "Uplink User Data Compression",
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