forked from osmocom/wireshark
Remove Series III code from vwr_read_s2_W_rec().
It's only called if vwr->FPGA_VERSION is S2_W_FPGA, so any code that's run only if it's *not* S2_W_FPGA is dead code. Remove it, for clarity. While we're at it, add some new comments, fix some comments, and get rid of an unused argument to vwr_read_s2_W_rec(). Change-Id: I3e4bd5d7a79f36d8354a0bbf875ee87eeaf60d43 Reviewed-on: https://code.wireshark.org/review/21414 Reviewed-by: Guy Harris <guy@alum.mit.edu>
This commit is contained in:
Guy Harris
parent
c0a1ce2821
commit
a48997a174
244
wiretap/vwr.c
244
wiretap/vwr.c
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@ -82,12 +82,48 @@
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#define COMMAND_RX 0x21
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#define COMMAND_TX 0x31
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/* the metadata headers */
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/*
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* The data in packet records begins with a sequence of metadata headers.
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*
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* For packet records from FPGA versions < 48:
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*
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* The first header is the IxVeriWave common header, and that's
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* followed either by a WLAN metadata header or an Ethernet
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* metadata header. The port type field indicates whether it's
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* a WLAN packet or an Ethernet packet. Following that may, for
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* WLAN, be 1 octet of information from the FPGA and 16 bytes of
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* data including the PLCP header. After that comes the WLAN or
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* Ethernet frame, beginning with the MAC header.
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*
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* For packet records from FPGA versions >= 48:
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*
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* The first header contains only a 1-octet port type value, which
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* has a packet type value in the upper 4 bits and zero in the lower
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* 4 bits. NOTE: this is indistinguishable from an old FPGA header
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* if the packet type value is 0.
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*
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* If the packet type value isn't 3, the port type value is followed
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* by a 1-octet FPGA version number, which is followed by a timestamp
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* header.
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*
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* If the packet type value is 3 or 4, the next item is an RF metadata
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* header. For type 3, that immediately follows the port number octet,
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* otherwise it immediately follows the timestamp header.
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*
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* If the packet type isn't 3, the next item is a WLAN metadata header,
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* in a format different from the WLAN metadata header for FPGA versions
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* < 48. That is followed by a PLCP header, which is followed by a
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* header giving additional layer 2 through 4 metadata.
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*
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* Following those headers is the WLAN or Ethernet frame, beginning with
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* the MAC header.
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*/
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/*
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* IxVeriWave common header:
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*
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* 2 octets - port type
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* 1 octet - port type
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* 1 octet - FPGA version, or 0
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* 2 octets - length of the common header
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* 2 octets - MSDU length
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* 4 octets - flow ID
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@ -101,7 +137,7 @@
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*/
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/* Size of the IxVeriWave common header */
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#define STATS_COMMON_FIELDS_LEN (2+2+2+4+2+2+4+4+8+8+4)
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#define STATS_COMMON_FIELDS_LEN (1+1+2+2+4+2+2+4+4+8+8+4)
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/* Port type */
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#define WLAN_PORT 0
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@ -176,13 +212,74 @@
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/* Size of the VeriWave Ethernet metadata header */
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#define EXT_ETHERNET_FIELDS_LEN (2+2+2+4+4+4)
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/*
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* OCTO timestamp header.
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*
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* 4 octets - latency or 0
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* 4 octets - lower 32 bits of signature time stamp
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* 8 octets - start time
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* 8 octets - end time
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* 4 octets - delta(?) time
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*/
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/* Size of Timestamp header including 1st 4 Management bytes for OCTO version FPGA*/
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#define OCTO_TIMESTAMP_FIELDS_LEN (4+4+8+8+4+4)
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/*
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* OCTO layer 1-4 header:
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*
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* 2 octets - header length
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* 1 octet - l1p_1
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* 1 octet - number of spatial streams
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* 2 octets - PHY rate
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* 1 octet - l1p_2
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* 1 octet - RSSI
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* 1 octet - antenna b signal power, or 100 if missing
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* 1 octet - antenna c signal power, or 100 if missing
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* 1 octet - antenna d signal power, or 100 if missing
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* 1 octet - signal bandwidth mask
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* 1 octet - antenna port energy detect and VU_MASK
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* 1 octet - L1InfoC or 0
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* 2 octets - MSDU length
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* 16 octets - PLCP?
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* 4 octets - BM, BV, CV, BSSID and ClientID
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* 2 octets - FV, QT, HT, L4V, TID and WLAN type
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* 1 octets - flow sequence number
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* 3 octets - flow ID
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* 2 octets - layer 4 ID
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* 4 octets - payload decode
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* 3 octets - info
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* 4 octets - errors
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*/
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/* Size of Layer-1, PLCP, and Layer-2/4 header incase of OCTO version FPGA */
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#define OCTO_LAYER1TO4_LEN (2+14+16+23)
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/* Size of RF header*/
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/*
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* OCTO modified RF layer:
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*
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* 1 octet - RF ID
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* 3 octets - unused (zero)
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* 8 octets - noise for 4 ports
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* 8 octets - signal/noise ration for 4 ports
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* 8 octets - PFE for 4 ports
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* 8 octets - EVM SIG data for 4 ports
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* 8 octets - EVM SIG pilot for 4 ports
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* 8 octets - EVM Data data for 4 ports
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* 8 octets - EVM Data pilot for 4 ports
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* 8 octets - EVM worst symbol for 4 ports
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* 8 octets - CONTEXT_P for 4 ports
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*
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* Not supplied:
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* 24 octets of additional data
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*/
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/* Size of RF header, if all fields were supplied */
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#define OCTO_RF_MOD_ACTUAL_LEN 100 /* */
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/* Size of RF header with the fields we do supply */
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#define OCTO_MODIFIED_RF_LEN 76 /* 24 bytes of RF are not displayed*/
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/*Offset of differnt parameters of RF header for port-1*/
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#define RF_PORT_1_NOISE_OFF 4
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#define RF_PORT_1_SNR_OFF 6
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@ -628,7 +725,7 @@ typedef struct {
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guint32 RETRY_ERR; /* excessive retries on TX failure */
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guint8 IS_RX; /* TX/RX bit in STATS block */
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guint8 MT_MASK; /* modulation type mask */
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guint16 VCID_MASK; /* VC ID is only 9 bits */
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guint16 VCID_MASK; /* VC ID might not be a full 16 bits */
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guint32 FLOW_VALID; /* flow-is-valid flag (else force to 0) */
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guint16 QOS_VALID;
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guint32 RX_DECRYPTS; /* RX-frame-was-decrypted bits */
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@ -678,7 +775,7 @@ static int vwr_get_fpga_version(wtap *, int *, gchar **);
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static gboolean vwr_read_s1_W_rec(vwr_t *, struct wtap_pkthdr *, Buffer *,
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const guint8 *, int, int *, gchar **);
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static gboolean vwr_read_s2_W_rec(vwr_t *, struct wtap_pkthdr *, Buffer *,
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const guint8 *, int, int, int, int *,
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const guint8 *, int, int, int *,
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gchar **);
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/* For FPGA version >= 48 (OCTO Platform), following function will be used */
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static gboolean vwr_read_s3_W_rec(vwr_t *, struct wtap_pkthdr *, Buffer *,
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@ -981,8 +1078,8 @@ static int vwr_get_fpga_version(wtap *wth, int *err, gchar **err_info)
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return (-1);
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}
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g_free(rec);
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/* We found an FPGA that works */
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g_free(rec);
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return fpga_version;
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}
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}
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@ -1180,9 +1277,11 @@ static gboolean vwr_read_s1_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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*
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* All values are copied out in little-endian byte order.
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*/
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phtole8(&data_ptr[bytes_written], WLAN_PORT); /* 1st octet of record for port_type*/
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/* 1st octet of record for port_type and command (command is 0, hence RX) */
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phtole8(&data_ptr[bytes_written], WLAN_PORT);
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bytes_written += 1;
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phtole8(&data_ptr[bytes_written], 0); /* 2nd octet of record for fpga version*/
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/* 2nd octet of record for fpga version (0, hence pre-OCTO) */
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phtole8(&data_ptr[bytes_written], 0);
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bytes_written += 1;
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phtoles(&data_ptr[bytes_written], STATS_COMMON_FIELDS_LEN); /* it_len */
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bytes_written += 2;
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@ -1286,12 +1385,11 @@ static gboolean vwr_read_s1_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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Buffer *buf, const guint8 *rec, int rec_size,
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int IS_TX, int log_mode _U_, int *err, gchar **err_info)
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Buffer *buf, const guint8 *rec, int rec_size,
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int IS_TX, int *err, gchar **err_info)
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{
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guint8 *data_ptr;
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int bytes_written = 0; /* bytes output to buf so far */
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register int i; /* temps */
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const guint8 *s_start_ptr,*s_trail_ptr, *plcp_ptr, *m_ptr; /* stats & MPDU ptr */
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guint32 msdu_length, actual_octets; /* octets in frame */
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guint8 l1p_1,l1p_2, plcp_type, mcs_index, nss; /* mod (CCK-L/CCK-S/OFDM) */
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@ -1314,8 +1412,6 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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guint64 delta_b; /* Used for calculating latency */
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guint16 phyRate;
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guint16 vw_flags; /* VeriWave-specific packet flags */
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guint8 L1InfoC,vht_ndp_flag = 0;
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guint8 plcp_hdr_flag = 0; /* indicates plcp hdr info */
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/*
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* The record data must be large enough to hold the statistics header,
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@ -1334,89 +1430,38 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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s_start_ptr = &(rec[0]); /* point to stats header */
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s_trail_ptr = &(rec[rec_size - vVW510021_W_STATS_TRAILER_LEN]); /* point to stats trailer */
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/* L1p info is different for series III and for Series II - need to check */
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l1p_1 = s_start_ptr[vVW510021_W_L1P_1_OFF];
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l1p_2 = s_start_ptr[vVW510021_W_L1P_2_OFF];
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if (vwr->FPGA_VERSION == S2_W_FPGA)
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mcs_index = vVW510021_W_S2_MCS_INDEX(l1p_1);
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plcp_type = vVW510021_W_S2_PLCP_TYPE(l1p_2);
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/* we do the range checks at the end before copying the values
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into the wtap header */
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msdu_length = ((s_start_ptr[vVW510021_W_MSDU_LENGTH_OFF+1] & 0x1f) << 8)
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+ s_start_ptr[vVW510021_W_MSDU_LENGTH_OFF];
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vc_id = pntoh16(&s_start_ptr[vVW510021_W_VCID_OFF]);
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if (IS_TX)
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{
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mcs_index = vVW510021_W_S2_MCS_INDEX(l1p_1);
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plcp_type = vVW510021_W_S2_PLCP_TYPE(l1p_2);
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/* we do the range checks at the end before copying the values
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into the wtap header */
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msdu_length = ((s_start_ptr[vVW510021_W_MSDU_LENGTH_OFF+1] & 0x1f) << 8)
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+ s_start_ptr[vVW510021_W_MSDU_LENGTH_OFF];
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vc_id = pntoh16(&s_start_ptr[vVW510021_W_VCID_OFF]);
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if (IS_TX)
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{
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rssi[0] = (s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x80) ?
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-1 * (s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x7f) :
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s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x7f;
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}
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else
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{
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rssi[0] = (s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x80) ?
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(s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF]- 256) :
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s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF];
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}
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rssi[1] = 100;
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rssi[2] = 100;
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rssi[3] = 100;
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nss = (mcs_index / 8) + 1;
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plcp_ptr = &(rec[8]);
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rssi[0] = (s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x80) ?
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-1 * (s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x7f) :
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s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x7f;
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}
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else
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{
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plcp_type = vVW510021_W_S3_PLCP_TYPE(l1p_2);
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if (plcp_type == vVW510021_W_PLCP_VHT_MIXED)
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{
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/* S3 FPGA VHT frames ***/
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mcs_index = vVW510021_W_S3_MCS_INDEX_VHT(l1p_1);
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nss = vVW510021_W_S3_NSS_VHT(l1p_1); /* The nss is zero based from the fpga - increment it here */
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plcp_hdr_flag = 1;
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}
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else /*** S3_FPGA HT frames ***/
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{
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mcs_index = l1p_1 & 0x3f;
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nss = (mcs_index / 8) + 1;
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}
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/*** Extract NDP Flag if it is a received frame ***/
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if (!IS_TX){
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L1InfoC = s_start_ptr[8];
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vht_ndp_flag = L1InfoC & 0x80;
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}
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msdu_length = pntoh24(&s_start_ptr[9]);
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vc_id = pntoh16(&s_start_ptr[14]) & vVW510024_W_VCID_MASK;
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for (i = 0; i < 4; i++)
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{
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if (IS_TX)
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{
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rssi[i] = (s_start_ptr[4+i] & 0x80) ? -1 * (s_start_ptr[4+i] & 0x7f) : s_start_ptr[4+i] & 0x7f;
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}
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else
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{
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rssi[i] = (s_start_ptr[4+i] >= 128) ? (s_start_ptr[4+i] - 256) : s_start_ptr[4+i];
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}
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}
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/*** 16 bytes of PLCP header + 1 byte of L1P for user position ***/
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/* XXX - S3 claims to have 16 bytes of stats block and 16 bytes of
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*something*. Are those 16 bytes the PLCP? */
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plcp_ptr = &(rec[16]);
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rssi[0] = (s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF] & 0x80) ?
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(s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF]- 256) :
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s_start_ptr[vVW510021_W_RSSI_TXPOWER_OFF];
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}
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/*** Add the PLCP length for S3_W_FPGA version VHT frames for Beamforming decode ***/
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rssi[1] = 100;
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rssi[2] = 100;
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rssi[3] = 100;
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nss = (mcs_index / 8) + 1;
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plcp_ptr = &(rec[8]);
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actual_octets = msdu_length;
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if (plcp_hdr_flag == 1) {
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/*** 16 bytes of PLCP header + 1 byte of L1P for user position ***/
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actual_octets = actual_octets + 17;
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}
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/*
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* Sanity check the octets field to determine if it's greater than
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* the packet data available in the record - i.e., the record size
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@ -1628,9 +1673,11 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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* All values are copied out in little-endian byte order.
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*/
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/*** msdu_length = msdu_length + 16; ***/
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phtole8(&data_ptr[bytes_written], WLAN_PORT); /* 1st octet of record for port*/
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/* 1st octet of record for port_type and command (command is 0, hence RX) */
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phtole8(&data_ptr[bytes_written], WLAN_PORT);
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bytes_written += 1;
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phtole8(&data_ptr[bytes_written], 0); /* 2nd octet of record for fpga version*/
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/* 2nd octet of record for fpga version (0, hence pre-OCTO) */
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phtole8(&data_ptr[bytes_written], 0);
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bytes_written += 1;
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phtoles(&data_ptr[bytes_written], STATS_COMMON_FIELDS_LEN); /* it_len */
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bytes_written += 2;
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@ -1676,12 +1723,6 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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phtoles(&data_ptr[bytes_written], phyRate);
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bytes_written += 2;
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/*** If received frame populate the ndp_flag in the same byte as plcp_type***/
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if (!IS_TX) {
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plcp_type = vht_ndp_flag + plcp_type;
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}
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data_ptr[bytes_written] = plcp_type;
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bytes_written += 1;
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@ -1728,15 +1769,6 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
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phtolel(&data_ptr[bytes_written], errors);
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bytes_written += 4;
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/*** copy PLCP header and L1InfoC for VHT frames***/
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if (plcp_hdr_flag == 1) {
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data_ptr[bytes_written] = L1InfoC;
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bytes_written += 1;
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memcpy(&data_ptr[bytes_written], &rec[16], 16);
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bytes_written += 16;
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}
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/* Finally, copy the whole MAC frame to the packet buffer as-is.
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* This does not include the stats header or the PLCP.
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* This also does not include the last 4 bytes, as those don't
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@ -3138,7 +3170,7 @@ vwr_process_rec_data(FILE_T fh, int rec_size,
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ret = vwr_read_s1_W_rec(vwr, phdr, buf, rec, rec_size, err, err_info);
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break;
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case S2_W_FPGA:
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ret = vwr_read_s2_W_rec(vwr, phdr, buf, rec, rec_size, IS_TX, log_mode, err, err_info);
|
||||
ret = vwr_read_s2_W_rec(vwr, phdr, buf, rec, rec_size, IS_TX, err, err_info);
|
||||
break;
|
||||
case S3_W_FPGA:
|
||||
ret = vwr_read_s3_W_rec(vwr, phdr, buf, rec, rec_size, IS_TX, log_mode, err, err_info);
|
||||
|
|
|
|||
Loading…
Reference in New Issue