diff --git a/epan/dissectors/asn1/ansi_map/packet-ansi_map-template.c b/epan/dissectors/asn1/ansi_map/packet-ansi_map-template.c
index f5f6c7bf06..ba9e97ccdf 100644
--- a/epan/dissectors/asn1/ansi_map/packet-ansi_map-template.c
+++ b/epan/dissectors/asn1/ansi_map/packet-ansi_map-template.c
@@ -5055,7 +5055,7 @@ void proto_register_ansi_map(void) {
            NULL, HFILL }},
         {&hf_ansi_map_cdmachanneldata_nominal_pwr,
          { "Nominal Power", "ansi_map.cdmachanneldata.nominal_pwr",
-           FT_UINT8, BASE_DEC, NULL, 0x71,
+           FT_UINT8, BASE_DEC, NULL, 0x78,
            NULL, HFILL }},
         {&hf_ansi_map_cdmachanneldata_nr_preamble,
          { "Number Preamble", "ansi_map.cdmachanneldata.nr_preamble",
diff --git a/epan/dissectors/asn1/tetra/packet-tetra-template.c b/epan/dissectors/asn1/tetra/packet-tetra-template.c
index 8845539963..89c85ff5e6 100644
--- a/epan/dissectors/asn1/tetra/packet-tetra-template.c
+++ b/epan/dissectors/asn1/tetra/packet-tetra-template.c
@@ -589,7 +589,7 @@ void proto_register_tetra (void)
 		{ "Channel 3", "tetra.rxchannel3", FT_UINT8, BASE_DEC, VALS(recvchanneltypenames), 0x0,
 		"Logical channels type", HFILL }},
 		{ &hf_tetra_timer,
-		{ "Timer", "tetra.timer", FT_UINT16, BASE_HEX, NULL, 0x0,
+		{ "Timer", "tetra.timer", FT_UINT32, BASE_HEX, NULL, 0x0,
 		 "Timer Register", HFILL }},
 		{ &hf_tetra_crc,
 		{ "CRC", "tetra.crc", FT_BOOLEAN, BASE_NONE, NULL, 0x0,