...and add more BOM extd attribs
icE40-usbtrace - full-speed USB tracer
The icE40-usbtrace is an Open Source Hardware + Software passive tracer/sniffer for USB full-speed communication.
It was built as a lower-cost / complexity alternative to OpenVizsla v3.x whose FPGA became virtually impossible (or ridiculously expensive on the grey market) during the 2020/2021 chipocalypse.
The underlying idea is relatively simple: passively tap the CMOS logic-level full-speed USB signals and feed them into a passive/receive-only variant of the no2usb FPGA softcore of Sylvain "tnt" Munaut.
NOTE: This project only supports full-speed USB. Unlike the OpenVizsla, it supports neither low-speed nor high-speed!
The icE40-usbtrace hardware is form-factor compatible to the OpenVizsla v3.2 circuit boards in terms of the USB connector types and locations as well as the PCB outline and mounting holes. It's hence a mechanically compatible drop-in replacement.
hardware directory for the hardware design files.
The gateware (FPGA configuration) is based around the OSHW no2 softcores. They are referenced as git submodules from this repository.
gateware directory for more details.
The gateware can be upgraded via USB DFU (Device Firmware Upgrade)
There's a picoRISCV softcore inside the ice40 FPGA, whose firmware
is provided in the
The firmware can be upgraded via USB DFU (Device Firmware Upgrade)
There's a python library and sample application that can run on a USB host talking to the icE40-usbtrace device firmware. You can implement your own call-back function for handling the captured USB packets.
Building / Repository Structure
This git repository makes use of git submodules for the various softcores.
You will need to run
git submodule init and
git submodule update
to have the respective cores and build either firmware or gateware.
All parts of the project are released under Free / Open Source / Hardware licenses:
- The overall firmware is released under GPL-3.0-or-later (portions under MIT and LGPL-3.0-or-later, check the individual files).
- The hardware design is released under CC-BY-SA 3.0
- The gateware is released under CERN-OHL-P-2.0
- the software is released under LGPL-2.1-or-later