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6 Commits

Author SHA1 Message Date
Thomas Tsou 79a1cf3d34 uhd: set receive gain during initialization
This shouldn't matter much, but the gain settings through the
interface are short circuited right now, which makes this a
problem.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>
2011-05-06 13:34:30 -04:00
Thomas Tsou 0ff69c95ff uhd: set hardware side delay offset for e100
The value is used to align transmit and receive time slots within
a sample. This oscilloscope measured value is close, but may
need minor tweaking.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>
2011-05-06 13:19:47 -04:00
Thomas Tsou 39f0bcfd18 uhd: log useful information on monotonic errors
Track the current errant and previous timestamp values.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>
2011-05-06 12:58:41 -04:00
Thomas Tsou 6c51f54909 uhd: only the E100 supports FPGA timestamps and adjustable clock rate
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
2011-05-05 12:21:17 -04:00
Thomas Tsou b4fa0c4074 uhd: flush initial receive samples
Occasionally, the E100 will have errant timestamps at start
related to previous sessions. Early packets will be thrown
out anyways, so do this explicitly so the timestamps don't
royally fuck up the sample timing.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>
2011-05-05 12:21:08 -04:00
Thomas Tsou 90d7633583 uhd: add 52 MHz transceiver support
These are mostly identical changes as added to the non-52MHz
implementation with the exception of sample rate.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>
2011-05-05 12:20:08 -04:00