With UHD b4fc0d61bb6cbd1a5614745bab9aeb0abc22cb6f
Sample clock will reset to zero after an overrun. Earlier
versions may hang the FPGA, which is non-recoverable,
requiring a manual image reload or reboot.
If reset to zero, attempt to kick the sample clock to the
last properly received timestamp value. At this point,
there will be a timing continuity jump, which will drop
connections, but transmit and receive chains should be
aligned allowing for re-establishment.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Shadow all gains and frequencies, which minimizes device access.
This allows the transceiver to variably control the device
settings.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
This shouldn't matter much, but the gain settings through the
interface are short circuited right now, which makes this a
problem.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
The value is used to align transmit and receive time slots within
a sample. This oscilloscope measured value is close, but may
need minor tweaking.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Occasionally, the E100 will have errant timestamps at start
related to previous sessions. Early packets will be thrown
out anyways, so do this explicitly so the timestamps don't
royally fuck up the sample timing.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
These are mostly identical changes as added to the non-52MHz
implementation with the exception of sample rate.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Thomas Tsou