Transceiver: add WBX, DBSRX, and single board support
Remove all RFX specific parts and control daughterboard
functionality using the base API. The tuning is now set
to a non-inverted image so remove the I/Q swap as well.
Daughterboard configuration is set through an enum
variable. Currently, there is no auto-configuration and
the default is Tx/Rx on sides A/B respectively. For
transceiver boards the receive antenna is set to RX2.
enum dboardConfigType {
TXA_RXB,
TXB_RXA,
TXA_RXA,
TXB_RXB
};
const dboardConfigType dboardConfig = TXA_RXB;
The gains are currently not configurable through the
device API and default to midpoint for the installed
daughterboard(s).
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
This commit is contained in:
Thomas Tsou
parent
d15a9730fe
commit
bf383dd3ff
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@ -41,101 +41,15 @@
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using namespace std;
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string write_it(unsigned v) {
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string s = " ";
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s[0] = (v>>16) & 0x0ff;
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s[1] = (v>>8) & 0x0ff;
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s[2] = (v) & 0x0ff;
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return s;
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}
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const float USRPDevice::LO_OFFSET = 4.0e6;
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const double USRPDevice::masterClockRate = (double) 64.0e6;
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bool USRPDevice::compute_regs(double freq,
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unsigned *R,
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unsigned *control,
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unsigned *N,
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double *actual_freq)
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{
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float phdet_freq = 64.0e6/R_DIV;
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int desired_n = (int) round(freq*freq_mult/phdet_freq);
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*actual_freq = desired_n * phdet_freq/freq_mult;
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float B = floor(desired_n/16);
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float A = desired_n - 16*B;
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unsigned B_DIV = int(B);
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unsigned A_DIV = int(A);
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if (B < A) return false;
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*R = (R_RSV<<22) |
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(BSC << 20) |
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(TEST << 19) |
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(LDP << 18) |
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(ABP << 16) |
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(R_DIV << 2);
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*control = (P<<22) |
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(PD<<20) |
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(CP2 << 17) |
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(CP1 << 14) |
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(PL << 12) |
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(MTLD << 11) |
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(CPG << 10) |
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(CP3S << 9) |
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(PDP << 8) |
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(MUXOUT << 5) |
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(CR << 4) |
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(PC << 2);
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*N = (DIVSEL<<23) |
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(DIV2<<22) |
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(CPGAIN<<21) |
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(B_DIV<<8) |
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(N_RSV<<7) |
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(A_DIV<<2);
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return true;
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}
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bool USRPDevice::tx_setFreq(double freq, double *actual_freq)
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{
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unsigned R, control, N;
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if (!compute_regs(freq, &R, &control, &N, actual_freq)) return false;
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if (R==0) return false;
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m_uTx->_write_spi(0,SPI_ENABLE_TX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((R & ~0x3) | 1));
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m_uTx->_write_spi(0,SPI_ENABLE_TX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((control & ~0x3) | 0));
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usleep(10000);
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m_uTx->_write_spi(0,SPI_ENABLE_TX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((N & ~0x3) | 2));
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if (m_uTx->read_io(0) & PLL_LOCK_DETECT) return true;
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if (m_uTx->read_io(0) & PLL_LOCK_DETECT) return true;
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return false;
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}
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bool USRPDevice::rx_setFreq(double freq, double *actual_freq)
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{
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unsigned R, control, N;
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if (!compute_regs(freq, &R, &control, &N, actual_freq)) return false;
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if (R==0) return false;
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m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((R & ~0x3) | 1));
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m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((control & ~0x3) | 0));
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usleep(10000);
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m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((N & ~0x3) | 2));
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if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
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if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
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return false;
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}
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enum dboardConfigType {
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TXA_RXB,
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TXB_RXA,
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TXA_RXA,
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TXB_RXB
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};
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const dboardConfigType dboardConfig = TXA_RXB;
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const double USRPDevice::masterClockRate = 64.0e6;
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USRPDevice::USRPDevice (double _desiredSampleRate)
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{
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@ -212,6 +126,38 @@ bool USRPDevice::make(bool wSkipRx)
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#endif
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switch (dboardConfig) {
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case TXA_RXB:
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m_dbTx = m_uTx->db(0)[0];
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m_dbRx = m_uRx->db(1)[0];
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txSubdevSpec = usrp_subdev_spec(0,0);
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rxSubdevSpec = usrp_subdev_spec(1,0);
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break;
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case TXB_RXA:
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m_dbTx = m_uTx->db(1)[0];
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m_dbRx = m_uRx->db(0)[0];
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txSubdevSpec = usrp_subdev_spec(1,0);
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rxSubdevSpec = usrp_subdev_spec(0,0);
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break;
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case TXA_RXA:
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m_dbTx = m_uTx->db(0)[0];
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m_dbRx = m_uRx->db(0)[0];
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txSubdevSpec = usrp_subdev_spec(0,0);
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rxSubdevSpec = usrp_subdev_spec(0,0);
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break;
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case TXB_RXB:
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m_dbTx = m_uTx->db(1)[0];
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m_dbRx = m_uRx->db(1)[0];
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txSubdevSpec = usrp_subdev_spec(1,0);
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rxSubdevSpec = usrp_subdev_spec(1,0);
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break;
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default:
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m_dbTx = m_uTx->db(0)[0];
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m_dbRx = m_uRx->db(1)[0];
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txSubdevSpec = usrp_subdev_spec(0,0);
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rxSubdevSpec = usrp_subdev_spec(1,0);
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}
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samplesRead = 0;
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samplesWritten = 0;
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started = false;
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@ -229,36 +175,17 @@ bool USRPDevice::start()
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if (!skipRx) m_uRx->stop();
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m_uTx->stop();
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// power up and configure daughterboards
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m_uTx->_write_oe(0,0,0xffff);
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m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uTx->write_io(0,ENABLE,(POWER_UP|RX_TXN|ENABLE)); /* POWER_UP inverted */
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m_uTx->_write_fpga_reg(FR_ATR_MASK_0 ,0);//RX_TXN|ENABLE);
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m_uTx->_write_fpga_reg(FR_ATR_TXVAL_0,0);//,0 |ENABLE);
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m_uTx->_write_fpga_reg(FR_ATR_RXVAL_0,0);//,RX_TXN|0);
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m_uTx->_write_fpga_reg(40,0);
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m_uTx->_write_fpga_reg(42,0);
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m_uTx->set_pga(0,m_uTx->pga_max()); // should be 20dB
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m_uTx->set_pga(1,m_uTx->pga_max());
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m_uTx->set_mux(0x00000098);
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LOG(INFO) << "TX pgas: " << m_uTx->pga(0) << ", " << m_uTx->pga(1);
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// Transmit settings - gain at midpoint
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m_dbTx->set_gain((m_dbRx->gain_min() + m_dbRx->gain_max()) / 2);
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m_dbTx->set_enable(true);
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m_uTx->set_mux(m_uTx->determine_tx_mux_value(txSubdevSpec));
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if (!skipRx) {
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m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 3*3,0);
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m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 3*3,0);
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m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 3*3,0);
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m_uRx->_write_fpga_reg(43,0);
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m_uRx->_write_oe(1,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uRx->write_io(1,(RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE)); /* POWER_UP inverted */
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//m_uRx->write_io(1,0,RX2_RX1N); // using Tx/Rx/
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m_uRx->write_io(1,RX2_RX1N,RX2_RX1N); // using Rx2
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m_uRx->set_adc_buffer_bypass(2,true);
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m_uRx->set_adc_buffer_bypass(3,true);
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m_uRx->set_pga(2,m_uRx->pga_max()); // should be 20dB
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m_uRx->set_pga(3,m_uRx->pga_max());
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m_uRx->set_mux(0x00000032);
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m_uRx->write_aux_dac(1,0,(int) ceil(0.2*4096.0/3.3)); // set to maximum gain
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}
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// Receive settings - gain at max, antenna RX2 (if available)
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m_dbRx->set_gain(m_dbRx->gain_max());
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m_uRx->set_mux(m_uRx->determine_rx_mux_value(rxSubdevSpec));
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if (!m_dbRx->select_rx_antenna(1))
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m_dbRx->select_rx_antenna(0);
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data = new short[currDataSize];
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dataStart = 0;
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@ -271,7 +198,6 @@ bool USRPDevice::start()
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hi32Timestamp = 0;
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isAligned = false;
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if (!skipRx)
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started = (m_uRx->start() && m_uTx->start());
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else
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@ -289,10 +215,6 @@ bool USRPDevice::stop()
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if (!m_uRx) return false;
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if (!m_uTx) return false;
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// power down
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m_uTx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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m_uRx->write_io(1,POWER_UP,(POWER_UP|ENABLE));
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delete[] currData;
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started = !(m_uRx->stop() && m_uTx->stop());
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@ -519,27 +441,45 @@ bool USRPDevice::updateAlignment(TIMESTAMP timestamp)
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}
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#ifndef SWLOOPBACK
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bool USRPDevice::setTxFreq(double wFreq) {
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// Tune to wFreq+LO_OFFSET, to prevent LO bleedthrough from interfering with transmitted signal.
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double actFreq;
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if (!tx_setFreq(wFreq+LO_OFFSET,&actFreq)) return false;
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bool retVal = m_uTx->set_tx_freq(0,(wFreq-actFreq));
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LOG(INFO) << "set TX: " << wFreq-actFreq << " actual TX: " << m_uTx->tx_freq(0);
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return retVal;
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};
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bool USRPDevice::setTxFreq(double wFreq)
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{
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usrp_tune_result result;
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bool USRPDevice::setRxFreq(double wFreq) {
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// Tune to wFreq-2*LO_OFFSET, to
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// 1) prevent LO bleedthrough (as with the setTxFreq method above)
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// 2) The extra LO_OFFSET pushes potential transmitter energy (GSM BS->MS transmissions
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// are 45Mhz above MS->BS transmissions) into a notch of the baseband lowpass filter
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// in front of the ADC. This possibly gives us an extra 10-20dB Tx/Rx isolation.
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double actFreq;
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if (!rx_setFreq(wFreq-2*LO_OFFSET,&actFreq)) return false;
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bool retVal = m_uRx->set_rx_freq(0,(wFreq-actFreq));
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LOG(DEBUG) << "set RX: " << wFreq-actFreq << " actual RX: " << m_uRx->rx_freq(0);
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return retVal;
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};
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if (m_uTx->tune(0, m_dbTx, wFreq, &result)) {
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LOG(INFO) << "set TX: " << wFreq << std::endl
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<< " baseband freq: " << result.baseband_freq << std::endl
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<< " DDC freq: " << result.dxc_freq << std::endl
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<< " residual freq: " << result.residual_freq;
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return true;
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}
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else {
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LOG(ERROR) << "set TX: " << wFreq << "failed" << std::endl
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<< " baseband freq: " << result.baseband_freq << std::endl
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<< " DDC freq: " << result.dxc_freq << std::endl
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<< " residual freq: " << result.residual_freq;
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return false;
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}
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}
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bool USRPDevice::setRxFreq(double wFreq)
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{
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usrp_tune_result result;
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if (m_uRx->tune(0, m_dbRx, wFreq, &result)) {
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LOG(INFO) << "set RX: " << wFreq << std::endl
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<< " baseband freq: " << result.baseband_freq << std::endl
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<< " DDC freq: " << result.dxc_freq << std::endl
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<< " residual freq: " << result.residual_freq;
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return true;
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}
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else {
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LOG(ERROR) << "set RX: " << wFreq << "failed" << std::endl
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<< " baseband freq: " << result.baseband_freq << std::endl
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<< " DDC freq: " << result.dxc_freq << std::endl
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<< " residual freq: " << result.residual_freq;
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return false;
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}
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}
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#else
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bool USRPDevice::setTxFreq(double wFreq) { return true;};
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@ -63,7 +63,12 @@ private:
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double desiredSampleRate; ///< the desired sampling rate
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usrp_standard_rx_sptr m_uRx; ///< the USRP receiver
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usrp_standard_tx_sptr m_uTx; ///< the USRP transmitter
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db_base_sptr m_dbRx; ///< rx daughterboard
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db_base_sptr m_dbTx; ///< tx daughterboard
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usrp_subdev_spec rxSubdevSpec;
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usrp_subdev_spec txSubdevSpec;
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double actualSampleRate; ///< the actual USRP sampling rate
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unsigned int decimRate; ///< the USRP decimation rate
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@ -103,75 +108,6 @@ private:
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bool firstRead;
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#endif
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/** Mess of constants used to control various hardware on the USRP */
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static const unsigned POWER_UP = (1 << 7);
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static const unsigned RX_TXN = (1 << 6);
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static const unsigned RX2_RX1N = (1 << 6);
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static const unsigned ENABLE = (1 << 5);
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static const unsigned PLL_LOCK_DETECT = (1 << 2);
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static const unsigned SPI_ENABLE_TX_A = 0x10;
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static const unsigned SPI_ENABLE_RX_A = 0x20;
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static const unsigned SPI_ENABLE_TX_B = 0x40;
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static const unsigned SPI_ENABLE_RX_B = 0x80;
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static const unsigned SPI_FMT_MSB = (0 << 7);
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static const unsigned SPI_FMT_HDR_0 = (0 << 5);
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static const float LO_OFFSET;
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//static const float LO_OFFSET = 4.0e6;
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static const unsigned R_DIV = 16;
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static const unsigned P = 1;
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static const unsigned CP2 = 7;
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static const unsigned CP1 = 7;
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static const unsigned DIVSEL = 0;
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static const unsigned DIV2 = 1;
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static const unsigned freq_mult = 2;
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static const unsigned CPGAIN = 0;
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static const float minFreq = 800e6;
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static const float maxFreq = 1000e6;
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static const float freqRes = 4e6;
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// R-Register Common Values
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static const unsigned R_RSV = 0; // bits 23,22
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static const unsigned BSC = 3; // bits 21,20 Div by 8 to be safe
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static const unsigned TEST = 0; // bit 19
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static const unsigned LDP = 1; // bit 18
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static const unsigned ABP = 0; // bit 17,16 3ns
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// N-Register Common Values
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static const unsigned N_RSV = 0; // bit 7
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// Control Register Common Values
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static const unsigned PD = 0; // bits 21,20 Normal operation
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static const unsigned PL = 0; // bits 13,12 11mA
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static const unsigned MTLD = 1; // bit 11 enabled
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static const unsigned CPG = 0; // bit 10 CP setting 1
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static const unsigned CP3S = 0; // bit 9 Normal
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static const unsigned PDP = 1; // bit 8 Positive
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static const unsigned MUXOUT = 1;// bits 7:5 Digital Lock Detect
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static const unsigned CR = 0; // bit 4 Normal
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static const unsigned PC = 1; // bits 3,2 Core power 10mA
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// ATR register value
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static const int FR_ATR_MASK_0 = 20;
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static const int FR_ATR_TXVAL_0 = 21;
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static const int FR_ATR_RXVAL_0 = 22;
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/** Compute register values to tune daughterboard to desired frequency */
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bool compute_regs(double freq,
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unsigned *R,
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unsigned *control,
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unsigned *N,
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double *actual_freq);
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/** Set the transmission frequency */
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bool tx_setFreq(double freq, double *actual_freq);
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/** Set the receiver frequency */
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bool rx_setFreq(double freq, double *actual_freq);
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public:
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/** Object constructor */
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@ -97,16 +97,9 @@ signalVector *RadioInterface::unUSRPifyVector(short *shortVector, int numSamples
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signalVector::iterator itr = newVector->begin();
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short *shortItr = shortVector;
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// need to flip I and Q from USRP
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#ifndef SWLOOPBACK
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#define FLIP_IQ 1
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#else
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#define FLIP_IQ 0
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#endif
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while (itr < newVector->end()) {
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*itr++ = Complex<float>(usrp_to_host_short(*(shortItr+FLIP_IQ)),
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usrp_to_host_short(*(shortItr+1-FLIP_IQ)));
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*itr++ = Complex<float>(usrp_to_host_short(*(shortItr)),
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usrp_to_host_short(*(shortItr+1)));
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//LOG(DEEPDEBUG) << (*(itr-1));
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shortItr += 2;
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}
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