65 lines
1.3 KiB
Plaintext
65 lines
1.3 KiB
Plaintext
# SDRAM initialization script for the AT91SAM9RL
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#------------------------------------------------
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# Configure master clock
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echo Configuring the master clock...\n
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# Enable main oscillator
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set *0xFFFFFC20 = 0x00004001
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while ((*0xFFFFFC68 & 0x1) == 0)
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end
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# Set PLL to 200MHz
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set *0xFFFFFC28 = 0x2031BF03
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while ((*0xFFFFFC68 & 0x2) == 0)
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end
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# Select prescaler
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set *0xFFFFFC30 = 0x00000100
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while ((*0xFFFFFC68 & 0x8) == 0)
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end
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# Select master clock
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set *0xFFFFFC30 = 0x00000102
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while ((*0xFFFFFC68 & 0x8) == 0)
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end
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echo Master clock ok.\n
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echo Configuring the SDRAM controller...\n
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# Enable EBI chip select for the SDRAM
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set *0xFFFFEF20 = 0x2
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# SDRAM configuration
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set *0xFFFFEA08 = 0x85227259
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set *0xFFFFEA00 = 0x1
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x2
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x4
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x3
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set *0x20000000 = 0
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set *0xFFFFEA00 = 0x0
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set *0x20000000 = 0
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set *0xFFFFEA04 = 0x2BC
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echo SDRAM configuration ok.\n |