207 lines
7.2 KiB
ArmAsm
207 lines
7.2 KiB
ArmAsm
; * ----------------------------------------------------------------------------
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; * ATMEL Microcontroller Software Support
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; * ----------------------------------------------------------------------------
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; * Copyright (c) 2008, Atmel Corporation
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; *
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; * All rights reserved.
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; *
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; * Redistribution and use in source and binary forms, with or without
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; * modification, are permitted provided that the following conditions are met:
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; *
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; * - Redistributions of source code must retain the above copyright notice,
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; * this list of conditions and the disclaimer below.
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; *
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; * Atmel's name may not be used to endorse or promote products derived from
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; * this software without specific prior written permission.
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; *
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; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; * ----------------------------------------------------------------------------
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; KEIL startup file for AT91SAMCAP9 microcontrollers.
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; ------------------------------------------------------------------------------
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; Definitions
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; ------------------------------------------------------------------------------
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; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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ARM_MODE_USR EQU 0x10
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ARM_MODE_FIQ EQU 0x11
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ARM_MODE_IRQ EQU 0x12
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ARM_MODE_SVC EQU 0x13
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ARM_MODE_ABT EQU 0x17
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ARM_MODE_UND EQU 0x1B
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ARM_MODE_SYS EQU 0x1F
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I_BIT EQU 0x80 ; when I bit is set, IRQ is disabled
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F_BIT EQU 0x40 ; when F bit is set, FIQ is disabled
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AT91C_BASE_AIC EQU 0xFFFFF000
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AIC_IVR EQU 0x100
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AIC_EOICR EQU 0x130
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UND_Stack_Size EQU 0x00000000
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SVC_Stack_Size EQU 0x00000100
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ABT_Stack_Size EQU 0x00000000
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FIQ_Stack_Size EQU 0x00000000
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IRQ_Stack_Size EQU 0x00000080
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USR_Stack_Size EQU 0x00000400
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PRESERVE8
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; Area Definition and Entry Point
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; Startup Code must be linked first at Address at which it expects to run.
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AREA VECTOR, CODE
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ARM
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; Exception Vectors
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Vectors
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LDR pc,=resetHandler
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undefVector
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b undefVector ; Undefined instruction
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swiVector
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b swiVector ; Software interrupt
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prefetchAbortVector
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b prefetchAbortVector ; Prefetch abort
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dataAbortVector
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b dataAbortVector ; Data abort
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reservedVector
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b reservedVector ; Reserved for future use
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irqVector
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b irqHandler ; Interrupt
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fiqVector
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; Fast interrupt
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;------------------------------------------------------------------------------
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; Handles a fast interrupt request by branching to the address defined in the
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; AIC.
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;------------------------------------------------------------------------------
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fiqHandler
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b fiqHandler
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;------------------------------------------------------------------------------
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; Handles incoming interrupt requests by branching to the corresponding
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; handler, as defined in the AIC. Supports interrupt nesting.
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;------------------------------------------------------------------------------
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irqHandler
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; Save interrupt context on the stack to allow nesting */
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SUB lr, lr, #4
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STMFD sp!, {lr}
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MRS lr, SPSR
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STMFD sp!, {r0,r1,lr}
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; Write in the IVR to support Protect Mode */
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LDR lr, =AT91C_BASE_AIC
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LDR r0, [r14, #AIC_IVR]
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STR lr, [r14, #AIC_IVR]
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; Branch to interrupt handler in Supervisor mode */
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MSR CPSR_c, #ARM_MODE_SVC
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STMFD sp!, {r1-r4, r12, lr}
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MOV lr, pc
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BX r0
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LDMIA sp!, {r1-r4, r12, lr}
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MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
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; Acknowledge interrupt */
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LDR lr, =AT91C_BASE_AIC
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STR lr, [r14, #AIC_EOICR]
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; Restore interrupt context and branch back to calling code
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LDMIA sp!, {r0,r1,lr}
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MSR SPSR_cxsf, lr
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LDMIA sp!, {pc}^
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;------------------------------------------------------------------------------
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; After a reset, execution starts here, the mode is ARM, supervisor
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; with interrupts disabled.
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; Initializes the chip and branches to the main() function.
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;------------------------------------------------------------------------------
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AREA cstartup, CODE
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ENTRY ; Entry point for the application
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; Reset Handler
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EXPORT resetHandler
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IMPORT |Image$$Fixed_region$$Limit|
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IMPORT |Image$$Relocate_region$$Base|
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IMPORT |Image$$Relocate_region$$ZI$$Base|
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IMPORT |Image$$Relocate_region$$ZI$$Limit|
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IMPORT |Image$$ARM_LIB_STACK$$Base|
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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; Perform low-level initialization of the chip using LowLevelInit()
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IMPORT LowLevelInit
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resetHandler
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; Set pc to actual code location (i.e. not in remap zone)
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LDR pc, =label
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label
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; Set up temporary stack (Top of the SRAM)
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LDR r0, = |Image$$ARM_LIB_STACK$$ZI$$Limit|
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MOV sp, r0
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; Call Low level init
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LDR r0, =LowLevelInit
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MOV lr, pc
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BX r0
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;Initialize the Relocate_region segment
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LDR r0, = |Image$$Fixed_region$$Limit|
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LDR r1, = |Image$$Relocate_region$$Base|
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LDR r3, = |Image$$Relocate_region$$ZI$$Base|
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CMP r0, r1
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BEQ %1
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; Copy init data
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0 CMP r1, r3
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LDRCC r2, [r0], #4
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STRCC r2, [r1], #4
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BCC %0
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1 LDR r1, =|Image$$Relocate_region$$ZI$$Limit|
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MOV r2, #0
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2 CMP r3, r1
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STRCC r2, [r3], #4
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BCC %2
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; Setup Stack for each mode
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LDR R0, = |Image$$ARM_LIB_STACK$$ZI$$Limit|
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; Enter IRQ Mode and set its Stack Pointer
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MSR CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
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MOV SP, R0
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SUB R4, SP, #IRQ_Stack_Size
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; Supervisor mode (interrupts enabled)
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MSR CPSR_c, #ARM_MODE_SVC | F_BIT
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MOV SP, R4
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; Enter the C code
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IMPORT __main
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LDR R0, =__main
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BX R0
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loop4
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B loop4
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END
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