153 lines
7.6 KiB
C
153 lines
7.6 KiB
C
/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support
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* ----------------------------------------------------------------------------
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* Copyright (c) 2008, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef FPGA_INIT_H
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#define FPGA_INIT_H
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//------------------------------------------------------------------------------
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// Definitions
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//------------------------------------------------------------------------------
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// PAD configuration //////////////////////////////////////////////////////////
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#define MPIO_LP LOWPOWER_ON
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/*
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#ifdef MPIO18
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#define MPIO_SUPPLY SUPPLY_18
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#else
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#define MPIO_SUPPLY SUPPLY_33
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#endif
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*/
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#define MPIO_SUPPLY SUPPLY_33
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//////////////////////////////////////////////////////////////////////
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// CAP9 Part identification //////////////////////////////////////////
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#define EXTENDED_CHIP_ID_REG *((volatile unsigned int*)0xFFFFEE44)
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#define NOT_A_DEV_CHIP_ERROR 0xCACAB0F0
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#define CAP9_CHECK_REVISION_REG *((volatile unsigned int*)0xFFFFFCFC)
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#define REV_C_CHECK_VALUE 0x00000601
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#define REV_B_CHECK_VALUE 0x00000399
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#define NEW_IF 0
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#define OLD_IF 1
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//////////////////////////////////////////////////////////////////////
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#define RSTC_SR_REG *((volatile unsigned int*)0xFFFFFD04)
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#define POWER_ON_TEMPO 0x00FFFFFF
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#define __FPGA_IF_TYPE_DIV5
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// #define __FPGA_IF_TYPE_DIV3
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#define CLK_OUT_DELAY_MIN 28
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#define CLK_OUT_DELAY_MAX 50
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#define FPGA_SYNCHRO_TIMEOUT1 180 // max iteration number for first clk_out_delay match value research
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#define FPGA_SYNCHRO_TIMEOUT2 180 // max iteration number for last clk_out_delay match value research
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#define FPGA_SYNCHRO_TIMEOUT3 10 // max iteration number for cycle index match value
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#define FPGA_SYNCHRO_ERROR1 0xCACAB0F1 // timeout occured for first clk_out_delay match value research
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#define FPGA_SYNCHRO_ERROR2 0xCACAB0F2 // timeout occured for last clk_out_delay match value research
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#define FPGA_SYNCHRO_ERROR3 0xCACAB0F3 // timeout occured for cycle index match value
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// CAP9 MP Block user interface registers /////////////////////////////////////
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#define MPBLOCK_USER_INTERFACE_BASE_ADDR (char*)0xFDF00000
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#define INIT_CMD_REG_OFFSET 0x00
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#define INIT_ARG_REG_OFFSET 0x04
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#define FPGA_IF_TYPE_REG_OFFSET 0x08
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#define CYCLE_IDX_RESP_R_LSB_REG_OFFSET 0x10
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#define CYCLE_IDX_RESP_R_MSB_REG_OFFSET 0x14
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#define CYCLE_IDX_RESP_F_LSB_REG_OFFSET 0x18
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#define CYCLE_IDX_RESP_F_MSB_REG_OFFSET 0x1C
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#define DELAY_CTRL_REG_OFFSET 0x20
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#define DELAY_STATUS_REG_OFFSET 0x24
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#define CONFIG_INIT_REG_OFFSET 0x28
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#define LOCK_IPS_KEY1_REG_OFFSET 0x30
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#define LOCK_IPS_KEY2_REG_OFFSET 0x34
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#define LOCK_IPS_KEY3_REG_OFFSET 0x38
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#define LOCK_IPS_KEY4_REG_OFFSET 0x3C
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#define UNLOCK_IPS_REG_OFFSET 0x40
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#define INIT_CMD_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+INIT_CMD_REG_OFFSET))
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#define INIT_ARG_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+INIT_ARG_REG_OFFSET))
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#define FPGA_IF_TYPE_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+FPGA_IF_TYPE_REG_OFFSET))
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#define CYCLE_IDX_RESP_R_LSB_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+CYCLE_IDX_RESP_R_LSB_REG_OFFSET))
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#define CYCLE_IDX_RESP_R_MSB_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+CYCLE_IDX_RESP_R_MSB_REG_OFFSET))
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#define CYCLE_IDX_RESP_F_LSB_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+CYCLE_IDX_RESP_F_LSB_REG_OFFSET))
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#define CYCLE_IDX_RESP_F_MSB_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+CYCLE_IDX_RESP_F_MSB_REG_OFFSET))
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#define DELAY_CTRL_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+DELAY_CTRL_REG_OFFSET))
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#define DELAY_STATUS_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+DELAY_STATUS_REG_OFFSET))
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#define CONFIG_INIT_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+CONFIG_INIT_REG_OFFSET))
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#define LOCK_IPS_KEY1_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+LOCK_IPS_KEY1_REG_OFFSET))
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#define LOCK_IPS_KEY2_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+LOCK_IPS_KEY2_REG_OFFSET))
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#define LOCK_IPS_KEY3_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+LOCK_IPS_KEY3_REG_OFFSET))
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#define LOCK_IPS_KEY4_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+LOCK_IPS_KEY4_REG_OFFSET))
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#define UNLOCK_IPS_REG *((volatile unsigned int*)(MPBLOCK_USER_INTERFACE_BASE_ADDR+UNLOCK_IPS_REG_OFFSET))
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///////////////////////////////////////////////////////////////////////////////
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// CAP9 chip configuration user interface /////////////////////////////////////
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#define CCF_INTERFACE_BASE_ADDR (char*)0xFFFFEA00
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#define MPBS0_SFR_OFFSET 0x0114
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#define MPBS1_SFR_OFFSET 0x011C
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#define EBI_CSA_OFFSET 0x0120
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#define MPBS2_SFR_OFFSET 0x012C
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#define MPBS3_SFR_OFFSET 0x0130
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#define MPBS_ENABLE_BIT 0x80000000
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#define MPIOB_PUN_BIT 0x04000000
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#define MPIOB_LP_BIT 0x02000000
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#define MPIOB_SUP_BIT 0x01000000
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#define MPIOA_PUN_BIT 0x00040000
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#define MPIOA_LP_BIT 0x00020000
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#define MPIOA_SUP_BIT 0x00010000
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#define MPBS0_SFR_REG *((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS0_SFR_OFFSET))
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#define MPBS1_SFR_REG *((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS1_SFR_OFFSET))
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#define EBI_CSA_REG *((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+EBI_CSA_OFFSET))
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#define MPBS2_SFR_REG *((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS2_SFR_OFFSET))
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#define MPBS3_SFR_REG *((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS3_SFR_OFFSET))
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#define MPBS0 ((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS0_SFR_OFFSET))
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#define MPBS1 ((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS1_SFR_OFFSET))
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#define MPBS2 ((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS2_SFR_OFFSET))
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#define MPBS3 ((volatile unsigned int*)(CCF_INTERFACE_BASE_ADDR+MPBS3_SFR_OFFSET))
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#define PULLUP_ON 1
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#define PULLUP_OFF 2
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#define LOWPOWER_ON 3
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#define LOWPOWER_OFF 4
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#define SUPPLY_33 33
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#define SUPPLY_18 18
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///////////////////////////////////////////////////////////////////////////////
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//------------------------------------------------------------------------------
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// Exported functions
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//------------------------------------------------------------------------------
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extern unsigned int BOARD_InitMPBlock(unsigned char mode);
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#endif // FPGA_INIT_H
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