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initial checkin of 4.5.0 from gpon_optic_drv-4.5.0.tar.gz 

https://github.com/kbridgers/VOLTE4GFAX/raw/master/dl/gpon_optic_drv-4.5.0.tar.gz
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Harald Welte 2022-12-23 09:04:58 +01:00
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GPON Optic Driver, NEXT VERSION
v4.5.0 2013.03.08
- GPONSW-1078: Unstable RSSI Mesasurement Results
+ add an additional average on top of the one shot 10 measurements
- GPONSW-1063: Disable P1_Delta and P0/P1 gain calibration by default
+ fixed issues with disabled gain calibration
- GPONSW-1035: Tx disturber sent during initial optic mode switch
v4.4.1 2012.12.12
- GPONSW-1019: Before a reboot, the 1.0 V DC/DC coefficients are set to their hardware
default values.
- GPONSW-1031: Debug feature BOSA TX and RX enable was not working.
Fixed for FALC-ON V1.3 only
- GPONSW-1042: Laser Tx needs to be safely shut off in state O7 (also if BERT is enabled)
+ switch on after leaving O7 (any state)
+ BERT activation no longer switches the laser on
+ Adapted status functions to report the correct tx_enable state (two conditions are now evaluated)
v4.4.0 2012.11.20
- GPONSW-1011: Avoid range check for first collected internal temperature values to
ensure valid measurement results
- GPONSW-998: automatic power levelling based on RSSI
+ With the new RSSI_autoleveling feature the internal power level is automatically
switched from PL0 to PL1 if a certain upper RSSI threshold power is exceeded,
and it is switched back to PL0 values, if the measured RSSI power is lower than
a lower RSSI threshold power.
- GPONSW-1004: Support of defined biasing below laser threshold in case of low attenuation
+ In case of low attenuation, P0 detection of OLT transceiver is critical.
The lower the P0 value the better, some Transceivers do not have Rx Power Squelch
and are more susceptible to high P0 levels than others.
+ On the other hand, the additional Jitter with modulating below threshold would be not
beneficial for high attenuation, since with high attenuation the detection is
noise limited.
+ It is recommended to use this additional Feature especially together with (automatic) Power Leveling
to increase the overall dynamic range.
- GPONSW-829: fixed APD breakdown voltage calibration reports inaccurate
voltage with low probability
+ Updated APD regulation algrithm
- GPONSW-961, GPONSW-899: Improve eye diagram symmetry for FALC-ON V1.3
- GPONSW-927: 'BIASLOWSAT_CTRL' is dependent on actual temperature now
- GPONSW-924: LDD Power Save truncates end of burst in extended burst length mode against ALU OLT
- GPONSW-910: bias and drive DAC currents for A22 corrected
- GPONSW-908: Selflearning can be disabled via goi_config parameter
+ In case of a learning threshold configured to be higher than the reset threshold,
the optic driver disables self-learning
- GPONSW-898: enable tx path before BERT activation if not already enabled
- GPONSW-868: Provide a function that can enable/disable the transmission
+ independent of which OMU/BOSA mode is selected
- GPONSW-747: RSSI1490 parabolic correction
v4.3.0 2012.08.10
- GPONSW-833: Introduce selection for extended serial number (SN) response
v4.2.0 2012.07.30
- Preparation for FALC-ON v1.3
- GPONSW-747: prepared RSSI1490 parabolic correction
- GPONSW-778: corrected inconsistent polarity of the modulation and bias current
on startup using now the goi_config values and on bert enable/disable
- GPONSW-777: wrong scale for modulation current with A21
- GPONSW-795: FCSI settings for A21 must be corrected
- GPONSW-802: Offset current for A2x Laserdriver
- GPONSW-805: RSSI power value wrong after boot up
- GPONSW-791: wrong sign of 'Dref0_PL0' in 'otop',
also applied for Dref_PL1 and monitor settings
v4.1.1 2012.06.22
- APD DCDC is always reliable at 40V
- GPONSW-755: [BBF] Reboot during test
v4.1.0 2012.06.15
- GPONSW-686: Calculation of dark current compensation and leakage currents
in RSSI 1490 differential mode
- Code cleanup done
v4.0.4 2012.06.04
- corrected APD DCDC voltage status if DCDC is disabled
- moved FCSI settings from goi_config to internal constants now
- fixed wrong P1 offset
- prepared driver for using pmos, nmos settings for DCDC
configuration but not yet activated
- added bosa_int_coeff_get to optic API and CLI
- fixed Rogue ONU intraburst alarm
- deactivated accurate RSSI measurement since its affecting temperature measurement
- temperature measurement more stable now
v4.0.3 2012.05.08
- Added debug feature for measurement polling interval configuration
goi_mm_interval_cfg_set
- GPONSW-635: Keep voice pll untouched an leave it up to the voice driver if any
- Corrected sign of RSSI1490 single ended measurement
- Fixed sign handling of RSSI1490 differential measurement
- LOS and OVL interrupt/status indication (otop and optic function)
- corrected MPD dark current reporting in uA now
v4.0.2 2012.04.27
- FIO_CAL_ACT_BIAS_CURRENT_GET / FIO_CAL_ACT_MOD_CURRENT_GET returns current = 0
in case of deactivated DCDC APD
- several bias/mod init cycles in routine dualloop before regulation process
to avoid "reset" bias/mod
- power save feature doesn't touch MPD gain_ctrl register
- optic_ll_mpd_level_search() -> optic_mpd_level_search() to cover level search
environment modulary
- DCDC Core voltage calculation optic_ll_dcdc_core_voltage_get() bugfix
(+ 0,0117 V)
- MPD level search starts in INTRABURST in case of active BERT
- dual loop internal setting is reset for optic mode change and reset
- differential RSSI 1490 measurement: special LOS/OVL threshold handling for
A12 and A21
- Plugging/Unplugging fiber sync problem fixed
- more weight to coarse DAC in level search
- repeatability of level search improved
- repeatability and accuracy of RX offset search improved
- gain correction is done only if offset correction is enabled
Note that a gain correction relies on the calibration current (100uA) for the
chosen power level.
i.e. gain correction is not done with calmlf 1 0 0 or calmlf 0 1 1.
- GPON-SW 548 fixed:
driver init not working: Start currents are not correctly
initialized after "ocalodi"
- Changed FIO_GOI_STATUS_GET to represent the main status, created new FIO_GOI_EXT_STATUS_GET
for extended statistics
- Removed unused hot plug event for state change per compile switch OPTIC_STATE_HOTPLUG_EVENT
v4.0.1 2012.02.29
- RSSI1490 current measurement uses absolute values of (current-offset)
- fine current values enhanced by parameter is_positive
- measurement frequency for mm calibration increased upto 20ms,
only 20 measurement values are collected for first average
- fix DEVIO _IOC defines
- dual loop calls offset_cancellation even without level search for correction
factor recalculation
- goi_config: TempMonitorThreshold_MPDcorrection changed to 3 K
- dual loop regulation "update criteria": average even measured in no-update
case, because counter forced "update" (to avoid long passive phases) will use
this average to check against reset threshold
- "--enable-remote-only-onu" configuration option added
- MPD calibration review, feature activated
- optc_control bugfix: cli command "optic" without parameter handled as
"optic help"
- TX Fifo size set to maximum in goi_config -> 508 bits
- dual loop learning cleanup (+ table update for each learned Ith/SE value)
- MM gain factor calibration bugfix (+activation: OPTIC_MM_GAIN_CORRECTION)
v4.0.0 2012.02.14
- cleanup in dual loop: reset of bias/mod for crossing reset threshold
- range check delay_tx_disable for A11, A12: delay_tx_disable cannot be < 28
- rx dac offset filter alligned with mpd level search filter
- goi_status_get() doesn't communicate via packed-structure-elements parameter
directly
- FIO_CAL_CURRENT_OFFSET_GET IOCTL introduced + otop update
- powersave mode without BFD P0/P1 POWERSAVE_EN bit setting
(and active by default)
- RX offset manipulation supported by IOCTLs FIO_CAL_RX_OFFSET_SET/GET/FIND
- current_state introduced to simplify state get procedure
(buffer[index_buffer])
- DCDC APD update cleanup (no saturation update if VAPD wasn't updated)
- software reset clears mpd settings
- bugfix RSSI 1490 exclussive measurement (+timeout handling enhanced)
- TX data delay configured by default with 2
- dying gasp reaction: dcdc apd disabled
- goi_config: laser_enable_delay changed into 8 bits
- FCSI predriver check enabled, formula changed - max voltage = 2V
- goi_config: BD_loadn = BD_loadp = 0x1F, BD_bias_en = 0xF, BD_cm_load = 0x3
- P0/P1 level measurement sign regulation enhanced - coarse and fine dac never
use different signs
- P1 delta offset substraction not active in offset cancellation
- MPD saturation of fine level triggers coarse level adaptation
- Dual loop cleanup (stable criteria uses old and new averages)
- MPD level search doens't invert gain direction in case of active BERT
- MPD Offset cancellation started (and never changed) in INTRABURST mode,
if BERT us active (inactive BERT: INTERBURST and switch into INTRABURST,
if comperator doesn't react)
- MPD offset cancellation cleanup
- DCDC Core cleanup: CONF_TEST_ANA/DIG instead of CONF_TEST_ANA/DIG_NOAUTO used
- Dual loop updates Ibias/Imod for the very first entry (regular temperature)
- Dual loop update and stable criteria cleanup
v3.0.17 2011.12.20
- "--with-procfs" configuration option added
- FIO_BERT_CNT_RESET introduced to reset bert counters
- compile switch OPTIC_DYING_GASP_SHUTDOWN introduced, disables DCDC APD
- Fix state deadlock and fixed locked interrupt in repeating calibration
and thus fixed for kernel warning on /etc/optic/goi_config.sh config_all.
- BERT synchronize was always setting the sync bit but never toggled back.
Now corrected to just toggle the bit shortly
- hotplug table request deleted, state machine logic moved into worker thread
- optic_powerlevel_set/get() introduced and exported for calling
optic_bosa_powerlevel_set/get() with first device context
- optic_table_set differs between laserref_table update and init phase
- VAPD and saturation value are initialized for DCDC APD
(refering to configured temp_ref)
- DCDC APD PWM0 register init value changed from 0xFF into 0xF9, configuring
switching frequency to 250MHz/250 = 1MHz
- FIO_OPTIC_RECONFIG introduced to reset configs and tables and wait for updates
- Measurement: additional 300uA via FCSI is not working for A11, A12
v3.0.16 2011.12.06
- DCDC APD voltage_error -> regulation_error
SW ramp waits until regulation error is below 1V
- rework goi_init to optimize for boot up speed, fixes multiple hotplug
calls to it resulting in instable link on start-up
v3.0.15 2011.12.06
- avoid power measurement, MPD regulation and DC/DC APD Update in case of
initially not available temperature
- Speed up the temperature measurement by factor 10 if it is not yet available
- fix wrong voltage offset in RSSI 1490 measurement using command
cal_measure_rssi_1490_get for ocal (500 mV -> 0 V)
- update stable criteria in dual loop: cint dependent hardware checks have been
done before stable criteria can be measured
- bugfix new fusing format gaindrivedac interpretation
(STATUS_ANALOG_NEW_GAINDRIVEDAC_MASK definition)
- configuration BFD_SATURATION with bias_max and mod_max (codeword format)
- OPTIC_FLOAT2INTSHIFT_CURRENT changed 9 -> 8
- FIO_CAL_TSCALREF_SET/GET introduced
- coarse level find reduction by 5 (instead of 9) -> fine level ~100
(former ~180, sometimes ran into SATURATION)
- reset internal rogue detection to make the rogue alarms working. The config
can select between interburt, intraburst or both alarms, per default switched
off. If an alarm occurs the laser is switched off immediately
- remove annoying signal detect and los interrupt prints and make counters
available via procfs: cat /proc/driver/optic/status
- removed configuration of rogue detection thresholds and
introduced overcurrent thresholds in range configuration
v3.0.14 2011.11.22
- Die temperature formula used signed variables which lead to wrong
calculation of higher temperatures. Changed now to unsigned integers.
- Dual loop parameters changed (capture width=5, delay=4)
- activate offset cancelation for dual loop for temperature jumps
- Allow active BERT for MPD level search on P0
- Optimized MPD level find function with filter
v3.0.13 2011.11.12
- fix for dual loop parameter TX_DELAY to 6
- added configuration of rogue detection thresholds (rogue_bias_thr and
rogue_mod_thr)
- added configure support for the debug tool event logger
- set chip dependend settings of max bias and and max modulation current
to 78 mA and 130 mA respectively
- reactivate bert self_sync by reset and set the bit again
v3.0.12 2011.11.10
- new dual loop configuration
v3.0.11 2011.10.28
- general ll cleanup (only direct register access located in optic_ll_~ files)
- ll functions p_ctrl cleanup: ll_mm, ll_mpd
- bugfix temperature calculation/measurement
- bugfix bias calculation: register -> current bias, bias_max used for scaling
- bugfix signed integer printout (otop)
- bugfix dual loop learning criteria (only if c_int is increased and
learn threshold exceeded)
GPON Optic Driver, version 3.0.10, 2011.10.21
--------------------------------------------
- while offset cancellation, az_delay set temporarly to 3
- bugfix goi_status_get(): return code independent of PLL status
- startup cleanup for config/table free booting
- FIO_MM_1490_OPTICAL_POWER_GET introduced
- bugfix Offset Cancellation: P1 delta calibration uses level-search without
internal P1 delta offset subtraction (of old P1 delta value)
- ll functions p_ctrl cleanup: ll_fcsi, ll_tx, ll_rx, ll_gpio, ll_dcdc_apd,
ll_dcdc_core, ll_dcdc_ddr, ll_status, ll_int
GPON Optic Driver, version 3.0.9, 2011.10.14
--------------------------------------------
- BFD.P0/P1_DUALLOOP init configuration changed (min_bits_p0=11
(goi_config: CID0))
- CDR/CDRLF configuration update (RX)
- bugfix FIO_BERT_MODE_SET cli call (command instead of indication)
- P1 delta offset subtracted from level directly (optic_ll_mpd_dac_cal()) and
added to P1 codeword in register writing (optic_ll_mpd_codeword_set())
no P1 delta influence in codeword calculation anymore ..
- bugfix in P1 delta offset correction (optic_ll_mpd_codeword_set(): delta sign)
- new BOSA Interrupt concept: recogniced interrupts switch corresponding
internal interrupt status flag on and disable irq; re-enable, if IRNICR is
set while internal interrupt status flag is off
- FIO_BOSA_ALARM_STATUS_GET, FIO_BOSA_ALARM_STATUS_CLEAR implemented
- otop page for BOSA interrupts/alarms: "a"
- DAC1550 support: FIO_GOI_VIDEO_ENABLE/DISABLE/STATUS_GET,
FIO_GOI_VIDEO_CFG_SET/GET; access to FCSI VDAC
- powersave mode configured at end of bosa_init
GPON Optic Driver, version 3.0.8, 2011.10.07
--------------------------------------------
- TX.DATA_DELAY.EN_PMD_TX_PD initialized (no powerdown mode)
in optic_ll_tx_init()
- BFD.P0/P1_DUALLOOP init configuration changed (alarm=0x20, min_az=15,
min_det_bits=3, min_bits=8 (goi_config: CID), capture_width=3,
capture_delay=2, az_delay=0, ib_check=0)
- TX.DATA_DELAY init configuration update (data_delay=2, intrinsic_delay=0)
- switch between different CID settings (for calibration, Interburst,
Intraburst, dual loop) isn't necessary anymore and was skipped in
optic_ll_mpd_loop_set()
- comfort function for easy bert configuration: FIO_BERT_MODE_SET
- FIO_CAL_DEBUG_ENABLE/DISABLE updates TIA offset (powerlevel dependent or
debug specific values)
- goi_config enhanced by Polarity_Rx, Polarity_Bias, Polarity_Mod
struct optic_goi_cfg enhanced by rx_polarity_regular, bias_polarity_regular,
mod_polarity_regular, influence RX.DATA_LO.DATA_LO_INVERSE,
RX.DATA_HI.DATA_LO_INVERSE, RX.MONITOR.MONITOR_INVERSE,
TX.DATAPATH.DATA_INV, TX.BIASPATH.BIAS_INV + otop, control application update
- otop enhanced by MPD gain correction factor
- fusing interpretation update: offset in 2-complement
- Copyright 2011 update
GPON Optic Driver, version 3.0.7, 2011.09.30
--------------------------------------------
- update init configuration of BFD.P0_DUAL_LOOP, BFD.P1_DUAL_LOOP to reduce
offset/gain calibration differences between inter/intraburst
- rx offset correction only at first BOSA activation, added to otop
- special MPD Offset cancellation configuration deactivated
- Rogue ONT support (Rogue ONT irq disabled during MPD offset cancellation)
- optic_ll_mpd_gainctrl_set()/optic_ll_mpd_tia_offset_set() cleanup:
powerlevel <-> gainbank
GPON Optic Driver, version 3.0.6, 2011.09.23
--------------------------------------------
- new fuse concept supported (detection and interpretation change)
changes for tempmm, gaindrivedac, gainbiasdac, tbgp
offset/gainddrdcdc not fused anymore but instead offset/gain1v0dcdc
- DCDC core voltage setting/calculation with fusing information
- bugfix in DCDC DDR voltage calculation
- bugfix for reading temperature tables with invalid lines (like blanks)
- prepare flexible bias/mod max value (will be detected via fusing flag)
- otop WHAT string added
GPON Optic Driver, version 3.0.5, 2011.09.19
--------------------------------------------
- MPD offset cancellation use special configuration (COMPARE_METHOD=1,
COMPAREPATTERN=0x4, CID_SIZE=4, IB_CHECK=1)
- MPD calibration parameter optimization: gain = "0" for powerlevel 0
- DCDC APD change criteria (>2 digits difference) update
- tia_gain -> tia_gain_selector
- rssi_1550_scal_ref,rf_1550_scal_ref added to struct optic_mm_config and
struct optic_config_measurement + configuration transfer, otop enhancement
- meas_power_1550_rssi, meas_power_1550_rf added to struct optic_status and
optic_calibrate, power calculation for RSSI 1550 and RF 1550, otop enhancement
- support of general correction factor tables, used for PTH, MPDresp, RSSI1490,
RSSI1550, RF1550 tables,
FIO_CAL_MPDCORR_TABLE_SET/GET -> FIO_CAL_CORR_TABLE_SET/GET
- power correction factor tables for RSSI 1490, RSSI 1550 and RF 1550 added
- temperature table name cleanup
GPON Optic Driver, version 3.0.4, 2011.09.01
--------------------------------------------
- FIO_CAL_MPD_LEVEL_FIND enhancement: not requested level (P0/P1) returns
level=-1, COMPERATOR timeout error would be thrown via errorcode
- dual loop stable criteria enhancement: if abias/amod is out of range
(stablethreshold_init) ibias/imod is reset
- RX offset correction introduced (only called at init phase) - only active
in BOSA mode, in OMU mode instead only AFE_CTRL enabled
- Added support for Optic configuration via options (with disabled CLI)
GPON Optic Driver, version 3.0.3, 2011.08.18
--------------------------------------------
- BERT disabled explicitly in bert_init()
- bugfix changing tia offset (FIO_CAL_MPD_TIA_OFFSET_SET,
FIO_CAL_MPD_DBG_TIA_OFFSET_SET)-> update of MPD tia offset level
(not part of MPD level search anymore)
- P1 delta offset subtracted from P1 levels in optic_ll_mpd_dac_cal()
- digital codeword P0 P1 update after dcal/dcal_ref configuration
(FIO_CAL_MPD_DBG_REF_CODEWORD_SET, FIO_CAL_MPD_REF_CODEWORD_SET)
- MPD levels restored after level-search
- calibration current (GAIN_CTRL) is set before and is reset after level-search
(only calibration current! tia gain selector will not be reset)
- offset cancellation workaround: TX.BIASPATH burst = enable, GAIN_CTRL
cal_curent = close (0) - only for tia offset measurement to increase offset
accuracy; P1 delta offset is still measured with TX.BIASPATH burst = disable,
GAIN_CTRL cal_curent = open (1)
GPON Optic Driver, version 3.0.2, 2011.08.05
--------------------------------------------
- bugfix level calculation in cal_mpd_level_find()
- cal_debug_enable doesn't take over tia gain selector and
MPD calibration current anymore
- bugfix FIO_BERT_CFG_SET IOCTL (base) number
- bugfix dual loop, learning (special case: only BIAS or MOD changed)
- bugfix changing MPD calibration current or tia offset selector
(FIO_CAL_MPD_DBG_CAL_CURRENT_SET, FIO_CAL_MPD_CAL_CURRENT_SET,
FIO_CAL_MPD_DBG_GAIN_SET, FIO_CAL_MPD_GAIN_SET) -> update of MPD gain control
register (not part of MPD level search anymore)
- dual loop resets integration coefficients to 0 if regulation gets unstable
- OPTIC_MPD_GAIN_CORRECT, OPTIC_MPD_OFFSET_CANCEL introduced and disabled!
- StableThreshold_Bias / StableThreshold_Mod interpreted in percent
- stablethreshold_init introduced to avoid regulation ="stable" detection
in case of far regulation at lower or upper edge
- bugfix regulation-update criteria
GPON Optic Driver, version 3.0.1, 2011.07.28
--------------------------------------------
- gain control register keeps in powerlevel/debug mode dependent mode
- powersave feature enhanced by TX, MPD.GAIN_CTRL, FCSI#7 configuration
- long term drift (goi_table_laser_ref.csv <-> goi_table_laser_ref_base.csv)
module tested
- bugfix in laser_ref table extrapolation
- control application laser table writing (+ base table) enhanced by
driver (laser table) update - new inter/extrapolation
- bugfix in control application interpolation routine
- bugfix parameter exchange for FIO_CAL_MEASURE_RSSI_1490_GET
GPON Optic Driver, version 3.0.0, 2011.07.07
--------------------------------------------
- range check in optic_ll_dcdc_apd_voltage_get() inactive - no further warnings
about current low DCDC APD voltage
- optic_ll_mpd_cint_set() calculates automatically saturation
- optic_ll_mpd_loop_set() supports loop mode for P0 and P1 separatly
- bugfix DCDC APD init: LATCH_CONTROL_NOAUTO set instead of LATCH_CONTROL
- optic_ll_mpd_level_search() reacts on BERT status for P0 level analysis
- update FCSI init settings (#18)
- measurement calibration (offset, correction factor) bugfix (trigger point)
- external temperature calculation correction (1200mV difference activated)
- proc filesystem enhanced by temperature history file ("temperatures")
- optic_ll_mpd_level_search() enhancement: automatic Intra->Interburst switch
GPON Optic Driver, version 2.0.14, 2011.06.16
--------------------------------------------
- cal_mpd_tia_offset_find() bugfix: loopmode corrected in case of BOSA/
dual loop
- goi_config updated: TxDisableDelay = 28, TxFifoSize = 288 to fix IBL problem
predriver setting for power level 1 and 2 updated (identical to power level 0)
- bugfix cal_mpd_dbg_gain_get(), cal_mpd_dbg_cal_current_get():
don't return powerlevel dependent value if debug version == 0 (valid value!)
- DCDC APD init cleanup (DELAY_DEGLITCH = 0x07)
start with DIG_REF=0 and LATCH_CONTROL_NOAUTO = 0x21
activation of DCDC APD sets CONF_TEST_ANA_NOAUTO 0x78 -> 0x7 and
CONF_TEST_DIG_NOAUTO 0x00 -> 0x03 and LATCH_CONTROL_NOAUTO = 0x01
GPON Optic Driver, version 2.0.13, 2011.06.01
---------------------------------------------
- bugfix cal_mpd_level_get(), level_select was ignored
- FIO_BOSA_INT_COEFF_GET introduced (-> otop, status)
- FIO_BOSA_STABLE_GET introduced (-> otop, status)
- digital codeword P0/P1 moved from otop monitor to otop status
- bugfix in stable criteria for BOSA dual loop abias/amod characterization
- goi_config update
- otop update
GPON Optic Driver, version 2.0.12, 2011.05.30
---------------------------------------------
- BFD.GAIN_CTRL reset after each calculation to zero (in offset cancellation,
coarse/fine-ratio, mpd calibration)
- bosa loop mode (open loop / dual loop) configured via bosa_tx_config
(-> goi_config)
- FIO_BOSA_DUALLOOP_ENABLE/~_DISABLE/~_STATUS_GET deleted and
FIO_BOSA_LOOPMODE_SET/~_GET introduced for bosa loop mode configuration
- optic driver starts per default in OMU mode, loop mode (bosa) configured
per default in open-loop
GPON Optic Driver, version 2.0.11, 2011.05.25
---------------------------------------------
- PLL calibration with power down via RESETCONTROL
- PLL module initialisation update: A_CTRL2, CURR_SEL_DIV2 = 5
- RX module CDR configuration don't touch VCO (CTRL3)
- new predriver settings, FCSI TXBOSA.CTRL = 0x81, TX.PI_CTRL = 0x404F
- FCSI predriver range check disabled temporarly!
- bugfix in optic_ll_fcsi_init, optic_ll_fcsi_init_bosa_2nd():
just "add" TXBOSA_CTRL_FFR
- bugfix in FCSI predriver writing into FCSI registers
(incorrect masking overwrotes setting)
- FCSI register #19 PI_CTRL for OMU and BOSA mode introduced
- DCDC APD deactivated implicitly in OMU mode (former mode change didn't touched
DCDC APD configuration)
- init bias/mod value never set to zero by driver (use 1 instead)
0 is a meta value used by hardware after DAC update
GPON Optic Driver, version 2.0.10, 2011.05.20
---------------------------------------------
- RX.AFECTRL.OUTPUT_CM_SEL initialisation changed into 4
- reload timer for DCDC APD SW ramp reduced downto 10ms
- optic_mpd_config enhanced by ratio_coarse_fine, coarse fine ratio calculation
deactivated (compilerswitch OPTIC_MPD_COARSE_FINE_RATIO_CALC = INACTIVE)
- timestamp hotplug event triggered via worker thread, not directly anymore
- temperature alarms hidden (compilerswitch OPTIC_TEMPERATURE_ALARM = INACTIVE)
- TBGP value of ANALOG fuse register is ignored for FCSI reg 21 writing
(always 0 written into FSCI #21 TBGP field)
GPON Optic Driver, version 2.0.9, 2011.05.13
--------------------------------------------
- new measurement cycle concept: 20ms measurement cycles, no buffer cycle
between reconfiguration of channels and reading measurement values anymore
- external temperature calculation change: no 1200mV difference anymore
- fusing information writing into FCSI register reactivated
- chip version detection (gain recalibration measurement active)
- RSSI 1490 power measurement mode introduced: FIO_CAL_MEASURE_RSSI_1490_GET
configures measurement block, waits for measured values and calculates all
measured values into power values
- klocworks cleanup
- drv_optic_api.h + struct optic_device shifted from include dir (interface)
into driver internal part (src dir)
- optic driver uses hotplug.d/gpon directory for hotplug event handler script
GPON Optic Driver, version 2.0.8, 2011.04.29
--------------------------------------------
- temperature alarms provided via events: event OPTIC_FIFO_ALARM uses enum
optic_irq to describe alarm (OPTIC_IRQ_TEMPALARM_YELLOW_SET,
OPTIC_IRQ_TEMPALARM_YELLOW_CLEAR, OPTIC_IRQ_TEMPALARM_RED_SET,
OPTIC_IRQ_TEMPALARM_RED_CLEAR)
- next measurement cycle after channel configuration does not use read values
- scale factor for translation between Imod <-> Dmod powerlevel dependent
introduced as config parameter: struct optic_mpd_config enhanced
- otop update
GPON Optic Driver, version 2.0.7, 2011.04.15
--------------------------------------------
- MPD initialisation update
- MPD calibration bugfix (P1 coarse/fine ratio calculation takes care, coarse
level could could be zero - fine level relevant for correction direction
- LTC pattern length range check added
- OPTIC_IRQ_TEMPALARM_YELLOW_SET, OPTIC_IRQ_TEMPALARM_YELLOW_CLEAR,
OPTIC_IRQ_TEMPALARM_RED_SET, OPTIC_IRQ_TEMPALARM_RED_CLEAR introduced;
thresholds set via config file, struct optic_goi_config enhanced
- otop update
GPON Optic Driver, version 2.0.6, 2011.04.12
--------------------------------------------
- bugfix interrupt handling in BOSA mode
- change of predifined FCSI bias_en setting to pass plausibility check
- otop cleanup (BOSA2 printout)
- optic_ll_mpd_level_search() update: coarse level correction (-9),
loop starting with gain = +/-10 * 16 and run until gain = 0
- RX data FiFo security: LOS: RX_DATA_EN = 0, SIGDET: RX_DATA_EN = 1
- measurement module: gain correction factor calibration after measurement of
all 6 offsets, means each 7th measurement cycle (instead of each 2nd)
GPON Optic Driver, version 2.0.5, 2011.03.30
--------------------------------------------
- otop enhanced by LDO status
- LTS support: FIO_GOI_LTS_CFG_SET/GET, FIO_GOI_LTS_ENABLE/DISABLE/STATUS_GET
- optic_bert_cfg parameter pattern type change: uint32_t -> uint8_t
- cli_misc (non automatic generated cli layer) introduced:
cli for goi_lts_cfg_set/get, bert_cfg_set/get not automatically generated
GPON Optic Driver, version 2.0.4, 2011.03.24
--------------------------------------------
- DCDC DDR support: dcdc_ddr_cfg_set()/get(), dcdc_ddr_enable()/disable(),
dcdc_ddr_status_get(), cal_ddr_core_voltage_set()/get() implemented
- struct optic_dcdc_ddr_config used, DCDC DDR cinfiguration parameters in
goi_config
- otop update for DCDC DDR parameters (config, range, status)
- FIO_CAL_FUSES_GET introduced for fusing register overview -> otop "f"
- optic_ll_fcsi_predriver_set() range/plausibility check
- struct optic_mpd_config enhanced by parameter powersave, configures
PMA_POWERSAVE_POWER_UP_EN / PMA_POWERSAVE_POWER_UP_OVR
- LDO support: sys1 interface, FIO_LDO_ENABLE, FIO_LDO_DISABLE,
FIO_LDO_STATUS_GET
GPON Optic Driver, version 2.0.3, 2011.03.17
--------------------------------------------
- OPTIC_BOSA_2 mode introduced, using OMU rx pins
- DCDC APD files generalized to support DCDC-APD,-DDR,-CORE interface
- DCDC CORE support: dcdc_core_cfg_set()/get(), dcdc_core_enable()/disable(),
dcdc_core_status_get(), cal_dcdc_core_voltage_set()/get() implemented
- struct optic_range_config enhanced by vcore_min/max and vddr_min/max
- struct optic_dcdc_core_config used, DCDC Core cinfiguration parameters in
goi_config
- otop update for DCDC core parameters (config, range, status)
GPON Optic Driver, version 2.0.2, 2011.03.11
--------------------------------------------
- bugfix reconfiguration LOL, overload tresholds in bosa_rx_config_set():
threshold current/voltage values are (re)calculated in bosa_init()
which have to been started via goi_init() after updating bosa configuration
- general cleanup enabling/disabling interrupts, order of reset, ctrl CONTEXT
initialisation, goi_init to support OMU <-> BOSA mode switches on the fly
- general cleanup in startup/init phase for OMU/BOSA mode and switching between
modes via optic_mode_set()
- bugfix for starting without dedicated mode, later call of optic_mode_set()
GPON Optic Driver, version 2.0.1, 2011.03.07
--------------------------------------------
- BOSA / Int200 interrupts LOS, SD, OVL enable each other
- LOS and Overload thresholds calculated (power->current->voltage->
register value) and updated during temperature measurement cycle
- doublecheck INT200 interrupts (MM.M_RESULT_9 register against MM.ALARM_CFG)
if interrupt was not thrown correctly (sign error in M_RESULT interpretation)
interrupts are disabled until next measurement cycle
- omu_tx_disable()/enable(), omu_rx_disable()/enable(),
bosa_tx_disable()/enable(), bosa_rx_disable()/enable() use PLL.RESETCONTROL.
TX_RSTN and RX_RSTN instead of TX_PD/TXOMU_PD and RX_PD/RXOMU_PD
- measurement thread bugfix: active debug mode avoids ibias/imod update even in
BOSA/open-loop mode
GPON Optic Driver, version 2.0.0, 2011.03.01
--------------------------------------------
- control application updates Laserref temperature table file (~.csv):
original file is read, updates requested from driver, both tables
merged and data are written to new file ("goi_config.sh write_tables")
- otop printout cleanup
- calibration current selector enhanced by OPTIC_CAL_OFF
- optic_ll_tx_fifo_set/get() bugfix (16 bit enable/disable delay and
bit-interpretation); both functions are exported
- OMU/BOSA cleanup shifted to optic_ctrl_reset
GPON Optic Driver, version 1.2.0, 2011.02.25
--------------------------------------------
- ext_att parameter deleted in goi_config, exchanged by r_diff[2]
- rssi_1490_dark_corr parameter added to goi_config for current_offset
calculation
- otop update: printout new config parameters
- FIO_CAL_MM_DARK_CORR_SET, FIO_CAL_MM_DARK_CORR_GET, FIO_CAL_MM_DARK_CORR_FIND
to configure RSSI 1490 dark correction factor
- in BOSA mode (only!) BIASPATH invert bit is not set
- control apllication merges table from csv file with requested updated table
GPON Optic Driver, version 1.1.5, 2011.02.23
--------------------------------------------
- debug mode deactivates DCDC APD and (in openloop mode) IbiasImod Update
- maximum value check in Ibias/Imod calculation
- bugfix Vapd (error) printout in otop
- preparation to detect second call of optic_mode_set -> BOSA/OMU mode switch
- FIO_CAL_LASERREF_TABLE_SET, FIO_CAL_LASERREF_TABLE_GET to set/get Ith/SE
table values directly. Ibias/Imod values are updated automatically
- bugfix otop printout Ith/SE
- RSSI1490 power measurement/calculation: single ended & differential
- goi_config enhanced by parameter to define RSSI 1490 measurement method
GPON Optic Driver, version 1.1.4, 2011.02.17
--------------------------------------------
- cleanup voltage measurement
- bugfix in otop RSSI 1490 voltage/current printout
- bugfix in parameter cleaning for mm_cfg_get()
- BERT cleanup: bert_enable()
- add p0, p1, pth to struct goi_config for Ibias/Imod table calculation
- bugfix cal_dcdc_apd_voltage_set()
- 2.nd call of fcsi (bosa) init in BOSA mode (workaround for A1.1)
- Ibias/Imod calculation in driver (laserref + pth table transfered)
- otop cleanup: e.g. temperature tables, status shows precalc. ibias/imod
- bugfix in cal_*_table_get() functions: clearing param_out deletes param_in
GPON Optic Driver, version 1.1.3, 2011.02.11
--------------------------------------------
- optic_isr_register() supports undefined p_ctrl handle
(called by other kernel moduls) -> isr registered for all control instances
- FIO_CAL_LASERDELAY_SET/FIO_CAL_LASERDELAY_GET for laser bit delay
configuration, cal_laserdelay_set()/cal_laserdelay_get() are exported
- optic_ll_bert_prbs_set() accepts all prbs selections
- TX.DATAPATH.BERT and TX.BIASPATH.BERT set via bert_enable()/bert_disable()
- cli register get "optic opticrg" returns hex values
- power measurements shiftet from dual loop routine to general measurement
cycle (if BOSA mode is active)
- open loop mode: only ibias/imod update is done regarding to ext. temperature
- slope efficiency added to ibias/imod table, read back via
FIO_BOSA_TX_STATUS_GET for calculating tx power
GPON Optic Driver, version 1.1.2, 2011.02.08
--------------------------------------------
- requesting/freeing irqs a second time (optic_irq_set()) is ignored
- thread bugfix: reaction on pending signals
- bert counter reset in bert_enable()
- TX/DATAPATH and TX/BIASPATH configuration in bert_enable() and bert_disable()
(back to OMU or BOSA configuration)
- FIO_CAL_MM_ENABLE/FIO_CAL_MM_DISABLE to stop/restart measurement background
cycle (only active, if OPTIC_MM_MEASUREMENT_LOOP is activated)
- optic_config_omu struct enhanced by element laser_enable_single_ended
to define PLL.TOPCTRL.EXT_LASER_EN setting, read via config file
- FIO_OPTIC_ISR_REGISTER for registering ISR callback,
function optic_isr_register() is exported
GPON Optic Driver, version 1.1.1, 2011.01.28
--------------------------------------------
- GPIO signal detect -> interrupt (OMU mode)
- OMU signal detect / loss of signal GPIO interrupt sets/releases CDR3 BPD bit
- compiler switch/define OPTIC_DEBUG works as main switch for all debug defines
- ignore BGP fusing information (at the moment!): FCSI.CBIAS.CTRL1 is not
updated with fusing information, read from STATUS.ANALOG
- bugfix in automatic gain selection (optic_ll_mm_voltage_get())
- FCSI writing checks via read and write second time, if needed
- TX DATPATH, BIASPATH: DATA_PRG_EN not set (disturbs PLOAM state 5)
GPON Optic Driver, version 1.1.0, 2011.01.25
--------------------------------------------
- mpd level searching cleanup: mpd cancellation and coarse/fine ratio working
- fusing information handled
- measurement rework: new p/n junction concept,
initialisation of all measurement types, periodic measurement of 3x offsets,
3 voltages for internal temperature, 1 voltage for external temperature and 3
voltages for power measurement
- bugfix optic_float2int()
- VAPD start value configured via FIO_DCDC_APD_CFG_SET
GPON Optic Driver, version 1.0.10, 2011.01.21
---------------------------------------------
- enum optic_edable -> enum optic_activation
- bosa initialisation cleanup
- ioctl table check taken over from onu driver
- "OMU" / "BOSA" mode printout
- mpd offset cancellation bringup
GPON Optic Driver, version 1.0.9, 2011.01.11
--------------------------------------------
- remove optic mode dependency from module load and added the interface
FIO_OPTIC_MODE_SET, which must be called before any other configuration
- measurement module only read/calculate external temperature - without
any initial offset/gain-factor correction calibration
GPON Optic Driver, version 1.0.8, 2010.12.23
--------------------------------------------
- rebuild measurement module:
initially parallel measurement of all channels for offset (all gains), gain
corrections (all gains), VDD, VBE1, VBE2, p/n-junction and 3 power voltages
periodic switch between parallel measurement of offset, VDD, VBE1, VBE2 and 3
power voltages - explicite measurement of gain correction (rotating gain
selector) - explicite measurement of p/n-junction - and offset/gain
calibration
GPON Optic Driver, version 1.0.7, 2010.12.17
--------------------------------------------
- optic_exit() crash bugfixing: optic_context_free() cleaned
- no mm offset/gain corection recalibration: PLOAM state 5 accessable after ~10s
- mm init deactivated
GPON Optic Driver, version 1.0.6, 2010.12.08
--------------------------------------------
- shift table files from etc/config/ to etc/optic to clean up etc/config dir
- delete omu_init(), bosa_init()
- delete mode param in goi_init()
- add insmod parameter to choice OMU or BOSA mode at load-time
- preinit (OMU/BOSA) mode sensitive
GPON Optic Driver, version 1.0.5, 2010.12.03
--------------------------------------------
- bugfix optic_in_range() for address verification
- mm measurement concept redesign: parallel channels, measured all 100ms
gain/offset calibration is started for gain_selector 2 and done in parallel
all measurement types starts with configured number of measured values
to calculate an average value, later this value is updated via filter
- external temperature measurement bugfix & cleanup
GPON Optic Driver, version 1.0.4, 2010.11.25
--------------------------------------------
- gain/offset calibration (optic_ll_mm_calibrate()) optimized to prepare one
channel while reading another one. MM channels 0 and 1 are used
- gain/offset calibration restructured: channel prepare + read cycles + channel
reset. Same sequence used for all measurements
- internal temperature measurement cleanup
- dual loop state machine completed
- interrupt handling skeletton
GPON Optic Driver, version 1.0.3, 2010.11.19
--------------------------------------------
- initialisation adaptation, preinit, omu mode, printout options
- bugfix gpio request/interpretation
- bugfix optic_ll_mm_prepare()
- config parameters for BOSA dualloop introduced
- dual loop support: optic_ll_mpd_regulation_get(), optic_ll_mpd_stable_get()
GPON Optic Driver, version 1.0.2, 2010.11.12
--------------------------------------------
- pre-init sequence for module load phase
- mpd_cfg_set/get() enhanced by cid settings
- bosa_tx_cfg_set/get() enhanced by learnthreshold_bias/mod and
updatethreshold_bias/mod for dual loop operation
- goi_init() cleanup: OMU/BOSA PLL initialisation shifted to the start
goi_init() is called by startup handshake (hotplug event, if all configs read)
- housekeeper / measure_thread enhancement: BOSA event for BOSA measurements
GPON Optic Driver, version 1.0.1, 2010.11.05
--------------------------------------------
- goi_status_get() enhanced by imod, amod, ibias, abias
- BOSA module support: bosa_init() enhanced,
bosa_rx_cfg_set/get(), bosa_tx_cfg_set/get(), bosa_rx_enable/disable()
bosa_tx_enable/disable(), bosa_rx_status_get(), bosa_tx_status_get() added
- mm_cfg_set/get(): support RSSI1490shunt, RSSI1550vref, RF1550vref
- MM module: RSSI 1490 differential and single ended voltage/curent measurement
supported, RSSI 1550 and RF 1550 single ended voltage measurement supported
automatic gain calibration (only one correction of gain + new measurement
per cycle)
GPON Optic Driver, version 1.0.0, 2010.10.29
--------------------------------------------
- DCDC APD module added (drv_optic_dcdc_apd_interface.h, drv_optic_dcdc_apd.c)
dcdc_apd_cfg_set/get(), dcdc_apd_enable/disable(), dcdc_apd_voltage_set/get(),
dcdc_apd_status_get() added
- dcdc_apd_voltage_set(): APD voltage is changed by 2V maximum,
if needed, in several steps using 10ms timer optic_timer_apd_adapt()
- APD duty cycle saturation added to VAPD temperature table (calculated via
application). In case of dcdc_apd_voltage_set() sat value is calculated via
interpolation between nearest vapd voltage entries
GPON Optic Driver, version 0.4.1, 2010.10.22
--------------------------------------------
- CLI base command "vig" supported (instead of "vg") with additonal "type"
- BOSA module support: bosa_init(), bosa_powerlevel_set/get(),
bosa_dualloop_enable/disable(), bosa_dualloop_status_get()
- MPD module: mpd_trace_get() added
- typedef cleanup, register header files
GPON Optic Driver, version 0.4.0, 2010.10.20
--------------------------------------------
- CLI bugfix (additional parameters were skipped)
- CLI command "vg" added (used by LantiqLab for initial handshake)
- CAL module renew: cal_mpd_dbg_gaincal_set/get() ->
cal_mpd_dbg_gain_set/get(), cal_mpd_dbg_cal_set/get()
cal_mpd_gaincal_set/get() -> cal_mpd_gain_set/get(), cal_mpd_cal_set/get()
cal_mpd_refcw_set/get() -> cal_mpd_ref_codeword_set/get()
cal_mpd_dbg_refcw_set/get() -> cal_mpd_dbg_ref_codeword_set/get()
cal_mpd_offset_set/get/find() -> cal_mpd_tia_offset_set/get/find()
cal_mpd_dbg_offset_set/get() -> cal_mpd_dbg_tia_offset_set/get()
- MPD calibration splitted for independent P0 / P1 calibration
(needed for cal_mpd_level_find())
- CAL module: cal_mpd_level_set/get/find(),
cal_mpd_cfratio_set/get/find(), cal_fcsi_predriver_set/get() added
GPON Optic Driver, version 0.3.6, 2010.10.08
--------------------------------------------
- FCSI module support: fcsi_cfg_set/get() to init powerlevel specific fcsi
configuration: gvn, dd/bc_loadn, dd/bc_bias_en, dd/bc_loadp, dd/bc_cm_load
- CAL module: cal_debug_status_get(); status shown via otop
cal_mpd_gaincal_set/get(), cal_mpd_refcw_set/get(), cal_mpd_offset_set/get(),
cal_mpd_offset_find() added
- debug mode introduced: no powerlevel depending seetings are used but
debug setting (cal_debug_enable/disable())
cal_mpd_dbg_gaincal_set/get(), cal_mpd_dbg_refcw_set/get(),
cal_mpd_dbg_offset_set/get() added
GPON Optic Driver, version 0.3.5, 2010.10.01
--------------------------------------------
- laser lifetime (base) is configured via goi_cfg_set() - read from file
- laser lifetime (base) doublechecked against ibias/imod table
(use highest timestamp instead of configured base, if timestamp > base)
- optic driver use hotplug event to update stored laser lifetime (base) in file
- CAL module: cal_debug_enable/disable(), cal_vapd_table_set/get()
cal_mpdcorr_table_set/get(), cal_tcorrext_table_set/get() added
GPON Optic Driver, version 0.3.4, 2010.09.30
--------------------------------------------
- cleanup, deleting unused function description, skelettons, parameters
- mpd calibration in goi_init() shifted to bosa specific part: bosa_init()
- bert_status_get(): word_cnt and error_cnt added
- cal_ibiasimod_table_set/get(): read/written via temperature and powerlevel
definition; ibias/imod value + age timestamp read/written
- OCTRLG support: internal timestamp measured via OCTRLG.TXTCNT in seconds
- *_io_* files/routines renamed into *_ll_*
GPON Optic Driver, version 0.3.3, 2010.09.24
--------------------------------------------
- range configuration separated: goi_range_def_set/get()
- calibration module: ibias/imod direct write/read
- mm_laser_temperature_get(), mm_die_temperature_get() supported
with 1K granularity
- APD DCDC support: optic_ll_apd_init() called by goi_init()
- temperature specific cycle count / age
- goi_table_get() supported by driver
GPON Optic Driver, version 0.3.2, 2010.09.17
--------------------------------------------
- mm support: parameters used for external temperature measurement
- external temperature measurement (nominal), convert into corrected
- internal temperature (and external) calculated without bitshift [K]
- mpd calibration finalized: optic_ll_mpd_calibrate()
- loop mode setting separated: optic_ll_mpd_loop_set()
GPON Optic Driver, version 0.3.1, 2010.09.13
--------------------------------------------
- offset cancellation done per gain bank, coarse/fine DAC ratio measured
via separated gain selector for global measurements
- calibration (100uA/1mA) defined in config file for each gain bank
- transfer / completion of temptrans table supported
GPON Optic Driver, version 0.3.0, 2010.09.10
--------------------------------------------
- temperature tables rebuild: table_temperature_corr, table_temperature_nom
with separate min/max values, each processing routine differs between
- mm setting fix for internal temperature measurement
(separate channel for VDD, VBE1, VBE2 - no change needed)
- mpd cal setting is dependent of tia gain selector
- lol thresholds in omu configuration interpreted as % setting
GPON Optic Driver, version 0.2.7, 2010.09.07
--------------------------------------------
- mpd_cfg_set/get() separated from goi_cfg_set/get()
- state change crosscheck: all tables read / all config modules set
- drv_optic_goi_api.h deleted: api overview covered by drv_optic_api.h
- transfer / completion of mpd_resp_corr table supported
GPON Optic Driver, version 0.2.6, 2010.09.03
--------------------------------------------
- mpd support: dac calibration, offset cancellation,
mpd coarse/fine ratio measurement: optic_ll_mpd_ratio_measure()
- otop support for mpd calibrated settings (offset tia, P1; gain ratio P0, P1)
- cli cleanup (new style)
GPON Optic Driver, version 0.2.5, 2010.08.31
--------------------------------------------
- DCDC_APD access: pseudo 8 bit register support
- style cleanup: lower case functions and variables (not completed)
- VAPD calculated by application and transfered to driver
- fuse correction for temperature and ibias/imod values: optic_fusecorrect_*()
- ibias/imod -> codewords translation: optic_ibiasimod_codeword()
GPON Optic Driver, version 0.2.4, 2010.08.20
--------------------------------------------
- value type specific shift defines, gain correction becomes 32 bit
- extra-/interpolation of LaserRef table in application (instead of Ibias/Imod)
calculation of Ibias/Imod table bases of complete reference tables
- extrapolation bases on value type specific characteristic temperature/space,
if characteristic temperature cannot be calculated, initial value is used
GPON Optic Driver, version 0.2.3, 2010.08.17
--------------------------------------------
- Pth and LaserRef table are handled in application, Ibias/Imod table
is calculated and transfered via GOI_TableSet/Get()
- Inter-/Extrapolation in application
- GOI_CfgSet/Get parameters nP0[], nP1[], nPthRef deleted
- style cleanup (first parts): typedefs, variable names, function names, tabs
GPON Optic Driver, version 0.2.2, 2010.08.09
--------------------------------------------
- no *_StateSet/Get() CLI access : internal state gets part of GOI_StatusGet()
- default fuse values for fuse register == 0x0000 defined
- initialising FCSI.CBIAS with fuse information tgbp, vbgp, irefbgp
- management of several config and table states
- GOI_TableSet/Get() covers temperature table read/write (not GOI_CfgSet/Get())
GPON Optic Driver, version 0.2.1, 2010.08.06
--------------------------------------------
- no direct GPIO access, gpio_drv will care about
- new naming for OMU block: GOI_Omu* -> OMU_*
- separated bert interface: drv_optic_bert_interface.h,
drv_optic_bert.c, own OPTIC_BERT_MAGIC and bertFunctionTable
- gtc-pma access (alternative target for bert configuration)
- BERT support: BERT_CfgSet/Get(), BERT_Enable/Disable()
BERT_Synchronize(), BERT_StatusGet()
GPON Optic Driver, version 0.2.0, 2010.08.03
--------------------------------------------
- GPIO access in GOI_OmuCfgSet() for initialisation,
GOI_OmuRxStatusGet() and GOI_OmuTxStatusGet() for LOS, LOL, SD info
- temperature measurement / calculation
GPON Optic Driver, version 0.1.4, 2010.07.30
--------------------------------------------
- OMU support: GOI_OmuInit(), GOI_OmuCfgSet/Get(), GOI_OmuRxEnable/Disable(),
GOI_OmuTxEnable/Disable(), GOI_OmuRxStatusGet(), GOI_OmuTxStatusGet()
- offset/gain calibration
- proc fs / optic_top support for offset/gain calibration table
- SYSTEM_SIMULATION support (vhdl model based simulation of optic hardware)
- register access via OPTIC_RegisterRead/Write() supported for
OPTIC_SYS_GPON, OPTIC_STATUS, too
GPON Optic Driver, version 0.1.3, 2010.07.23
--------------------------------------------
- optic_top supports GOI_CfgGet() and internal temperature tables
via proc fs (current status: Pth, LaserRef, IbiasImod)
- generic table parsing and lineary interpolation of values
- calculation of ibias/imod in temp table (from pth, laser_ref)
- OPTIC_FCSI_BFD_CTRL0_RESET changed: 33 Ohm input termination
(bfd_rterm_sel = 0x07)
GPON Optic Driver, version 0.1.2, 2010.07.14
--------------------------------------------
- supports SYS_GPON module: activate clocks in GOI_Init()
- measurement thread, waked up by internal timer
- config table handling via control application
- interpolation of empty table values
GPON Optic Driver, version 0.1.1, 2010.07.09
--------------------------------------------
- FCSI initialisation
- reading fuse registers in GOI_Init()
- config tables read via ioctl (GOI_CfgSet)
- drv_optic_ll_pll.c/h for internal pll routines
- separated omu interface: drv_optic_omu_interface.h,
drv_optic_omu.c, own OPTIC_OMU_MAGIC and omuFunctionTable
GPON Optic Driver, version 0.1.0, 2010.07.01
--------------------------------------------
- opticFifo, nfcFifo, WorkerThread, control-deamon run
- hotplug msg -> etc/hotplug.d/gpon-optic/*
- 16 bit register support
- FCSI handling
- register access simulation
- devio timer simulation
GPON Optic Driver, version 0.0.2, 2010.06.01
--------------------------------------------
- ONU -> OPTIC cleanup
- register header files integrated
- register access via OPTIC_RegisterRead/Write()
GPON Optic Driver, version 0.0.1, 2010.04.01
--------------------------------------------
- skeleton reused from ONU driver

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This source code is distributed under a dual license of GPL and BSD (2-clause).
Please choose the appropriate license for your intended usage.
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Copyright (c) 2009, Lantiq Deutschland GmbH
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program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source
code means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to
control compilation and installation of the executable. However, as a
special exception, the source code distributed need not include
anything that is normally distributed (in either source or binary
form) with the major components (compiler, kernel, and so on) of the
operating system on which the executable runs, unless that component
itself accompanies the executable.
If distribution of executable or object code is made by offering
access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
void, and will automatically terminate your rights under this License.
However, parties who have received copies, or rights, from you under
this License will not have their licenses terminated so long as such
parties remain in full compliance.
5. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or distributing the Program (or any work based on the
Program), you indicate your acceptance of this License to do so, and
all its terms and conditions for copying, distributing or modifying
the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further
restrictions on the recipients' exercise of the rights granted herein.
You are not responsible for enforcing compliance by third parties to
this License.
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot
distribute so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you
may not distribute the Program at all. For example, if a patent
license would not permit royalty-free redistribution of the Program by
all those who receive copies directly or indirectly through you, then
the only way you could satisfy both it and this License would be to
refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
apply and the section as a whole is intended to apply in other
circumstances.
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
generous contributions to the wide range of software distributed
through that system in reliance on consistent application of that
system; it is up to the author/donor to decide if he or she is willing
to distribute software through any other system and a licensee cannot
impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

59
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## Process this file with automake to produce Makefile.in
AUTOMAKE_OPTIONS = foreign 1.7 nostdinc
if ENABLE_LINUX
LINUXDIRS = tools/optic tools/otop
endif ENABLE_LINUX
SUBDIRS = src $(LINUXDIRS)
DISTCHECK_CONFIGURE_FLAGS=@CONFIGURE_OPTIONS@
drv_optic_docdir = ${prefix}/doc/drv_optic
drv_optic_doc_DATA = \
LICENSE \
README \
AUTHORS \
ChangeLog \
NEWS \
TODO \
doc/doxyconfig \
doc/footer.html \
doc/header.html \
doc/logo.gif \
doc/stylesheet.css
EXTRA_DIST = $(drv_optic_doc_DATA)
clean-local:
rm -Rf .built .built_check .version* .prepared* ipkg/
# Copy all the spec files. Of cource, only one is actually used.
dist-hook:
for specfile in *.spec; do \
if test -f $$specfile; then \
cp -p $$specfile $(distdir); \
fi \
done
# Create self extracting linux distribution
distcheck-hook:
chmod a+w $(distdir)
echo "Checking line ends ...!!!"; \
find $(distdir) -type f -exec file {} \; | grep -e "CRLF" -e "Non-ISO" && exit 1; \
echo "Create installation package ..."; \
makeself.sh --gzip --notemp $(distdir) \
gpon_optic_drv-$(PACKAGE_VERSION).sh "$(PACKAGE_NAME)"
doc:
( cd @top_srcdir@/doc; \
doxygen doxyconfig; )
doc_cli:
( cd @top_srcdir@/doc; \
python @top_srcdir@/scripts/cli_parser.py; \
doxygen @top_srcdir@/doc/doxyconfig_cli; )
.PHONY: doc doc_cli

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# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.
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INSTALL_HEADER = $(INSTALL_DATA)
transform = $(program_transform_name)
NORMAL_INSTALL = :
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mkinstalldirs = $(install_sh) -d
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CONFIG_CLEAN_FILES =
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ETAGS = etags
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RANLIB = @RANLIB@
SET_MAKE = @SET_MAKE@
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README \
AUTHORS \
ChangeLog \
NEWS \
TODO \
doc/doxyconfig \
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doc/header.html \
doc/logo.gif \
doc/stylesheet.css
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0
NEWS Normal file
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README Normal file
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2
TODO Normal file
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@ -0,0 +1,2 @@
- init FCSI.BFD.GVS via config file (GainGVS) for offest cancellation

902
aclocal.m4 vendored Normal file
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# and am__untar set.
test -n "${am_cv_prog_tar_$1}" && break
# tar/untar a dummy directory, and stop if the command works
rm -rf conftest.dir
mkdir conftest.dir
echo GrepMe > conftest.dir/file
AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar])
rm -rf conftest.dir
if test -s conftest.tar; then
AM_RUN_LOG([$am__untar <conftest.tar])
grep GrepMe conftest.dir/file >/dev/null 2>&1 && break
fi
done
rm -rf conftest.dir
AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool])
AC_MSG_RESULT([$am_cv_prog_tar_$1])])
AC_SUBST([am__tar])
AC_SUBST([am__untar])
]) # _AM_PROG_TAR

142
compile Executable file
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@ -0,0 +1,142 @@
#! /bin/sh
# Wrapper for compilers which do not understand `-c -o'.
scriptversion=2005-05-14.22
# Copyright (C) 1999, 2000, 2003, 2004, 2005 Free Software Foundation, Inc.
# Written by Tom Tromey <tromey@cygnus.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
# This file is maintained in Automake, please report
# bugs to <bug-automake@gnu.org> or send patches to
# <automake-patches@gnu.org>.
case $1 in
'')
echo "$0: No command. Try \`$0 --help' for more information." 1>&2
exit 1;
;;
-h | --h*)
cat <<\EOF
Usage: compile [--help] [--version] PROGRAM [ARGS]
Wrapper for compilers which do not understand `-c -o'.
Remove `-o dest.o' from ARGS, run PROGRAM with the remaining
arguments, and rename the output as expected.
If you are trying to build a whole package this is not the
right script to run: please start by reading the file `INSTALL'.
Report bugs to <bug-automake@gnu.org>.
EOF
exit $?
;;
-v | --v*)
echo "compile $scriptversion"
exit $?
;;
esac
ofile=
cfile=
eat=
for arg
do
if test -n "$eat"; then
eat=
else
case $1 in
-o)
# configure might choose to run compile as `compile cc -o foo foo.c'.
# So we strip `-o arg' only if arg is an object.
eat=1
case $2 in
*.o | *.obj)
ofile=$2
;;
*)
set x "$@" -o "$2"
shift
;;
esac
;;
*.c)
cfile=$1
set x "$@" "$1"
shift
;;
*)
set x "$@" "$1"
shift
;;
esac
fi
shift
done
if test -z "$ofile" || test -z "$cfile"; then
# If no `-o' option was seen then we might have been invoked from a
# pattern rule where we don't need one. That is ok -- this is a
# normal compilation that the losing compiler can handle. If no
# `.c' file was seen then we are probably linking. That is also
# ok.
exec "$@"
fi
# Name of file we expect compiler to create.
cofile=`echo "$cfile" | sed -e 's|^.*/||' -e 's/\.c$/.o/'`
# Create the lock directory.
# Note: use `[/.-]' here to ensure that we don't use the same name
# that we are using for the .o file. Also, base the name on the expected
# object file name, since that is what matters with a parallel build.
lockdir=`echo "$cofile" | sed -e 's|[/.-]|_|g'`.d
while true; do
if mkdir "$lockdir" >/dev/null 2>&1; then
break
fi
sleep 1
done
# FIXME: race condition here if user kills between mkdir and trap.
trap "rmdir '$lockdir'; exit 1" 1 2 15
# Run the compile.
"$@"
ret=$?
if test -f "$cofile"; then
mv "$cofile" "$ofile"
elif test -f "${cofile}bj"; then
mv "${cofile}bj" "$ofile"
fi
rmdir "$lockdir"
exit $ret
# Local Variables:
# mode: shell-script
# sh-indentation: 2
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:

7365
configure vendored Executable file
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353
configure.in Normal file
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@ -0,0 +1,353 @@
dnl Process this file with autoconf to produce a configure script.
AC_REVISION($Revision: 1.10 $)
AC_INIT([GPON Optic Driver],[4.5.0],[],[gpon_optic_drv])
AC_PROG_CC
ifdef([AC_PROG_CC_STDC], [AC_PROG_CC_STDC])
AC_LANG([C])
AC_PROG_RANLIB
AC_CONFIG_SRCDIR(src/drv_optic_common.c)
AM_INIT_AUTOMAKE
AM_PROG_CC_C_O
AC_PROG_CXX
AC_CONFIG_HEADER(src/drv_optic_config.h)
AH_TOP([
/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _GPON_OPTIC_CONFIG_H
#define _GPON_OPTIC_CONFIG_H])
AH_BOTTOM([
#endif /* _GPON_OPTIC_CONFIG_H */])
#
# save the configure arguments
#
CONFIGURE_OPTIONS="$ac_configure_args"
AC_SUBST(CONFIGURE_OPTIONS)
AC_CHECK_TYPES([ulong_t])
dnl enable linux kernel 2.6.x support
AM_CONDITIONAL(KERNEL_2_6, true)
AC_ARG_ENABLE(linux-26,
AS_HELP_STRING(--enable-linux-26,Enable support for linux kernel 2.6.x),
[
AM_CONDITIONAL(KERNEL_2_6, true)
if test -z "$ARCH" ; then
[ARCH=`$CC -dumpmachine | sed -e s'/-.*//' \
-e 's/i[3-9]86/i386/' \
-e 's/mipsel/mips/' \
-e 's/powerpc/ppc/' \
-e 's/sh[234]/sh/' \
`]
fi
if test -n "$ARCH" ; then
echo "Set the kernel architecture to $ARCH"
AC_SUBST([KERNEL_ARCH],[$ARCH])
else
AC_MSG_ERROR([Kernel architecture not set!])
fi
]
)
dnl Set kernel include path (Linux, eCos, ...)
DEFAULT_KERNEL_INCL_PATH='.'
AC_ARG_ENABLE(kernelincl,
AS_HELP_STRING([--enable-kernelincl=x],[Set the target kernel include path
]),
[
if test -n $enableval; then
echo Set the kernel include path $enableval
AC_SUBST([KERNEL_INCL_PATH],[$enableval])
else
echo Set the default kernel include path $DEFAULT_KERNEL_INCL_PATH
AC_SUBST([KERNEL_INCL_PATH],[$DEFAULT_KERNEL_INCL_PATH])
fi
],
[
echo Set the default kernel include path $DEFAULT_KERNEL_INCL_PATH
AC_SUBST([KERNEL_INCL_PATH],[$DEFAULT_KERNEL_INCL_PATH])
]
)
dnl Set kernel build path
AC_ARG_ENABLE(kernelbuild,
AS_HELP_STRING(--enable-kernelbuild=x,Set the target kernel build path (only for kernel 2.6.x)),
[
if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
else
AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
fi
],
[
if test -z $KERNEL_BUILD_PATH; then
# assume kernel was build in source dir...
AC_SUBST([KERNEL_BUILD_PATH],[$KERNEL_INCL_PATH/..])
fi
]
)
dnl set libifxos.a library path
DEFAULT_IFXOS_LIBRARY_PATH='-L.'
AC_ARG_ENABLE(ifxos-library,
AS_HELP_STRING([--enable-ifxos-library=/path/to/your/lib_ifxos/src] , [Set the lib_ifxos library path. In this location the libifxos.a should be found]),
[
if test -n "$enableval"; then
echo Set the libifxos.a library path to $enableval
AC_SUBST([IFXOS_LIBRARY_PATH],[$enableval])
else
echo Set the lib_board_config library path $DEFAULT_IFXOS_LIBRARY_PATH
AC_SUBST([IFXOS_LIBRARY_PATH],[$DEFAULT_IFXOS_LIBRARY_PATH])
fi
],
[
echo Set the libifxos.a library path $DEFAULT_IFXOS_LIBRARY_PATH
AC_SUBST([IFXOS_LIBRARY_PATH],[$DEFAULT_IFXOS_LIBRARY_PATH])
]
)
dnl set lib_ifxos include path
DEFAULT_IFXOS_INCLUDE_PATH='-I.'
AC_ARG_ENABLE(ifxos-include,
AS_HELP_STRING([--enable-ifxos-include=-I/path/to/your/lib_ifxos/src/include],[Set the lib_ifxos include path.]),
[
if test -n "$enableval"; then
echo Set the lib_ifxos include path $enableval
AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
else
echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
fi
],
[
echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
]
)
dnl compile for linux kernel
ENABLE_LINUX=true
AC_ARG_ENABLE(linux,
AS_HELP_STRING(
[--enable-linux],
[Enable linux support]
),
[
case $enableval in
0|no)
ENABLE_LINUX=false
;;
1|yes)
;;
*) AC_MSG_ERROR([linux support]);
;;
esac
]
)
dnl Build simulation application
AM_CONDITIONAL(OPTIC_SIMULATION, false)
AC_ARG_WITH(optic-simulation,
AS_HELP_STRING(
[--with-optic-simulation],
[OPTIC simulation]
),
[
echo OPTIC simulation = $withval
case $withval in
0|no)
;;
1|yes)
AC_DEFINE(OPTIC_SIMULATION,,[OPTIC simulation])
AM_CONDITIONAL(OPTIC_SIMULATION, true)
ENABLE_LINUX=false
;;
*) AC_MSG_ERROR([ OPTIC simulation ]);
;;
esac
],
[
echo OPTIC simulation disabled
]
)
dnl Build os independend library
AM_CONDITIONAL(OPTIC_LIBRARY, false)
AC_ARG_WITH(optic-library,
AS_HELP_STRING(
[--with-optic-library],
[OPTIC library]
),
[
echo OPTIC library = $withval
case $withval in
0|no)
;;
1|yes)
AC_DEFINE(OPTIC_LIBRARY,,[OPTIC library])
AM_CONDITIONAL(OPTIC_LIBRARY, true)
ENABLE_LINUX=false
;;
*) AC_MSG_ERROR([ OPTIC library ]);
;;
esac
],
[
echo OPTIC library disabled
]
)
AM_CONDITIONAL(ENABLE_LINUX, $ENABLE_LINUX)
if test "$ENABLE_LINUX" == "true" ; then
AC_DEFINE(ENABLE_LINUX,,[compile for linux kernel])
fi
dnl Include Command Line Interface
AC_ARG_WITH(cli,
AS_HELP_STRING(
[--with-cli],
[Command Line Interface]
),
[
echo Command Line Interface = $withval
case $withval in
0|no)
;;
1|yes)
AC_DEFINE(INCLUDE_CLI_SUPPORT,,[Command Line Interface])
;;
*) AC_MSG_ERROR([ Command Line Interface ]);
;;
esac
],
[
echo Command Line Interface enabled
AC_DEFINE(INCLUDE_CLI_SUPPORT,,[Command Line Interface])
]
)
dnl Include procfs support
AC_ARG_WITH(procfs,
AS_HELP_STRING(
[--with-procfs],
[proc filesystem]
),
[
echo proc filesystem = $withval
case $withval in
0|no)
;;
1|yes)
AC_DEFINE(INCLUDE_PROCFS_SUPPORT,,[proc filesystem])
;;
*) AC_MSG_ERROR([ proc filesystem ]);
;;
esac
],
[
echo procfs support enabled
AC_DEFINE(INCLUDE_PROCFS_SUPPORT,,[proc filesystem])
]
)
dnl Add debugging information
AC_ARG_WITH(debug-support,
AS_HELP_STRING(
[--with-debug-support],
[Debug Support]
),
[
echo Debug Support = $withval
case $withval in
0|no)
;;
1|yes)
AC_DEFINE(INCLUDE_DEBUG_SUPPORT,,[Debug Support])
;;
*) AC_MSG_ERROR([Debug Support]);
;;
esac
],
[
echo Debug Support enabled
AC_DEFINE(INCLUDE_DEBUG_SUPPORT,,[Debug Support])
]
)
dnl set Event Logger includes path
AM_CONDITIONAL(EVENT_LOGGER_DEBUG, false)
AC_ARG_WITH(el-incl,
AC_HELP_STRING(
[--with-el-incl@<:@=-IDIR@:>@],
[Event Logger includes path]
),
[
AC_SUBST([EVENT_LOGGER_INCL_PATH],[$withval])
AC_DEFINE([EVENT_LOGGER_DEBUG],[1],[enable event logger debugging])
AM_CONDITIONAL(EVENT_LOGGER_DEBUG, true)
]
)
dnl enable\disable remote ONU
AC_ARG_ENABLE(remote-onu,
AS_HELP_STRING([--enable-remote-onu],
[enable remote ONU]),
[
if test "$enableval" = yes; then
echo Enable remote ONU
AC_DEFINE([INCLUDE_REMOTE_ONU], [1], [Enable remote ONU])
AC_SUBST([INCLUDE_REMOTE_ONU],[$enableval])
AM_CONDITIONAL(INCLUDE_REMOTE_ONU, true)
else
echo Disable remote ONU
AM_CONDITIONAL(INCLUDE_REMOTE_ONU, false)
fi
],
[
echo Enable remote ONU
AC_DEFINE([INCLUDE_REMOTE_ONU], [1], [Enable remote ONU])
AC_SUBST([INCLUDE_REMOTE_ONU],[$enableval])
AM_CONDITIONAL(INCLUDE_REMOTE_ONU, true)
]
)
dnl enable\disable remote-only ONU
AC_ARG_ENABLE(remote-only-onu,
AS_HELP_STRING([--enable-remote-only-onu],
[enable remote-only ONU]),
[
if test "$enableval" = yes; then
echo Enable remote-only ONU
AC_DEFINE([INCLUDE_REMOTE_ONLY_ONU], [1], [Enable remote-only ONU])
AC_SUBST([INCLUDE_REMOTE_ONLY_ONU],[$enableval])
AM_CONDITIONAL(INCLUDE_REMOTE_ONLY_ONU, true)
else
echo Disable remote-only ONU
AM_CONDITIONAL(INCLUDE_REMOTE_ONLY_ONU, false)
fi
],
[
echo Disable remote ONU
AM_CONDITIONAL(INCLUDE_REMOTE_ONLY_ONU, false)
]
)
AC_CONFIG_FILES([Makefile src/Makefile tools/optic/Makefile tools/otop/Makefile])
AC_OUTPUT

589
depcomp Executable file
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@ -0,0 +1,589 @@
#! /bin/sh
# depcomp - compile a program generating dependencies as side-effects
scriptversion=2007-03-29.01
# Copyright (C) 1999, 2000, 2003, 2004, 2005, 2006, 2007 Free Software
# Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
# Originally written by Alexandre Oliva <oliva@dcc.unicamp.br>.
case $1 in
'')
echo "$0: No command. Try \`$0 --help' for more information." 1>&2
exit 1;
;;
-h | --h*)
cat <<\EOF
Usage: depcomp [--help] [--version] PROGRAM [ARGS]
Run PROGRAMS ARGS to compile a file, generating dependencies
as side-effects.
Environment variables:
depmode Dependency tracking mode.
source Source file read by `PROGRAMS ARGS'.
object Object file output by `PROGRAMS ARGS'.
DEPDIR directory where to store dependencies.
depfile Dependency file to output.
tmpdepfile Temporary file to use when outputing dependencies.
libtool Whether libtool is used (yes/no).
Report bugs to <bug-automake@gnu.org>.
EOF
exit $?
;;
-v | --v*)
echo "depcomp $scriptversion"
exit $?
;;
esac
if test -z "$depmode" || test -z "$source" || test -z "$object"; then
echo "depcomp: Variables source, object and depmode must be set" 1>&2
exit 1
fi
# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po.
depfile=${depfile-`echo "$object" |
sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`}
tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`}
rm -f "$tmpdepfile"
# Some modes work just like other modes, but use different flags. We
# parameterize here, but still list the modes in the big case below,
# to make depend.m4 easier to write. Note that we *cannot* use a case
# here, because this file can only contain one case statement.
if test "$depmode" = hp; then
# HP compiler uses -M and no extra arg.
gccflag=-M
depmode=gcc
fi
if test "$depmode" = dashXmstdout; then
# This is just like dashmstdout with a different argument.
dashmflag=-xM
depmode=dashmstdout
fi
case "$depmode" in
gcc3)
## gcc 3 implements dependency tracking that does exactly what
## we want. Yay! Note: for some reason libtool 1.4 doesn't like
## it if -MD -MP comes after the -MF stuff. Hmm.
## Unfortunately, FreeBSD c89 acceptance of flags depends upon
## the command line argument order; so add the flags where they
## appear in depend2.am. Note that the slowdown incurred here
## affects only configure: in makefiles, %FASTDEP% shortcuts this.
for arg
do
case $arg in
-c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;;
*) set fnord "$@" "$arg" ;;
esac
shift # fnord
shift # $arg
done
"$@"
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
mv "$tmpdepfile" "$depfile"
;;
gcc)
## There are various ways to get dependency output from gcc. Here's
## why we pick this rather obscure method:
## - Don't want to use -MD because we'd like the dependencies to end
## up in a subdir. Having to rename by hand is ugly.
## (We might end up doing this anyway to support other compilers.)
## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like
## -MM, not -M (despite what the docs say).
## - Using -M directly means running the compiler twice (even worse
## than renaming).
if test -z "$gccflag"; then
gccflag=-MD,
fi
"$@" -Wp,"$gccflag$tmpdepfile"
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
rm -f "$depfile"
echo "$object : \\" > "$depfile"
alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz
## The second -e expression handles DOS-style file names with drive letters.
sed -e 's/^[^:]*: / /' \
-e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile"
## This next piece of magic avoids the `deleted header file' problem.
## The problem is that when a header file which appears in a .P file
## is deleted, the dependency causes make to die (because there is
## typically no way to rebuild the header). We avoid this by adding
## dummy dependencies for each header file. Too bad gcc doesn't do
## this for us directly.
tr ' ' '
' < "$tmpdepfile" |
## Some versions of gcc put a space before the `:'. On the theory
## that the space means something, we add a space to the output as
## well.
## Some versions of the HPUX 10.20 sed can't process this invocation
## correctly. Breaking it into two sed invocations is a workaround.
sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
hp)
# This case exists only to let depend.m4 do its work. It works by
# looking at the text of this script. This case will never be run,
# since it is checked for above.
exit 1
;;
sgi)
if test "$libtool" = yes; then
"$@" "-Wp,-MDupdate,$tmpdepfile"
else
"$@" -MDupdate "$tmpdepfile"
fi
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
rm -f "$depfile"
if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files
echo "$object : \\" > "$depfile"
# Clip off the initial element (the dependent). Don't try to be
# clever and replace this with sed code, as IRIX sed won't handle
# lines with more than a fixed number of characters (4096 in
# IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines;
# the IRIX cc adds comments like `#:fec' to the end of the
# dependency line.
tr ' ' '
' < "$tmpdepfile" \
| sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' | \
tr '
' ' ' >> $depfile
echo >> $depfile
# The second pass generates a dummy entry for each header file.
tr ' ' '
' < "$tmpdepfile" \
| sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \
>> $depfile
else
# The sourcefile does not contain any dependencies, so just
# store a dummy comment line, to avoid errors with the Makefile
# "include basename.Plo" scheme.
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile"
;;
aix)
# The C for AIX Compiler uses -M and outputs the dependencies
# in a .u file. In older versions, this file always lives in the
# current directory. Also, the AIX compiler puts `$object:' at the
# start of each line; $object doesn't have directory information.
# Version 6 uses the directory in both cases.
dir=`echo "$object" | sed -e 's|/[^/]*$|/|'`
test "x$dir" = "x$object" && dir=
base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'`
if test "$libtool" = yes; then
tmpdepfile1=$dir$base.u
tmpdepfile2=$base.u
tmpdepfile3=$dir.libs/$base.u
"$@" -Wc,-M
else
tmpdepfile1=$dir$base.u
tmpdepfile2=$dir$base.u
tmpdepfile3=$dir$base.u
"$@" -M
fi
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3"
exit $stat
fi
for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3"
do
test -f "$tmpdepfile" && break
done
if test -f "$tmpdepfile"; then
# Each line is of the form `foo.o: dependent.h'.
# Do two passes, one to just change these to
# `$object: dependent.h' and one to simply `dependent.h:'.
sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile"
# That's a tab and a space in the [].
sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile"
else
# The sourcefile does not contain any dependencies, so just
# store a dummy comment line, to avoid errors with the Makefile
# "include basename.Plo" scheme.
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile"
;;
icc)
# Intel's C compiler understands `-MD -MF file'. However on
# icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c
# ICC 7.0 will fill foo.d with something like
# foo.o: sub/foo.c
# foo.o: sub/foo.h
# which is wrong. We want:
# sub/foo.o: sub/foo.c
# sub/foo.o: sub/foo.h
# sub/foo.c:
# sub/foo.h:
# ICC 7.1 will output
# foo.o: sub/foo.c sub/foo.h
# and will wrap long lines using \ :
# foo.o: sub/foo.c ... \
# sub/foo.h ... \
# ...
"$@" -MD -MF "$tmpdepfile"
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
rm -f "$depfile"
# Each line is of the form `foo.o: dependent.h',
# or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'.
# Do two passes, one to just change these to
# `$object: dependent.h' and one to simply `dependent.h:'.
sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile"
# Some versions of the HPUX 10.20 sed can't process this invocation
# correctly. Breaking it into two sed invocations is a workaround.
sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" |
sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
hp2)
# The "hp" stanza above does not work with aCC (C++) and HP's ia64
# compilers, which have integrated preprocessors. The correct option
# to use with these is +Maked; it writes dependencies to a file named
# 'foo.d', which lands next to the object file, wherever that
# happens to be.
# Much of this is similar to the tru64 case; see comments there.
dir=`echo "$object" | sed -e 's|/[^/]*$|/|'`
test "x$dir" = "x$object" && dir=
base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'`
if test "$libtool" = yes; then
tmpdepfile1=$dir$base.d
tmpdepfile2=$dir.libs/$base.d
"$@" -Wc,+Maked
else
tmpdepfile1=$dir$base.d
tmpdepfile2=$dir$base.d
"$@" +Maked
fi
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile1" "$tmpdepfile2"
exit $stat
fi
for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2"
do
test -f "$tmpdepfile" && break
done
if test -f "$tmpdepfile"; then
sed -e "s,^.*\.[a-z]*:,$object:," "$tmpdepfile" > "$depfile"
# Add `dependent.h:' lines.
sed -ne '2,${; s/^ *//; s/ \\*$//; s/$/:/; p;}' "$tmpdepfile" >> "$depfile"
else
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile" "$tmpdepfile2"
;;
tru64)
# The Tru64 compiler uses -MD to generate dependencies as a side
# effect. `cc -MD -o foo.o ...' puts the dependencies into `foo.o.d'.
# At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put
# dependencies in `foo.d' instead, so we check for that too.
# Subdirectories are respected.
dir=`echo "$object" | sed -e 's|/[^/]*$|/|'`
test "x$dir" = "x$object" && dir=
base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'`
if test "$libtool" = yes; then
# With Tru64 cc, shared objects can also be used to make a
# static library. This mechanism is used in libtool 1.4 series to
# handle both shared and static libraries in a single compilation.
# With libtool 1.4, dependencies were output in $dir.libs/$base.lo.d.
#
# With libtool 1.5 this exception was removed, and libtool now
# generates 2 separate objects for the 2 libraries. These two
# compilations output dependencies in $dir.libs/$base.o.d and
# in $dir$base.o.d. We have to check for both files, because
# one of the two compilations can be disabled. We should prefer
# $dir$base.o.d over $dir.libs/$base.o.d because the latter is
# automatically cleaned when .libs/ is deleted, while ignoring
# the former would cause a distcleancheck panic.
tmpdepfile1=$dir.libs/$base.lo.d # libtool 1.4
tmpdepfile2=$dir$base.o.d # libtool 1.5
tmpdepfile3=$dir.libs/$base.o.d # libtool 1.5
tmpdepfile4=$dir.libs/$base.d # Compaq CCC V6.2-504
"$@" -Wc,-MD
else
tmpdepfile1=$dir$base.o.d
tmpdepfile2=$dir$base.d
tmpdepfile3=$dir$base.d
tmpdepfile4=$dir$base.d
"$@" -MD
fi
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4"
exit $stat
fi
for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4"
do
test -f "$tmpdepfile" && break
done
if test -f "$tmpdepfile"; then
sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile"
# That's a tab and a space in the [].
sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile"
else
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile"
;;
#nosideeffect)
# This comment above is used by automake to tell side-effect
# dependency tracking mechanisms from slower ones.
dashmstdout)
# Important note: in order to support this mode, a compiler *must*
# always write the preprocessed file to stdout, regardless of -o.
"$@" || exit $?
# Remove the call to Libtool.
if test "$libtool" = yes; then
while test $1 != '--mode=compile'; do
shift
done
shift
fi
# Remove `-o $object'.
IFS=" "
for arg
do
case $arg in
-o)
shift
;;
$object)
shift
;;
*)
set fnord "$@" "$arg"
shift # fnord
shift # $arg
;;
esac
done
test -z "$dashmflag" && dashmflag=-M
# Require at least two characters before searching for `:'
# in the target name. This is to cope with DOS-style filenames:
# a dependency such as `c:/foo/bar' could be seen as target `c' otherwise.
"$@" $dashmflag |
sed 's:^[ ]*[^: ][^:][^:]*\:[ ]*:'"$object"'\: :' > "$tmpdepfile"
rm -f "$depfile"
cat < "$tmpdepfile" > "$depfile"
tr ' ' '
' < "$tmpdepfile" | \
## Some versions of the HPUX 10.20 sed can't process this invocation
## correctly. Breaking it into two sed invocations is a workaround.
sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
dashXmstdout)
# This case only exists to satisfy depend.m4. It is never actually
# run, as this mode is specially recognized in the preamble.
exit 1
;;
makedepend)
"$@" || exit $?
# Remove any Libtool call
if test "$libtool" = yes; then
while test $1 != '--mode=compile'; do
shift
done
shift
fi
# X makedepend
shift
cleared=no
for arg in "$@"; do
case $cleared in
no)
set ""; shift
cleared=yes ;;
esac
case "$arg" in
-D*|-I*)
set fnord "$@" "$arg"; shift ;;
# Strip any option that makedepend may not understand. Remove
# the object too, otherwise makedepend will parse it as a source file.
-*|$object)
;;
*)
set fnord "$@" "$arg"; shift ;;
esac
done
obj_suffix="`echo $object | sed 's/^.*\././'`"
touch "$tmpdepfile"
${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@"
rm -f "$depfile"
cat < "$tmpdepfile" > "$depfile"
sed '1,2d' "$tmpdepfile" | tr ' ' '
' | \
## Some versions of the HPUX 10.20 sed can't process this invocation
## correctly. Breaking it into two sed invocations is a workaround.
sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile" "$tmpdepfile".bak
;;
cpp)
# Important note: in order to support this mode, a compiler *must*
# always write the preprocessed file to stdout.
"$@" || exit $?
# Remove the call to Libtool.
if test "$libtool" = yes; then
while test $1 != '--mode=compile'; do
shift
done
shift
fi
# Remove `-o $object'.
IFS=" "
for arg
do
case $arg in
-o)
shift
;;
$object)
shift
;;
*)
set fnord "$@" "$arg"
shift # fnord
shift # $arg
;;
esac
done
"$@" -E |
sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \
-e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' |
sed '$ s: \\$::' > "$tmpdepfile"
rm -f "$depfile"
echo "$object : \\" > "$depfile"
cat < "$tmpdepfile" >> "$depfile"
sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
msvisualcpp)
# Important note: in order to support this mode, a compiler *must*
# always write the preprocessed file to stdout, regardless of -o,
# because we must use -o when running libtool.
"$@" || exit $?
IFS=" "
for arg
do
case "$arg" in
"-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI")
set fnord "$@"
shift
shift
;;
*)
set fnord "$@" "$arg"
shift
shift
;;
esac
done
"$@" -E |
sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::echo "`cygpath -u \\"\1\\"`":p' | sort | uniq > "$tmpdepfile"
rm -f "$depfile"
echo "$object : \\" > "$depfile"
. "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s:: \1 \\:p' >> "$depfile"
echo " " >> "$depfile"
. "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::\1\::p' >> "$depfile"
rm -f "$tmpdepfile"
;;
none)
exec "$@"
;;
*)
echo "Unknown depmode $depmode" 1>&2
exit 1
;;
esac
exit 0
# Local Variables:
# mode: shell-script
# sh-indentation: 2
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:

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<hr>
<img border="0" src="logo.gif" width="160" height="72">
<address style="align: right;"><small>
Generated on $datetime for $projectname by doxygen $doxygenversion</small></address>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
<title>$title</title>
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DIV.qindex {
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DIV.nav {
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border: 1px solid #84b0c7;
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DIV.navtab {
background-color: #e8eef2;
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TD.navtab {
font-size: 70%;
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A.qindex {
text-decoration: none;
font-weight: bold;
color: #1A419D;
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A.qindex:visited {
text-decoration: none;
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text-decoration: none;
font-weight: bold;
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border: 1px double #9295C2;
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A.qindexHL:hover {
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PRE.fragment {
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DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px }
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BODY {
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TD.indexkey {
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margin-right : 0px;
margin-top : 2px;
margin-bottom : 2px;
border: 1px solid #CCCCCC;
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TR.memlist {
background-color: #f0f0f0;
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P.formulaDsp { text-align: center; }
IMG.formulaDsp { }
IMG.formulaInl { vertical-align: middle; }
SPAN.keyword { color: #008000 }
SPAN.keywordtype { color: #604020 }
SPAN.keywordflow { color: #e08000 }
SPAN.comment { color: #800000 }
SPAN.preprocessor { color: #806020 }
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font-style: italic;
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border-right: 1px none #E0E0E0;
border-bottom: 1px none #E0E0E0;
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margin: 0px;
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border-top-style: solid;
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font-size: 80%;
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margin: 4px;
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border-right-width: 1px;
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border-right-width: 1px;
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DIV.tabs UL
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margin : 0px;
padding-left : 10px;
list-style : none;
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DIV.tabs LI, DIV.tabs FORM
{
display : inline;
margin : 0px;
padding : 0px;
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DIV.tabs FORM
{
float : right;
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DIV.tabs A
{
float : left;
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font-weight : bold;
text-decoration : none;
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DIV.tabs A:active, DIV.tabs A:hover
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DIV.tabs SPAN
{
float : left;
display : block;
background : url("tab_l.gif") no-repeat left top;
padding : 5px 9px;
white-space : nowrap;
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{
float : right;
display : inline;
font-size : 1em;
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{
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font-weight : bold;
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519
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#!/bin/sh
# install - install a program, script, or datafile
scriptversion=2006-12-25.00
# This originates from X11R5 (mit/util/scripts/install.sh), which was
# later released in X11R6 (xc/config/util/install.sh) with the
# following copyright and license.
#
# Copyright (C) 1994 X Consortium
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to
# deal in the Software without restriction, including without limitation the
# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
# sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC-
# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
# Except as contained in this notice, the name of the X Consortium shall not
# be used in advertising or otherwise to promote the sale, use or other deal-
# ings in this Software without prior written authorization from the X Consor-
# tium.
#
#
# FSF changes to this file are in the public domain.
#
# Calling this script install-sh is preferred over install.sh, to prevent
# `make' implicit rules from creating a file called install from it
# when there is no Makefile.
#
# This script is compatible with the BSD install script, but was written
# from scratch.
nl='
'
IFS=" "" $nl"
# set DOITPROG to echo to test this script
# Don't use :- since 4.3BSD and earlier shells don't like it.
doit=${DOITPROG-}
if test -z "$doit"; then
doit_exec=exec
else
doit_exec=$doit
fi
# Put in absolute file names if you don't have them in your path;
# or use environment vars.
chgrpprog=${CHGRPPROG-chgrp}
chmodprog=${CHMODPROG-chmod}
chownprog=${CHOWNPROG-chown}
cmpprog=${CMPPROG-cmp}
cpprog=${CPPROG-cp}
mkdirprog=${MKDIRPROG-mkdir}
mvprog=${MVPROG-mv}
rmprog=${RMPROG-rm}
stripprog=${STRIPPROG-strip}
posix_glob='?'
initialize_posix_glob='
test "$posix_glob" != "?" || {
if (set -f) 2>/dev/null; then
posix_glob=
else
posix_glob=:
fi
}
'
posix_mkdir=
# Desired mode of installed file.
mode=0755
chgrpcmd=
chmodcmd=$chmodprog
chowncmd=
mvcmd=$mvprog
rmcmd="$rmprog -f"
stripcmd=
src=
dst=
dir_arg=
dst_arg=
copy_on_change=false
no_target_directory=
usage="\
Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE
or: $0 [OPTION]... SRCFILES... DIRECTORY
or: $0 [OPTION]... -t DIRECTORY SRCFILES...
or: $0 [OPTION]... -d DIRECTORIES...
In the 1st form, copy SRCFILE to DSTFILE.
In the 2nd and 3rd, copy all SRCFILES to DIRECTORY.
In the 4th, create DIRECTORIES.
Options:
--help display this help and exit.
--version display version info and exit.
-c (ignored)
-C install only if different (preserve the last data modification time)
-d create directories instead of installing files.
-g GROUP $chgrpprog installed files to GROUP.
-m MODE $chmodprog installed files to MODE.
-o USER $chownprog installed files to USER.
-s $stripprog installed files.
-t DIRECTORY install into DIRECTORY.
-T report an error if DSTFILE is a directory.
Environment variables override the default commands:
CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG
RMPROG STRIPPROG
"
while test $# -ne 0; do
case $1 in
-c) ;;
-C) copy_on_change=true;;
-d) dir_arg=true;;
-g) chgrpcmd="$chgrpprog $2"
shift;;
--help) echo "$usage"; exit $?;;
-m) mode=$2
case $mode in
*' '* | *' '* | *'
'* | *'*'* | *'?'* | *'['*)
echo "$0: invalid mode: $mode" >&2
exit 1;;
esac
shift;;
-o) chowncmd="$chownprog $2"
shift;;
-s) stripcmd=$stripprog;;
-t) dst_arg=$2
shift;;
-T) no_target_directory=true;;
--version) echo "$0 $scriptversion"; exit $?;;
--) shift
break;;
-*) echo "$0: invalid option: $1" >&2
exit 1;;
*) break;;
esac
shift
done
if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then
# When -d is used, all remaining arguments are directories to create.
# When -t is used, the destination is already specified.
# Otherwise, the last argument is the destination. Remove it from $@.
for arg
do
if test -n "$dst_arg"; then
# $@ is not empty: it contains at least $arg.
set fnord "$@" "$dst_arg"
shift # fnord
fi
shift # arg
dst_arg=$arg
done
fi
if test $# -eq 0; then
if test -z "$dir_arg"; then
echo "$0: no input file specified." >&2
exit 1
fi
# It's OK to call `install-sh -d' without argument.
# This can happen when creating conditional directories.
exit 0
fi
if test -z "$dir_arg"; then
trap '(exit $?); exit' 1 2 13 15
# Set umask so as not to create temps with too-generous modes.
# However, 'strip' requires both read and write access to temps.
case $mode in
# Optimize common cases.
*644) cp_umask=133;;
*755) cp_umask=22;;
*[0-7])
if test -z "$stripcmd"; then
u_plus_rw=
else
u_plus_rw='% 200'
fi
cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;;
*)
if test -z "$stripcmd"; then
u_plus_rw=
else
u_plus_rw=,u+rw
fi
cp_umask=$mode$u_plus_rw;;
esac
fi
for src
do
# Protect names starting with `-'.
case $src in
-*) src=./$src;;
esac
if test -n "$dir_arg"; then
dst=$src
dstdir=$dst
test -d "$dstdir"
dstdir_status=$?
else
# Waiting for this to be detected by the "$cpprog $src $dsttmp" command
# might cause directories to be created, which would be especially bad
# if $src (and thus $dsttmp) contains '*'.
if test ! -f "$src" && test ! -d "$src"; then
echo "$0: $src does not exist." >&2
exit 1
fi
if test -z "$dst_arg"; then
echo "$0: no destination specified." >&2
exit 1
fi
dst=$dst_arg
# Protect names starting with `-'.
case $dst in
-*) dst=./$dst;;
esac
# If destination is a directory, append the input filename; won't work
# if double slashes aren't ignored.
if test -d "$dst"; then
if test -n "$no_target_directory"; then
echo "$0: $dst_arg: Is a directory" >&2
exit 1
fi
dstdir=$dst
dst=$dstdir/`basename "$src"`
dstdir_status=0
else
# Prefer dirname, but fall back on a substitute if dirname fails.
dstdir=`
(dirname "$dst") 2>/dev/null ||
expr X"$dst" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$dst" : 'X\(//\)[^/]' \| \
X"$dst" : 'X\(//\)$' \| \
X"$dst" : 'X\(/\)' \| . 2>/dev/null ||
echo X"$dst" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'
`
test -d "$dstdir"
dstdir_status=$?
fi
fi
obsolete_mkdir_used=false
if test $dstdir_status != 0; then
case $posix_mkdir in
'')
# Create intermediate dirs using mode 755 as modified by the umask.
# This is like FreeBSD 'install' as of 1997-10-28.
umask=`umask`
case $stripcmd.$umask in
# Optimize common cases.
*[2367][2367]) mkdir_umask=$umask;;
.*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;;
*[0-7])
mkdir_umask=`expr $umask + 22 \
- $umask % 100 % 40 + $umask % 20 \
- $umask % 10 % 4 + $umask % 2
`;;
*) mkdir_umask=$umask,go-w;;
esac
# With -d, create the new directory with the user-specified mode.
# Otherwise, rely on $mkdir_umask.
if test -n "$dir_arg"; then
mkdir_mode=-m$mode
else
mkdir_mode=
fi
posix_mkdir=false
case $umask in
*[123567][0-7][0-7])
# POSIX mkdir -p sets u+wx bits regardless of umask, which
# is incompatible with FreeBSD 'install' when (umask & 300) != 0.
;;
*)
tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$
trap 'ret=$?; rmdir "$tmpdir/d" "$tmpdir" 2>/dev/null; exit $ret' 0
if (umask $mkdir_umask &&
exec $mkdirprog $mkdir_mode -p -- "$tmpdir/d") >/dev/null 2>&1
then
if test -z "$dir_arg" || {
# Check for POSIX incompatibilities with -m.
# HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or
# other-writeable bit of parent directory when it shouldn't.
# FreeBSD 6.1 mkdir -m -p sets mode of existing directory.
ls_ld_tmpdir=`ls -ld "$tmpdir"`
case $ls_ld_tmpdir in
d????-?r-*) different_mode=700;;
d????-?--*) different_mode=755;;
*) false;;
esac &&
$mkdirprog -m$different_mode -p -- "$tmpdir" && {
ls_ld_tmpdir_1=`ls -ld "$tmpdir"`
test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1"
}
}
then posix_mkdir=:
fi
rmdir "$tmpdir/d" "$tmpdir"
else
# Remove any dirs left behind by ancient mkdir implementations.
rmdir ./$mkdir_mode ./-p ./-- 2>/dev/null
fi
trap '' 0;;
esac;;
esac
if
$posix_mkdir && (
umask $mkdir_umask &&
$doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir"
)
then :
else
# The umask is ridiculous, or mkdir does not conform to POSIX,
# or it failed possibly due to a race condition. Create the
# directory the slow way, step by step, checking for races as we go.
case $dstdir in
/*) prefix='/';;
-*) prefix='./';;
*) prefix='';;
esac
eval "$initialize_posix_glob"
oIFS=$IFS
IFS=/
$posix_glob set -f
set fnord $dstdir
shift
$posix_glob set +f
IFS=$oIFS
prefixes=
for d
do
test -z "$d" && continue
prefix=$prefix$d
if test -d "$prefix"; then
prefixes=
else
if $posix_mkdir; then
(umask=$mkdir_umask &&
$doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break
# Don't fail if two instances are running concurrently.
test -d "$prefix" || exit 1
else
case $prefix in
*\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;;
*) qprefix=$prefix;;
esac
prefixes="$prefixes '$qprefix'"
fi
fi
prefix=$prefix/
done
if test -n "$prefixes"; then
# Don't fail if two instances are running concurrently.
(umask $mkdir_umask &&
eval "\$doit_exec \$mkdirprog $prefixes") ||
test -d "$dstdir" || exit 1
obsolete_mkdir_used=true
fi
fi
fi
if test -n "$dir_arg"; then
{ test -z "$chowncmd" || $doit $chowncmd "$dst"; } &&
{ test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } &&
{ test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false ||
test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1
else
# Make a couple of temp file names in the proper directory.
dsttmp=$dstdir/_inst.$$_
rmtmp=$dstdir/_rm.$$_
# Trap to clean up those temp files at exit.
trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0
# Copy the file name to the temp name.
(umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") &&
# and set any options; do chmod last to preserve setuid bits.
#
# If any of these fail, we abort the whole thing. If we want to
# ignore errors from any of these, just make sure not to ignore
# errors from the above "$doit $cpprog $src $dsttmp" command.
#
{ test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } &&
{ test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } &&
{ test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } &&
{ test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } &&
# If -C, don't bother to copy if it wouldn't change the file.
if $copy_on_change &&
old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` &&
new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` &&
eval "$initialize_posix_glob" &&
$posix_glob set -f &&
set X $old && old=:$2:$4:$5:$6 &&
set X $new && new=:$2:$4:$5:$6 &&
$posix_glob set +f &&
test "$old" = "$new" &&
$cmpprog "$dst" "$dsttmp" >/dev/null 2>&1
then
rm -f "$dsttmp"
else
# Rename the file to the real destination.
$doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null ||
# The rename failed, perhaps because mv can't rename something else
# to itself, or perhaps because mv is so ancient that it does not
# support -f.
{
# Now remove or move aside any old file at destination location.
# We try this two ways since rm can't unlink itself on some
# systems and the destination file might be busy for other
# reasons. In this case, the final cleanup might fail but the new
# file should still install successfully.
{
test ! -f "$dst" ||
$doit $rmcmd -f "$dst" 2>/dev/null ||
{ $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null &&
{ $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; }
} ||
{ echo "$0: cannot unlink or rename $dst" >&2
(exit 1); exit 1
}
} &&
# Now rename the file to the real destination.
$doit $mvcmd "$dsttmp" "$dst"
}
fi || exit 1
trap '' 0
fi
done
# Local variables:
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:

367
missing Executable file
View File

@ -0,0 +1,367 @@
#! /bin/sh
# Common stub for a few missing GNU programs while installing.
scriptversion=2006-05-10.23
# Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004, 2005, 2006
# Free Software Foundation, Inc.
# Originally by Fran,cois Pinard <pinard@iro.umontreal.ca>, 1996.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
if test $# -eq 0; then
echo 1>&2 "Try \`$0 --help' for more information"
exit 1
fi
run=:
sed_output='s/.* --output[ =]\([^ ]*\).*/\1/p'
sed_minuso='s/.* -o \([^ ]*\).*/\1/p'
# In the cases where this matters, `missing' is being run in the
# srcdir already.
if test -f configure.ac; then
configure_ac=configure.ac
else
configure_ac=configure.in
fi
msg="missing on your system"
case $1 in
--run)
# Try to run requested program, and just exit if it succeeds.
run=
shift
"$@" && exit 0
# Exit code 63 means version mismatch. This often happens
# when the user try to use an ancient version of a tool on
# a file that requires a minimum version. In this case we
# we should proceed has if the program had been absent, or
# if --run hadn't been passed.
if test $? = 63; then
run=:
msg="probably too old"
fi
;;
-h|--h|--he|--hel|--help)
echo "\
$0 [OPTION]... PROGRAM [ARGUMENT]...
Handle \`PROGRAM [ARGUMENT]...' for when PROGRAM is missing, or return an
error status if there is no known handling for PROGRAM.
Options:
-h, --help display this help and exit
-v, --version output version information and exit
--run try to run the given command, and emulate it if it fails
Supported PROGRAM values:
aclocal touch file \`aclocal.m4'
autoconf touch file \`configure'
autoheader touch file \`config.h.in'
autom4te touch the output file, or create a stub one
automake touch all \`Makefile.in' files
bison create \`y.tab.[ch]', if possible, from existing .[ch]
flex create \`lex.yy.c', if possible, from existing .c
help2man touch the output file
lex create \`lex.yy.c', if possible, from existing .c
makeinfo touch the output file
tar try tar, gnutar, gtar, then tar without non-portable flags
yacc create \`y.tab.[ch]', if possible, from existing .[ch]
Send bug reports to <bug-automake@gnu.org>."
exit $?
;;
-v|--v|--ve|--ver|--vers|--versi|--versio|--version)
echo "missing $scriptversion (GNU Automake)"
exit $?
;;
-*)
echo 1>&2 "$0: Unknown \`$1' option"
echo 1>&2 "Try \`$0 --help' for more information"
exit 1
;;
esac
# Now exit if we have it, but it failed. Also exit now if we
# don't have it and --version was passed (most likely to detect
# the program).
case $1 in
lex|yacc)
# Not GNU programs, they don't have --version.
;;
tar)
if test -n "$run"; then
echo 1>&2 "ERROR: \`tar' requires --run"
exit 1
elif test "x$2" = "x--version" || test "x$2" = "x--help"; then
exit 1
fi
;;
*)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
# We have it, but it failed.
exit 1
elif test "x$2" = "x--version" || test "x$2" = "x--help"; then
# Could not run --version or --help. This is probably someone
# running `$TOOL --version' or `$TOOL --help' to check whether
# $TOOL exists and not knowing $TOOL uses missing.
exit 1
fi
;;
esac
# If it does not exist, or fails to run (possibly an outdated version),
# try to emulate it.
case $1 in
aclocal*)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`acinclude.m4' or \`${configure_ac}'. You might want
to install the \`Automake' and \`Perl' packages. Grab them from
any GNU archive site."
touch aclocal.m4
;;
autoconf)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`${configure_ac}'. You might want to install the
\`Autoconf' and \`GNU m4' packages. Grab them from any GNU
archive site."
touch configure
;;
autoheader)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`acconfig.h' or \`${configure_ac}'. You might want
to install the \`Autoconf' and \`GNU m4' packages. Grab them
from any GNU archive site."
files=`sed -n 's/^[ ]*A[CM]_CONFIG_HEADER(\([^)]*\)).*/\1/p' ${configure_ac}`
test -z "$files" && files="config.h"
touch_files=
for f in $files; do
case $f in
*:*) touch_files="$touch_files "`echo "$f" |
sed -e 's/^[^:]*://' -e 's/:.*//'`;;
*) touch_files="$touch_files $f.in";;
esac
done
touch $touch_files
;;
automake*)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`Makefile.am', \`acinclude.m4' or \`${configure_ac}'.
You might want to install the \`Automake' and \`Perl' packages.
Grab them from any GNU archive site."
find . -type f -name Makefile.am -print |
sed 's/\.am$/.in/' |
while read f; do touch "$f"; done
;;
autom4te)
echo 1>&2 "\
WARNING: \`$1' is needed, but is $msg.
You might have modified some files without having the
proper tools for further handling them.
You can get \`$1' as part of \`Autoconf' from any GNU
archive site."
file=`echo "$*" | sed -n "$sed_output"`
test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"`
if test -f "$file"; then
touch $file
else
test -z "$file" || exec >$file
echo "#! /bin/sh"
echo "# Created by GNU Automake missing as a replacement of"
echo "# $ $@"
echo "exit 0"
chmod +x $file
exit 1
fi
;;
bison|yacc)
echo 1>&2 "\
WARNING: \`$1' $msg. You should only need it if
you modified a \`.y' file. You may need the \`Bison' package
in order for those modifications to take effect. You can get
\`Bison' from any GNU archive site."
rm -f y.tab.c y.tab.h
if test $# -ne 1; then
eval LASTARG="\${$#}"
case $LASTARG in
*.y)
SRCFILE=`echo "$LASTARG" | sed 's/y$/c/'`
if test -f "$SRCFILE"; then
cp "$SRCFILE" y.tab.c
fi
SRCFILE=`echo "$LASTARG" | sed 's/y$/h/'`
if test -f "$SRCFILE"; then
cp "$SRCFILE" y.tab.h
fi
;;
esac
fi
if test ! -f y.tab.h; then
echo >y.tab.h
fi
if test ! -f y.tab.c; then
echo 'main() { return 0; }' >y.tab.c
fi
;;
lex|flex)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified a \`.l' file. You may need the \`Flex' package
in order for those modifications to take effect. You can get
\`Flex' from any GNU archive site."
rm -f lex.yy.c
if test $# -ne 1; then
eval LASTARG="\${$#}"
case $LASTARG in
*.l)
SRCFILE=`echo "$LASTARG" | sed 's/l$/c/'`
if test -f "$SRCFILE"; then
cp "$SRCFILE" lex.yy.c
fi
;;
esac
fi
if test ! -f lex.yy.c; then
echo 'main() { return 0; }' >lex.yy.c
fi
;;
help2man)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified a dependency of a manual page. You may need the
\`Help2man' package in order for those modifications to take
effect. You can get \`Help2man' from any GNU archive site."
file=`echo "$*" | sed -n "$sed_output"`
test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"`
if test -f "$file"; then
touch $file
else
test -z "$file" || exec >$file
echo ".ab help2man is required to generate this page"
exit 1
fi
;;
makeinfo)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified a \`.texi' or \`.texinfo' file, or any other file
indirectly affecting the aspect of the manual. The spurious
call might also be the consequence of using a buggy \`make' (AIX,
DU, IRIX). You might want to install the \`Texinfo' package or
the \`GNU make' package. Grab either from any GNU archive site."
# The file to touch is that specified with -o ...
file=`echo "$*" | sed -n "$sed_output"`
test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"`
if test -z "$file"; then
# ... or it is the one specified with @setfilename ...
infile=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'`
file=`sed -n '
/^@setfilename/{
s/.* \([^ ]*\) *$/\1/
p
q
}' $infile`
# ... or it is derived from the source name (dir/f.texi becomes f.info)
test -z "$file" && file=`echo "$infile" | sed 's,.*/,,;s,.[^.]*$,,'`.info
fi
# If the file does not exist, the user really needs makeinfo;
# let's fail without touching anything.
test -f $file || exit 1
touch $file
;;
tar)
shift
# We have already tried tar in the generic part.
# Look for gnutar/gtar before invocation to avoid ugly error
# messages.
if (gnutar --version > /dev/null 2>&1); then
gnutar "$@" && exit 0
fi
if (gtar --version > /dev/null 2>&1); then
gtar "$@" && exit 0
fi
firstarg="$1"
if shift; then
case $firstarg in
*o*)
firstarg=`echo "$firstarg" | sed s/o//`
tar "$firstarg" "$@" && exit 0
;;
esac
case $firstarg in
*h*)
firstarg=`echo "$firstarg" | sed s/h//`
tar "$firstarg" "$@" && exit 0
;;
esac
fi
echo 1>&2 "\
WARNING: I can't seem to be able to run \`tar' with the given arguments.
You may want to install GNU tar or Free paxutils, or check the
command line arguments."
exit 1
;;
*)
echo 1>&2 "\
WARNING: \`$1' is needed, and is $msg.
You might have modified some files without having the
proper tools for further handling them. Check the \`README' file,
it often tells you about the needed prerequisites for installing
this package. You may also peek at any GNU archive site, in case
some other package would contain this missing \`$1' program."
exit 1
;;
esac
exit 0
# Local variables:
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:

203
src/Makefile.am Normal file
View File

@ -0,0 +1,203 @@
## Process this file with automake to produce Makefile.in
liboptic_sources= \
drv_optic_common.c \
drv_optic_calc.c \
drv_optic_goi.c \
drv_optic_fcsi.c \
drv_optic_mm.c \
drv_optic_mpd.c \
drv_optic_bert.c \
drv_optic_tx.c \
drv_optic_rx.c \
drv_optic_omu.c \
drv_optic_bosa.c \
drv_optic_cal.c \
drv_optic_dcdc_apd.c \
drv_optic_dcdc_core.c \
drv_optic_dcdc_ddr.c \
drv_optic_ldo.c \
drv_optic_ll_fcsi.c \
drv_optic_ll_status.c \
drv_optic_ll_sys_gpon.c \
drv_optic_ll_octrlg.c \
drv_optic_ll_gpio.c \
drv_optic_ll_pll.c \
drv_optic_ll_rx.c \
drv_optic_ll_tx.c \
drv_optic_ll_mm.c \
drv_optic_ll_mpd.c \
drv_optic_ll_bert.c \
drv_optic_ll_gtc.c \
drv_optic_ll_dcdc_apd.c \
drv_optic_ll_dcdc_core.c \
drv_optic_ll_dcdc_ddr.c \
drv_optic_ll_sys1.c \
drv_optic_ll_int.c \
drv_optic_ll_simulator.c \
drv_optic_linux.c \
drv_optic_devio.c \
drv_optic_base.c \
drv_optic_cli.c \
drv_optic_cli_misc.c \
drv_optic_cli_core.c
liboptic_interface_headers= \
include/drv_optic_std_defs.h \
include/drv_optic_error.h \
include/drv_optic_resource.h \
include/drv_optic_interface.h \
include/drv_optic_devio.h \
include/drv_optic_base.h \
include/drv_optic_goi_interface.h \
include/drv_optic_fcsi_interface.h \
include/drv_optic_mm_interface.h \
include/drv_optic_mpd_interface.h \
include/drv_optic_bert_interface.h \
include/drv_optic_omu_interface.h \
include/drv_optic_bosa_interface.h \
include/drv_optic_cal_interface.h \
include/drv_optic_event_interface.h \
include/drv_optic_dcdc_apd_interface.h \
include/drv_optic_dcdc_core_interface.h \
include/drv_optic_dcdc_ddr_interface.h \
include/drv_optic_ldo_interface.h
liboptic_extra_headers= \
drv_optic_debug.h \
drv_optic_api.h \
drv_optic_common.h \
drv_optic_fcsi.h \
drv_optic_tx.h \
drv_optic_rx.h \
drv_optic_dcdc_apd.h \
drv_optic_dcdc_core.h \
drv_optic_dcdc_ddr.h \
drv_optic_calc.h \
drv_optic_mpd.h \
drv_optic_mm.h \
drv_optic_bosa.h \
drv_optic_ll_fcsi.h \
drv_optic_ll_status.h \
drv_optic_ll_sys_gpon.h \
drv_optic_ll_octrlg.h \
drv_optic_ll_gpio.h \
drv_optic_ll_pll.h \
drv_optic_ll_rx.h \
drv_optic_ll_tx.h \
drv_optic_ll_mm.h \
drv_optic_ll_bert.h \
drv_optic_ll_gtc.h \
drv_optic_ll_mpd.h \
drv_optic_ll_dcdc_apd.h \
drv_optic_ll_dcdc_core.h \
drv_optic_ll_dcdc_ddr.h \
drv_optic_ll_sys1.h \
drv_optic_ll_int.h \
drv_optic_ll_simulator.h \
drv_optic_timer.h \
drv_optic_cli_core.h \
drv_optic_register.h \
drv_optic_reg_base.h \
drv_optic_reg_pma.h \
drv_optic_reg_pma_int200.h \
drv_optic_reg_pma_intrx.h \
drv_optic_reg_pma_inttx.h \
drv_optic_reg_status.h \
drv_optic_reg_sys_gpon.h \
drv_optic_reg_octrlg.h \
drv_optic_reg_gtc.h \
drv_optic_reg_gtc_pma.h \
drv_optic_reg_dcdc.h \
drv_optic_reg_sys1.h \
drv_optic_reg_fcsic.h \
drv_optic_reg_fcsi_base.h \
drv_optic_reg_fcsi_txbosa.h \
drv_optic_reg_fcsi_txomu.h \
drv_optic_reg_fcsi_rxbosa.h \
drv_optic_reg_fcsi_rxomu.h \
drv_optic_reg_fcsi_mm.h \
drv_optic_reg_fcsi_vdac.h \
drv_optic_reg_fcsi_bfd.h \
drv_optic_reg_fcsi_cbias.h \
drv_optic_reg_fcsi_vdll.h
bin_PROGRAMS =
EXTRA_DIST = \
$(liboptic_sources) \
$(liboptic_interface_headers) \
$(liboptic_extra_headers) \
$(optic_headers)
if ENABLE_LINUX
if !INCLUDE_REMOTE_ONLY_ONU
bin_PROGRAMS += mod_optic.ko
endif
#mod_optic_SOURCES = $(liboptic_sources)
mod_optic_kodir = /include
mod_optic_ko_HEADERS = $(liboptic_interface_headers)
else !ENABLE_LINUX
lib_LIBRARIES = liboptic.a
liboptic_a_SOURCES = $(liboptic_sources)
endif !ENABLE_LINUX
if !OPTIC_LIBRARY
AM_CFLAGS= -DLINUX
else
AM_CFLAGS= -Wall -Wno-unused-parameter -Wno-unused-variable -Os \
-ffunction-sections -fdata-sections -funit-at-a-time
endif
AM_CPPFLAGS = -Wall -Wextra \
-I@srcdir@ \
-I@top_srcdir@/.. \
@IFXOS_INCLUDE_PATH@ \
-I@srcdir@/include
if EVENT_LOGGER_DEBUG
AM_CFLAGS += @EVENT_LOGGER_INCL_PATH@
endif
liboptic_a_CFLAGS=$(AM_CFLAGS)
if ENABLE_LINUX
clean-generic:
@echo "Cleanup Linux 2.6.x kernel object build"
@- find . -name ".*.cmd" | xargs rm -f
@- find . -name "*.o" | xargs rm -f
@- rm -f Module.symvers Kbuild
@- rm -rf .tmp_versions *.mod.c *.order
# linux 2.6 kernel object
# linux 2.6 kernel object - dummy to force dependencies
mod_optic_ko_SOURCES = ../ChangeLog
mod_optic_ko_OBJS = "$(subst .c,.o,$(filter %.c,$(liboptic_sources)))"
mod_optic.ko: $(liboptic_sources)
@echo -e "mod_optic: Making Linux 2.6.x kernel object"
if test ! -e drv_optic_common.c ; then \
echo "copy source files (as links only!)"; \
for f in $(filter %.c,$(liboptic_sources)); do \
mkdir -p $(PWD)/`dirname $$f`/ ; \
cp -sf $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
done \
fi
@echo -e "# mod_optic: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
@echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
@echo -e "$(subst .ko,,$@)-y := $(mod_optic_ko_OBJS)" >> $(PWD)/Kbuild
@echo -e "EXTRA_CFLAGS := $(liboptic_a_CFLAGS) -DHAVE_CONFIG_H -I@abs_srcdir@ -I@abs_srcdir@/include $(IFXOS_INCLUDE_PATH)" >> $(PWD)/Kbuild
$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
endif ENABLE_LINUX
lint:
@flint -vm \
+libdir\(@KERNEL_INCL_PATH@/*\) \
-i$(shell dirname `$(CC) -print-file-name=include`)/include \
-i@top_srcdir@ std_lx.lnt env-cw6.lnt $(AM_CPPFLAGS)\
$(AM_CFLAGS) -D__KERNEL__ -DMODULE $(liboptic_sources)

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_api_h
#define _drv_optic_api_h
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
Internally used functions to control the optical interface.
@{
*/
/** \addtogroup OPTIC_COMMON_INTERNAL Optic Common Driver Interface - Internal
@{
*/
/* exclude some parts from SWIG generation */
#ifndef SWIG
#include "drv_optic_std_defs.h"
#include "ifxos_thread.h"
#include "ifxos_event.h"
#include "ifxos_select.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
#include "drv_optic_debug.h"
#include "drv_optic_goi_interface.h"
#include "drv_optic_fcsi_interface.h"
#include "drv_optic_mm_interface.h"
#include "drv_optic_mpd_interface.h"
#include "drv_optic_bert_interface.h"
#include "drv_optic_omu_interface.h"
#include "drv_optic_bosa_interface.h"
#include "drv_optic_cal_interface.h"
#include "drv_optic_dcdc_apd_interface.h"
#include "drv_optic_dcdc_core_interface.h"
#include "drv_optic_dcdc_ddr_interface.h"
#include "drv_optic_ldo_interface.h"
EXTERN_C_BEGIN
#endif /* SWIG */
#ifdef INCLUDE_DEBUG_SUPPORT
enum optic_errorcode optic_debuglevel_set ( struct optic_device *p_dev,
const struct optic_debuglevel
*param );
enum optic_errorcode optic_debuglevel_get ( struct optic_device *p_dev,
struct optic_debuglevel *param );
#endif
enum optic_errorcode optic_version_get ( struct optic_device *p_dev,
struct optic_versionstring *param );
enum optic_errorcode optic_register_set ( struct optic_device *p_dev,
const struct optic_reg_set *param );
enum optic_errorcode optic_register_get ( struct optic_device *p_dev,
const struct optic_reg_get_in
*param_in,
struct optic_reg_get_out
*param_out );
enum optic_errorcode optic_reset ( struct optic_device *p_dev );
enum optic_errorcode optic_reconfig ( struct optic_device *p_dev );
enum optic_errorcode optic_mode_set ( struct optic_device *p_dev,
const struct optic_mode *param);
enum optic_errorcode optic_isr_register ( struct optic_device *p_dev,
const struct optic_register
*param );
/* GOI block -> drv_optic_goi_interface.h, drv_optic_goi.c */
enum optic_errorcode goi_init ( struct optic_device *p_dev );
enum optic_errorcode goi_init_ctrl ( struct optic_control *p_ctrl );
enum optic_errorcode goi_cfg_set ( struct optic_device *p_dev,
const struct optic_goi_config *param );
enum optic_errorcode goi_cfg_get ( struct optic_device *p_dev,
struct optic_goi_config *param );
enum optic_errorcode goi_range_cfg_set ( struct optic_device *p_dev,
const struct optic_range_config
*param );
enum optic_errorcode goi_range_cfg_get ( struct optic_device *p_dev,
struct optic_range_config *param );
enum optic_errorcode goi_table_set ( struct optic_device *p_dev,
const struct optic_transfer_table_set
*param );
enum optic_errorcode goi_table_get ( struct optic_device *p_dev,
const struct optic_transfer_table_get_in
*param_in,
struct optic_transfer_table_get_out
*param_out );
enum optic_errorcode goi_status_get ( struct optic_device *p_dev,
struct optic_status *param );
enum optic_errorcode goi_ext_status_get ( struct optic_device *p_dev,
struct optic_ext_status *param );
enum optic_errorcode goi_lts_cfg_set ( struct optic_device *p_dev,
const struct optic_lts_config *param );
enum optic_errorcode goi_lts_cfg_get ( struct optic_device *p_dev,
struct optic_lts_config *param );
#ifndef SWIG
enum optic_errorcode goi_lts_trigger ( void );
#endif
enum optic_errorcode goi_video_cfg_set ( struct optic_device *p_dev,
const struct optic_video_config
*param );
enum optic_errorcode goi_video_cfg_get ( struct optic_device *p_dev,
struct optic_video_config *param );
enum optic_errorcode goi_video_enable ( struct optic_device *p_dev );
enum optic_errorcode goi_video_disable ( struct optic_device *p_dev );
enum optic_errorcode goi_video_status_get ( struct optic_device *p_dev,
struct optic_video_status *param );
enum optic_errorcode goi_mm_interval_cfg_set ( struct optic_device *p_dev,
const struct optic_mm_interval_config *param );
/* FCSI block -> drv_optic_fcsi_interface.h, drv_optic_fcsi.c */
enum optic_errorcode fcsi_cfg_set ( struct optic_device *p_dev,
const struct optic_fcsi_config *param );
enum optic_errorcode fcsi_cfg_get ( struct optic_device *p_dev,
struct optic_fcsi_config *param );
/* DCDC APD block -> drv_optic_dcdc_apd_interface.h, drv_optic_dcdc_apd.c */
enum optic_errorcode dcdc_apd_cfg_set ( struct optic_device *p_dev,
const struct optic_dcdc_apd_config
*param );
enum optic_errorcode dcdc_apd_cfg_get ( struct optic_device *p_dev,
struct optic_dcdc_apd_config *param );
enum optic_errorcode dcdc_apd_enable ( struct optic_device *p_dev );
enum optic_errorcode dcdc_apd_disable ( struct optic_device *p_dev );
#ifndef SWIG
bool dcdc_apd_disabled (void);
#endif
enum optic_errorcode dcdc_apd_status_get ( struct optic_device *p_dev,
struct optic_dcdc_apd_status
*param );
/* DCDC CORE block -> drv_optic_dcdc_core_interface.h, drv_optic_dcdc_core.c */
enum optic_errorcode dcdc_core_cfg_set ( struct optic_device *p_dev,
const struct optic_dcdc_core_config
*param );
enum optic_errorcode dcdc_core_cfg_get ( struct optic_device *p_dev,
struct optic_dcdc_core_config *param );
enum optic_errorcode dcdc_core_enable ( struct optic_device *p_dev );
enum optic_errorcode dcdc_core_disable ( struct optic_device *p_dev );
enum optic_errorcode dcdc_core_status_get ( struct optic_device *p_dev,
struct optic_dcdc_core_status
*param );
/* LDO block -> drv_optic_ldo_interface.h, drv_optic_ldo.c */
enum optic_errorcode ldo_enable ( struct optic_device *p_dev );
enum optic_errorcode ldo_disable ( struct optic_device *p_dev );
enum optic_errorcode ldo_status_get ( struct optic_device *p_dev,
struct optic_ldo_status *param );
/* MM block -> drv_optic_mm_interface.h, drv_optic_mm.c */
enum optic_errorcode mm_cfg_set ( struct optic_device *p_dev,
const struct optic_mm_config *param );
enum optic_errorcode mm_cfg_get ( struct optic_device *p_dev,
struct optic_mm_config *param );
enum optic_errorcode mm_die_temperature_get ( struct optic_device *p_dev,
struct optic_temperature
*param );
enum optic_errorcode mm_laser_temperature_get ( struct optic_device *p_dev,
struct optic_temperature
*param );
enum optic_errorcode mm_1490_optical_voltage_get ( struct optic_device *p_dev,
struct optic_voltage_fine
*param );
enum optic_errorcode mm_1490_optical_current_get ( struct optic_device *p_dev,
struct optic_current_fine
*param );
enum optic_errorcode mm_1490_optical_power_get ( struct optic_device *p_dev,
struct optic_power *param );
enum optic_errorcode mm_1550_optical_voltage_get ( struct optic_device *p_dev,
struct optic_voltage_fine
*param );
enum optic_errorcode mm_1550_electrical_voltage_get ( struct optic_device
*p_dev,
struct optic_voltage_fine
*param );
/* MPD block -> drv_optic_mpd_interface.h, drv_optic_mpd.c */
enum optic_errorcode mpd_cfg_set ( struct optic_device *p_dev,
const struct optic_mpd_config *param );
enum optic_errorcode mpd_cfg_get ( struct optic_device *p_dev,
struct optic_mpd_config *param );
enum optic_errorcode mpd_trace_get ( struct optic_device *p_dev,
struct optic_mpd_trace *param );
/* BERT block -> drv_optic_bert_interface.h, drv_optic_bert.c */
enum optic_errorcode bert_cfg_set ( struct optic_device *p_dev,
const struct optic_bert_cfg *param );
enum optic_errorcode bert_cfg_get ( struct optic_device *p_dev,
struct optic_bert_cfg *param );
enum optic_errorcode bert_enable ( struct optic_device *p_dev );
enum optic_errorcode bert_disable ( struct optic_device *p_dev );
enum optic_errorcode bert_synchronize ( struct optic_device *p_dev );
enum optic_errorcode bert_status_get ( struct optic_device *p_dev,
struct optic_bert_status *param );
enum optic_errorcode bert_mode_set ( struct optic_device *p_dev,
const struct optic_bert_mode *param );
enum optic_errorcode bert_counter_reset ( struct optic_device *p_dev );
/* OMU block -> drv_optic_omu_interface.h, drv_optic_omu.c */
enum optic_errorcode omu_init ( struct optic_control *p_ctrl );
enum optic_errorcode omu_cfg_set ( struct optic_device *p_dev,
const struct optic_omu_config *param );
enum optic_errorcode omu_cfg_get ( struct optic_device *p_dev,
struct optic_omu_config *param );
enum optic_errorcode omu_rx_enable ( struct optic_device *p_dev );
enum optic_errorcode omu_rx_disable ( struct optic_device *p_dev );
enum optic_errorcode omu_tx_enable ( struct optic_device *p_dev );
enum optic_errorcode omu_tx_disable ( struct optic_device *p_dev );
enum optic_errorcode omu_rx_status_get ( struct optic_device *p_dev,
struct optic_omu_rx_status_get
*param );
enum optic_errorcode omu_tx_status_get ( struct optic_device *p_dev,
struct optic_omu_tx_status_get
*param );
/* BOSA block -> drv_optic_bosa_interface.h, drv_optic_bosa.c */
enum optic_errorcode bosa_rx_cfg_set ( struct optic_device *p_dev,
const struct optic_bosa_rx_config
*param );
enum optic_errorcode bosa_rx_cfg_get ( struct optic_device
*p_dev,
struct optic_bosa_rx_config *param );
enum optic_errorcode bosa_tx_cfg_set ( struct optic_device *p_dev,
const struct optic_bosa_tx_config
*param );
enum optic_errorcode bosa_tx_cfg_get ( struct optic_device *p_dev,
struct optic_bosa_tx_config *param );
enum optic_errorcode bosa_rx_enable ( struct optic_device *p_dev );
enum optic_errorcode bosa_rx_disable ( struct optic_device *p_dev );
enum optic_errorcode bosa_tx_enable ( struct optic_device *p_dev );
enum optic_errorcode bosa_tx_disable ( struct optic_device *p_dev );
enum optic_errorcode bosa_powerlevel_set ( struct optic_device *p_dev,
const struct optic_bosa_powerlevel
*param );
enum optic_errorcode bosa_powerlevel_get ( struct optic_device *p_dev,
struct optic_bosa_powerlevel
*param );
enum optic_errorcode bosa_loopmode_set ( struct optic_device *p_dev,
const struct optic_bosa_loopmode
*param);
enum optic_errorcode bosa_loopmode_get ( struct optic_device *p_dev,
struct optic_bosa_loopmode *param);
enum optic_errorcode bosa_rx_status_get ( struct optic_device *p_dev,
struct optic_bosa_rx_status *param );
enum optic_errorcode bosa_tx_status_get ( struct optic_device *p_dev,
struct optic_bosa_tx_status *param );
enum optic_errorcode bosa_alarm_status_get ( struct optic_device *p_dev,
struct optic_bosa_alarm *param );
enum optic_errorcode bosa_alarm_status_clear ( struct optic_device *p_dev );
enum optic_errorcode bosa_int_coeff_get ( struct optic_device *p_dev,
struct optic_int_coeff *param );
enum optic_errorcode bosa_stable_get ( struct optic_device *p_dev,
struct optic_stable *param );
/* Calibration block -> drv_optic_cal_interface.h, drv_optic_cal.c */
enum optic_errorcode cal_debug_enable ( struct optic_device *p_dev );
enum optic_errorcode cal_debug_disable ( struct optic_device *p_dev );
enum optic_errorcode cal_mm_enable ( struct optic_device *p_dev );
enum optic_errorcode cal_mm_disable ( struct optic_device *p_dev );
enum optic_errorcode cal_debug_status_get ( struct optic_device *p_dev,
struct optic_debug_status *param );
enum optic_errorcode cal_laser_age_get ( struct optic_device *p_dev,
struct optic_timestamp *param );
enum optic_errorcode cal_ibiasimod_table_set ( struct optic_device *p_dev,
const struct optic_ibiasimod_set
*param );
enum optic_errorcode cal_ibiasimod_table_get ( struct optic_device *p_dev,
const struct
optic_ibiasimod_get_in
*param_in,
struct optic_ibiasimod_get_out
*param_out );
enum optic_errorcode cal_laserref_table_set ( struct optic_device *p_dev,
const struct optic_laserref_set
*param );
enum optic_errorcode cal_laserref_table_get ( struct optic_device *p_dev,
const struct optic_laserref_get_in
*param_in,
struct optic_laserref_get_out
*param_out );
enum optic_errorcode cal_vapd_table_set ( struct optic_device *p_dev,
const struct optic_vapd_set *param );
enum optic_errorcode cal_vapd_table_get ( struct optic_device *p_dev,
const struct optic_vapd_get_in
*param_in,
struct optic_vapd_get_out
*param_out );
enum optic_errorcode cal_corr_table_set ( struct optic_device *p_dev,
const struct optic_corr_set *param );
enum optic_errorcode cal_corr_table_get ( struct optic_device *p_dev,
const struct optic_corr_get_in
*param_in,
struct optic_corr_get_out
*param_out );
enum optic_errorcode cal_tcorrext_table_set ( struct optic_device *p_dev,
const struct optic_tcorrext_set
*param );
enum optic_errorcode cal_tcorrext_table_get ( struct optic_device *p_dev,
const struct optic_tcorrext_get_in
*param_in,
struct optic_tcorrext_get_out
*param_out );
enum optic_errorcode cal_init_bias_current_set ( struct optic_device *p_dev,
const struct optic_bias
*param );
enum optic_errorcode cal_init_bias_current_get ( struct optic_device *p_dev,
struct optic_bias *param );
enum optic_errorcode cal_init_mod_current_set ( struct optic_device *p_dev,
const struct optic_mod
*param );
enum optic_errorcode cal_init_mod_current_get ( struct optic_device *p_dev,
struct optic_mod *param );
enum optic_errorcode cal_actual_bias_current_get ( struct optic_device *p_dev,
struct optic_bias *param );
enum optic_errorcode cal_actual_mod_current_get ( struct optic_device *p_dev,
struct optic_mod *param );
enum optic_errorcode cal_mpd_gain_set ( struct optic_device *p_dev,
const struct optic_gain_set *param );
enum optic_errorcode cal_mpd_gain_get ( struct optic_device *p_dev,
const struct optic_gain_get_in
*param_in,
struct optic_gain_get_out *param_out );
enum optic_errorcode cal_mpd_dbg_gain_set ( struct optic_device *p_dev,
const struct optic_dbg_gain
*param );
enum optic_errorcode cal_mpd_dbg_gain_get ( struct optic_device *p_dev,
struct optic_dbg_gain *param );
enum optic_errorcode cal_mpd_cal_current_set ( struct optic_device *p_dev,
const struct optic_cal_set
*param );
enum optic_errorcode cal_mpd_cal_current_get ( struct optic_device *p_dev,
const struct optic_cal_get_in
*param_in,
struct optic_cal_get_out
*param_out );
enum optic_errorcode cal_mpd_dbg_cal_current_set ( struct optic_device *p_dev,
const struct optic_dbg_cal
*param );
enum optic_errorcode cal_mpd_dbg_cal_current_get ( struct optic_device *p_dev,
struct optic_dbg_cal
*param );
enum optic_errorcode cal_mpd_ref_codeword_set ( struct optic_device *p_dev,
const struct optic_refcw_set
*param );
enum optic_errorcode cal_mpd_ref_codeword_get ( struct optic_device *p_dev,
const struct optic_refcw_get_in
*param_in,
struct optic_refcw_get_out
*param_out );
enum optic_errorcode cal_mpd_dbg_ref_codeword_set ( struct optic_device *p_dev,
const struct optic_dbg_refcw
*param );
enum optic_errorcode cal_mpd_dbg_ref_codeword_get ( struct optic_device *p_dev,
struct optic_dbg_refcw
*param );
enum optic_errorcode cal_mpd_tia_offset_set ( struct optic_device *p_dev,
const struct optic_tia_offset_set
*param );
enum optic_errorcode cal_mpd_tia_offset_get ( struct optic_device *p_dev,
const struct optic_tia_offset_get_in
*param_in,
struct optic_tia_offset_get_out
*param_out );
enum optic_errorcode cal_mpd_dbg_tia_offset_set ( struct optic_device *p_dev,
const struct optic_dbg_tia_offset
*param );
enum optic_errorcode cal_mpd_dbg_tia_offset_get ( struct optic_device *p_dev,
struct optic_dbg_tia_offset
*param );
enum optic_errorcode cal_mpd_tia_offset_find ( struct optic_device *p_dev );
enum optic_errorcode cal_mpd_level_set ( struct optic_device *p_dev,
const struct optic_level_set *param );
enum optic_errorcode cal_mpd_level_get ( struct optic_device *p_dev,
const struct optic_level_get_in
*param_in,
struct optic_level_get_out
*param_out );
enum optic_errorcode cal_mpd_level_find ( struct optic_device *p_dev,
const struct optic_level_find_in
*param_in,
struct optic_level_find_out
*param_out );
enum optic_errorcode cal_mpd_cfratio_set ( struct optic_device *p_dev,
const struct optic_cfratio
*param );
enum optic_errorcode cal_mpd_cfratio_get ( struct optic_device *p_dev,
struct optic_cfratio *param );
enum optic_errorcode cal_mpd_cfratio_find ( struct optic_device *p_dev );
enum optic_errorcode cal_mpd_powersave_set ( struct optic_device *p_dev,
const struct optic_powersave
*param );
enum optic_errorcode cal_mpd_powersave_get ( struct optic_device *p_dev,
struct optic_powersave *param );
enum optic_errorcode cal_fcsi_predriver_set ( struct optic_device *p_dev,
const struct optic_fcsi_predriver
*param );
enum optic_errorcode cal_fcsi_predriver_get ( struct optic_device *p_dev,
struct optic_fcsi_predriver
*param );
enum optic_errorcode cal_dcdc_apd_voltage_set ( struct optic_device *p_dev,
const struct optic_voltage
*param );
enum optic_errorcode cal_dcdc_apd_voltage_get ( struct optic_device *p_dev,
struct optic_voltage *param );
enum optic_errorcode cal_dcdc_core_voltage_set ( struct optic_device *p_dev,
const struct optic_voltage
*param );
enum optic_errorcode cal_dcdc_core_voltage_get ( struct optic_device *p_dev,
struct optic_voltage *param );
enum optic_errorcode cal_dcdc_ddr_voltage_set ( struct optic_device *p_dev,
const struct optic_voltage
*param );
enum optic_errorcode cal_dcdc_ddr_voltage_get ( struct optic_device *p_dev,
struct optic_voltage *param );
enum optic_errorcode cal_laser_delay_set ( struct optic_device *p_dev,
const struct optic_laserdelay
*param );
enum optic_errorcode cal_laser_delay_get ( struct optic_device *p_dev,
struct optic_laserdelay *param );
enum optic_errorcode cal_mm_dark_corr_set ( struct optic_device *p_dev,
const struct optic_rssi_1490_dark
*param );
enum optic_errorcode cal_mm_dark_corr_get ( struct optic_device *p_dev,
struct optic_rssi_1490_dark
*param );
enum optic_errorcode cal_mm_dark_corr_find ( struct optic_device *p_dev );
enum optic_errorcode cal_fusing_get ( struct optic_device *p_dev,
struct optic_fusing *param );
enum optic_errorcode cal_tscalref_set( struct optic_device *p_dev,
const struct optic_tscalref *param );
enum optic_errorcode cal_tscalref_get( struct optic_device *p_dev,
struct optic_tscalref *param );
enum optic_errorcode cal_measure_rssi_1490_get ( struct optic_device *p_dev,
const struct
optic_measure_rssi_1490_get_in
*param_in,
struct
optic_measure_rssi_1490_get_out
*param_out );
enum optic_errorcode cal_current_offset_get( struct optic_device *p_dev,
struct optic_current_fine *param );
enum optic_errorcode cal_rx_offset_set ( struct optic_device *p_dev,
const struct optic_rx_offset *param );
enum optic_errorcode cal_rx_offset_get ( struct optic_device *p_dev,
struct optic_rx_offset *param );
enum optic_errorcode cal_rx_offset_find ( struct optic_device *p_dev );
/*! @} */
/*! @} */
#ifndef SWIG
EXTERN_C_END
#endif
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifdef HAVE_CONFIG_H
#include "drv_optic_config.h"
#endif
#ifdef OPTIC_LIBRARY
#include <stddefs.h>
#include <stdlib.h>
#include "config.h"
#include "device_io.h"
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "sys_tickedtimer.h"
#include "drv_optic_timer.h"
#include "drv_optic_dcdc_apd.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_fcsi.h"
#include "drv_optic_reg_base.h"
#include "drv_optic_reg_sys_gpon.h"
#include "drv_optic_reg_status.h"
#include "drv_optic_reg_dcdc.h"
#include "drv_optic_reg_sys1.h"
#include "drv_optic_reg_pma.h"
#include "drv_optic_reg_gtc_pma.h"
#include "drv_optic_reg_pma_int200.h"
#include "drv_optic_reg_pma_intrx.h"
#include "drv_optic_reg_pma_inttx.h"
#include "drv_optic_reg_fcsic.h"
#include "drv_optic_ll_int.h"
#define IFXOS_BlockAlloc IFXOS_MemAlloc
#define IFXOS_BlockFree IFXOS_MemFree
long optic_open ( void *ctrl,
const char *appendix );
int optic_ioctl ( void *dev,
unsigned int cmd,
ulong_t arg );
int optic_poll ( void *dev );
struct optic_device g_optic_device;
struct optic_reg_pma *pma = (struct optic_reg_pma *)OPTIC_PMA_BASE;
struct optic_reg_dcdc *dcdc_core =
(struct optic_reg_dcdc *)OPTIC_DCDC_CORE_BASE;
struct optic_reg_dcdc *dcdc_ddr =
(struct optic_reg_dcdc *) OPTIC_DCDC_DDR_BASE;
struct optic_reg_dcdc *dcdc_apd =
(struct optic_reg_dcdc *) OPTIC_DCDC_APD_BASE;
struct optic_reg_fcsic *fcsic =
(struct optic_reg_fcsic *) OPTIC_FCSIC_BASE;
struct optic_reg_gtc_pma *gtc_pma =
(struct optic_reg_gtc_pma *) OPTIC_GTC_PMA_BASE;
struct optic_reg_pma_int200 *pma_int200 =
(struct optic_reg_pma_int200 *)OPTIC_PMA_INT200_BASE;
struct optic_reg_pma_intrx *pma_intrx =
(struct optic_reg_pma_intrx *) OPTIC_PMA_INTRX_BASE;
struct optic_reg_pma_inttx *pma_inttx =
(struct optic_reg_pma_inttx *) OPTIC_PMA_INTTX_BASE;
struct optic_reg_status *status =
(struct optic_reg_status *)OPTIC_STATUS_BASE;
struct optic_reg_sys1 *sys1 =
(struct optic_reg_sys1 *)OPTIC_SYS1_BASE;
struct optic_reg_sys_gpon *sys_gpon =
(struct optic_reg_sys_gpon *) OPTIC_SYS_GPON_BASE;
struct optic_reg_fcsi *fcsi;
STATIC struct timer_list optic_timer[OPTIC_TIMER_GLOBAL_MAX];
#ifdef INCLUDE_DEBUG_SUPPORT
enum optic_debug_levels optic_debug_level = OPTIC_DBG_ERR;
#endif
STATIC unsigned int major_number;
/**
Open the device.
At the first time:
- allocating internal memory for each new device
- initialize the device
\return
- 0 - if error,
- device context - if success
*/
long optic_open ( void *ctrl, const char *appendix)
{
struct optic_device *p_dev = &g_optic_device;
(void) appendix;
if (optic_device_open (&optic_ctrl[0], p_dev) !=
OPTIC_STATUS_OK) {
optic_device_close ( p_dev );
return -1;
}
return (long) p_dev;
}
/**
Release the device.
\param inode pointer to the inode
\param filp pointer to the file descriptor
\return
- 0 - on success
- otherwise error code
*/
int optic_release (long p_dev)
{
optic_device_close ((struct optic_device *) p_dev );
return 0;
}
void optic_irq_poll (void)
{
int i;
struct optic_control *p_ctrl = &optic_ctrl[0];
if (p_ctrl->config.mode != OPTIC_OMU) {
for (i = 0; i < 3; i++)
optic_ll_int_bosa_handle ( i, NULL,
p_ctrl->calibrate.thresh_codeword_los,
p_ctrl->calibrate.thresh_codeword_ovl,
&(p_ctrl->state.interrupts) );
} else {
optic_ll_int_omu_handle ( OPTIC_IRQ_TYPE_GPIO_SD ,
p_ctrl->config.callback_isr,
p_ctrl->config.omu.signal_detect_port,
&(p_ctrl->state.interrupts) );
}
}
/**
The select function of the driver.
A user space program may sleep until the driver it wakes up.
\param
filp - pointer to the file descriptor
\param
wait - wait table
\return
- POLLIN - data available
- 0 - no data
- POLLERR - device pointer is zero
*/
int optic_poll ( void *dev )
{
return 0;
}
static void cp ( struct optic_device *p_dev,
const struct optic_entry *table,
struct optic_exchange *p_exchange,
uint32_t nr,
uint8_t *buf )
{
/*
if (_IOC_DIR(table[nr].id) & _IOC_WRITE)
memcpy(buf, p_exchange->p_data, table[nr].size_in);
*/
if (table[nr].p_entry0) {
p_exchange->error = table[nr].p_entry0 (p_dev);
} else
if (table[nr].p_entry1) {
p_exchange->error = table[nr].p_entry1 (p_dev,
p_exchange->p_data);
} else
if (table[nr].p_entry2) {
p_exchange->error = table[nr].p_entry2 (p_dev,
p_exchange->p_data,
p_exchange->p_data);
}
if (_IOC_DIR(table[nr].id) & _IOC_READ) {
/*memcpy(p_exchange->p_data, buf, table[nr].size_out);*/
p_exchange->length = table[nr].size_out;
} else {
p_exchange->length = 0;
}
}
/**
Configuration and control interface of the device.
\param inode pointer to the inode
\param filp pointer to the file descriptor
\param cmd function id's
\param arg optional argument
\return
- 0 and positive values - success,
- negative value - ioctl failed
*/
int optic_ioctl ( void *dev, unsigned int cmd, ulong_t arg)
{
struct optic_device *p_dev = (struct optic_device *) dev;
uint8_t *buf = NULL;
struct optic_exchange *p_exchange = (struct optic_exchange *) arg;
uint32_t type = _IOC_TYPE(cmd);
uint32_t nr = _IOC_NR(cmd);
uint32_t dir = _IOC_DIR(cmd);
(void) dir;
if ((type == OPTIC_MAGIC) && (nr < OPTIC_MAX) &&
(nr == _IOC_NR(optic_function_table[nr].id))) {
cp ( p_dev, optic_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_GOI_MAGIC) && (nr < OPTIC_GOI_MAX) &&
(nr == _IOC_NR(goi_function_table[nr].id))) {
cp ( p_dev, goi_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_FCSI_MAGIC) && (nr < OPTIC_FCSI_MAX) &&
(nr == _IOC_NR(fcsi_function_table[nr].id))) {
cp ( p_dev, fcsi_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_MM_MAGIC) && (nr < OPTIC_MM_MAX) &&
(nr == _IOC_NR(mm_function_table[nr].id))) {
cp ( p_dev, mm_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_MPD_MAGIC) && (nr < OPTIC_MPD_MAX) &&
(nr == _IOC_NR(mpd_function_table[nr].id))) {
cp ( p_dev, mpd_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_BERT_MAGIC) && (nr < OPTIC_BERT_MAX) &&
(nr == _IOC_NR(bert_function_table[nr].id))) {
cp ( p_dev, bert_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_OMU_MAGIC) && (nr < OPTIC_OMU_MAX) &&
(nr == _IOC_NR(omu_function_table[nr].id))) {
cp ( p_dev, omu_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_BOSA_MAGIC) && (nr < OPTIC_BOSA_MAX) &&
(nr == _IOC_NR(bosa_function_table[nr].id))) {
cp ( p_dev, bosa_function_table, p_exchange, nr, buf );
} else
#if (OPTIC_OCAL_SUPPORT == ACTIVE)
if ((type == OPTIC_CAL_MAGIC) && (nr < OPTIC_CAL_MAX) &&
(nr == _IOC_NR(cal_function_table[nr].id))) {
cp ( p_dev, cal_function_table, p_exchange, nr, buf );
} else
#endif
if ((type == OPTIC_DCDC_APD_MAGIC) && (nr < OPTIC_DCDC_APD_MAX) &&
(nr == _IOC_NR(dcdc_apd_function_table[nr].id))) {
cp ( p_dev, dcdc_apd_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_DCDC_CORE_MAGIC) && (nr < OPTIC_DCDC_CORE_MAX) &&
(nr == _IOC_NR(dcdc_core_function_table[nr].id))) {
cp ( p_dev, dcdc_core_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_DCDC_DDR_MAGIC) && (nr < OPTIC_DCDC_DDR_MAX) &&
(nr == _IOC_NR(dcdc_ddr_function_table[nr].id))) {
cp ( p_dev, dcdc_ddr_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_LDO_MAGIC) && (nr < OPTIC_LDO_MAX) &&
(nr == _IOC_NR(ldo_function_table[nr].id))) {
cp ( p_dev, ldo_function_table, p_exchange, nr, buf );
}
return 0;
}
void optic_udelay ( uint32_t u_sec )
{
udelay(u_sec);
}
#ifdef OPTIC_STATE_HOTPLUG_EVENT
void optic_hotplug_state ( const enum optic_statetype state )
{
(void) state;
}
#endif
void optic_hotplug_timestamp (const uint32_t timestamp)
{
(void) timestamp;
}
int optic_signal_pending(void *sig)
{
(void) sig;
return 0;
}
void optic_irq_set ( enum optic_manage_mode mode,
enum optic_activation act )
{
(void) mode;
(void) act;
return;
}
void optic_enable_irq (uint32_t irq)
{
(void) irq;
}
void optic_disable_irq (uint32_t irq)
{
(void) irq;
}
/** Timer Handler
\param timer Indicates the timer index
*/
STATIC void optic_timer_handler(unsigned long timer_no)
{
struct optic_control *ctrl = &optic_ctrl[0];
if (timer_no == OPTIC_TIMER_ID_MEASURE)
optic_timer_measure (ctrl);
if (timer_no == OPTIC_TIMER_ID_APD_ADAPT)
optic_timer_dcdc_apd_adapt (ctrl);
}
/**
Start optic timer
\param timer Timer Reference
\param timeout Timeout in mseconds.
*/
void optic_timer_start(const uint32_t timer_no, uint32_t timeout)
{
timer_start (&optic_timer[timer_no], timeout, 0);
}
/**
Stop Timer
\param timer_no Timer Index
*/
void optic_timer_stop(const uint32_t timer_no)
{
tick_timer_stop (&optic_timer[timer_no]);
}
void* optic_malloc (size_t size, uint32_t id)
{
static char temp_corr[8850];
static char temp_nom[1024];
printf ("Optic malloc #%d %d bytes\n", id, size);
switch (id) {
case MEM_TBL_TEMP_CORR:
return &temp_corr;
case MEM_TBL_TEMP_NOM:
return &temp_nom;
default:
return NULL;
}
}
/**
Initialize the driver module.
\return
- 0 on success
- Error code
\remarks
Called by the kernel.
*/
int optic_init ( void )
{
int i;
#ifdef INCLUDE_DEBUG_SUPPORT
optic_debug_level = (enum optic_debug_levels) OPTIC_DBG_WRN;
#endif
OPTIC_DEBUG_MSG("%s", &optic_whatversion[4]);
major_number = DEVIO_driver_install ( (DEVIO_device_open)optic_open,
(DEVIO_device_close)optic_release,
NULL,
NULL,
optic_ioctl,
optic_poll );
if (major_number == (unsigned)-1) {
OPTIC_DEBUG_ERR("can't get major %d", major_number);
return -1;
}
memset(optic_ctrl, 0x00, sizeof(optic_ctrl));
if (DEVIO_device_add ( &optic_ctrl[0],
"/dev/optic0",
major_number) == (unsigned int)IFX_ERROR) {
OPTIC_DEBUG_ERR("unable to create device.");
return -1;
}
if (optic_context_init (&optic_ctrl[0], 0 ) !=
OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("unable to create device.");
return -1;
}
for (i = 0; i < OPTIC_TIMER_GLOBAL_MAX; i++) {
timer_init ( &optic_timer[i], optic_timer_handler, i);
}
return 0;
}
void optic_irq_omu_init ( const uint8_t signal_detect_irq )
{
(void) signal_detect_irq;
return;
}
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, BERT Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_BERT_INTERNAL BERT Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_bert_interface.h"
#include "drv_optic_mpd.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_bert.h"
#include "drv_optic_ll_tx.h"
#include "drv_optic_ll_gtc.h"
#include "drv_optic_ll_pll.h"
/**
The bert_cfg_set function is used to provide configurations for the
BERT unit within the GOI module.
\param param.pattern_mode this parameter selects, if the BERT
pattern generator/receiver shall be
used (0) or the GTCPMAIF buffer (1).
\param param.pattern_type selects 4 pattern types for the
BERT pattern generator.
= 0: clock pattern (configurable
frequency and duty cycle)
= 1: PRBS pattern (multiple types)
= 2: fixed pattern (32 bit)
= 3: all-zero
\param param.pattern_length selects the length of each part of
the BERT pattern
\param param.fixed_pattern fixed pattern definition
\param param.clock_period selects the period of a clock
sub-pattern
\param param.clock_high selects the clock sub-pattern
duty cycle
\param param.prbs_type selects the PRBS pattern type
\param param.datarate_tx_high selects the transmit data rate
- false: 1.244 Gbit/s
- true : 2.488 Gbit/s
\param param.datarate_rx_high selects the treceive data rate
- false: 1.244 Gbit/s
- true : 2.488 Gbit/s
\param param.loop_enable enables loop back of transmitted
data to the receiver
- pattern_type:
(0): 1st part of the pattern -> BERT_CONTROL.mux_sel1
(1): 2nd part of the pattern -> BERT_CONTROL.mux_sel2
(2): 3rd part of the pattern -> BERT_CONTROL.mux_sel3
(3): 4th part of the pattern -> BERT_CONTROL.mux_sel4
- pattern_length:
if (pattern_mode == 0)
(0): write to BERT_CNT.endcounter_1
(1): write to BERT_CNT.endcounter_2
(2): write to BERT_CNT.endcounter_3
(3): write to BERT_CNT.endcounter_4
if (pattern_mode == 1)
pattern_length[0] -> GTCPMAIF.LTSC.LEN
- fixed_pattern:
if (pattern_mode == 0)
fixed_pattern[0] -> BERT_PATTERN.fixedin
if (pattern_mode == 1)
fixed_pattern[0] -> GTCPMAIF.LTSDATA0
fixed_pattern[1] -> GTCPMAIF.LTSDATA1
...
fixed_pattern[19] -> GTCPMAIF.LTSDATA19
- clock_period: -> BERT_CLK.genclkperiod
- clock_high: -> BERT_CLK.genclkhi
- prbs_type:
switch(nPrbsType):
- case(7) : BERT_CONTROL.prbs_sel = 7
- case(11): BERT_CONTROL.prbs_sel = 11
- case(15): BERT_CONTROL.prbs_sel = 15
- case(18): BERT_CONTROL.prbs_sel = 18
- case(21): BERT_CONTROL.prbs_sel = 21
- case(23): BERT_CONTROL.prbs_sel = 23
- case(31): BERT_CONTROL.prbs_sel = 31
- default: error message
- datarate_tx_high:
- true : BERT_CONTROL.MODE_2G5_TX = 1
- false: BERT_CONTROL.MODE_2G5_TX = 0
- datarate_rx_high
- true : BERT_CONTROL.MODE_2G5_RX = 1
- false: BERT_CONTROL.MODE_2G5_RX = 0
- loop_enable:
- true : BERT_CONTROL.LOOPBACK_ENABLE = 1
- false: BERT_CONTROL.LOOPBACK_ENABLE = 0
*/
enum optic_errorcode bert_cfg_set ( struct optic_device *p_dev,
const struct optic_bert_cfg *param )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
uint32_t fixed_pattern[20];
uint8_t i;
(void) p_dev;
if (param == NULL)
return OPTIC_STATUS_ERR;
switch (param->pattern_mode) {
case 0:
ret = optic_ll_bert_analyzer_set ( OPTIC_ENABLE );
fixed_pattern[0] = (param->fixed_pattern[0] << 24) |
(param->fixed_pattern[1] << 16) |
(param->fixed_pattern[2] << 8) |
(param->fixed_pattern[3]);
break;
case 1:
ret = optic_ll_bert_analyzer_set ( OPTIC_DISABLE );
for (i=0; i<(param->pattern_length[0]+3)/4; i++) {
fixed_pattern[i] = (param->fixed_pattern[i+0] << 24) |
(param->fixed_pattern[i+1] << 16) |
(param->fixed_pattern[i+2] << 8) |
(param->fixed_pattern[i+3]);
}
break;
default:
return OPTIC_STATUS_POOR;
}
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_muxsel_set ( param->pattern_type[0],
param->pattern_type[1],
param->pattern_type[2],
param->pattern_type[3] );
if (ret != OPTIC_STATUS_OK)
return ret;
if (param->pattern_mode == 0) {
/* BERT mode */
ret = optic_ll_bert_pattern_set ( fixed_pattern[0],
param->pattern_length[0],
param->pattern_length[1],
param->pattern_length[2],
param->pattern_length[3] );
} else {
/* GTC-PMA mode */
ret = optic_ll_gtc_pattern_config_set ( OPTIC_PATTERNMODE_BERT,
fixed_pattern,
param->pattern_length[0]
);
}
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_clk_set ( param->clock_period,
param->clock_high );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_prbs_set ( param->prbs_type );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_speed_set ( param->datarate_tx_high,
param->datarate_rx_high );
if (ret != OPTIC_STATUS_OK)
return ret;
if (param->loop_enable)
ret = optic_ll_bert_loop_set (OPTIC_ENABLE );
else
ret = optic_ll_bert_loop_set (OPTIC_DISABLE );
return ret;
}
/**
The bert_cfg_get function is used to read back the basic configuration
of measurement unit within the GOI module.
Hardware programming details: See bert_cfg_set.
*/
enum optic_errorcode bert_cfg_get ( struct optic_device *p_dev,
struct optic_bert_cfg *param)
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
enum optic_activation mode;
enum optic_patternmode gtc_mode;
uint32_t fixed_pattern[20];
uint8_t i;
(void) p_dev;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset(param, 0x00, sizeof(struct optic_bert_cfg));
ret = optic_ll_bert_analyzer_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->pattern_mode = (mode == OPTIC_ENABLE) ? 0 : 1;
ret = optic_ll_bert_muxsel_get ( &(param->pattern_type[0]),
&(param->pattern_type[1]),
&(param->pattern_type[2]),
&(param->pattern_type[3]) );
if (ret != OPTIC_STATUS_OK)
return ret;
if (param->pattern_mode == 0) {
/* BERT mode */
ret = optic_ll_bert_pattern_get (
&(fixed_pattern[0]),
&(param->pattern_length[0]),
&(param->pattern_length[1]),
&(param->pattern_length[2]),
&(param->pattern_length[3]) );
param->fixed_pattern[0] = (fixed_pattern[0] >> 24) & 0xFF;
param->fixed_pattern[1] = (fixed_pattern[0] >> 16) & 0xFF;
param->fixed_pattern[2] = (fixed_pattern[0] >> 8) & 0xFF;
param->fixed_pattern[3] = (fixed_pattern[0]) & 0xFF;
} else {
/* GTC-PMA mode */
ret = optic_ll_gtc_pattern_config_get ( &gtc_mode,
fixed_pattern,
&(param->
pattern_length[0]) );
if (gtc_mode != OPTIC_PATTERNMODE_BERT)
ret = OPTIC_STATUS_ERR;
else {
for (i=0; i<(param->pattern_length[0]+3)/4; i++) {
if (i >= sizeof(fixed_pattern))
break;
if ((i*4 +3) >=
((uint8_t) sizeof(param->fixed_pattern)))
break;
param->fixed_pattern[i*4 +0] =
(fixed_pattern[i] >> 24) & 0xFF;
param->fixed_pattern[i*4 +1] =
(fixed_pattern[i] >> 16) & 0xFF;
param->fixed_pattern[i*4 +2] =
(fixed_pattern[i] >> 8) & 0xFF;
param->fixed_pattern[i*4 +3] =
(fixed_pattern[i]) & 0xFF;
}
}
}
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_clk_get ( &param->clock_period,
&param->clock_high );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_prbs_get ( &param->prbs_type );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_speed_get ( &param->datarate_tx_high,
&param->datarate_rx_high );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_loop_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->loop_enable = (mode == OPTIC_ENABLE) ? true : false;
return ret;
}
/**
The bert_enable function is used to enable the
BERT unit within the GOI module.
*/
enum optic_errorcode bert_enable ( struct optic_device *p_dev )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
enum optic_errorcode ret = OPTIC_STATUS_OK;
bool invert;
ret = optic_ll_bert_counter_config (OPTIC_BERTCNT_RESET);
if (ret != OPTIC_STATUS_OK)
return ret;
if (is_falcon_chip_a1x())
invert = true;
else
invert = !(p_ctrl->config.bias_polarity_regular);
/* bias path: flip, invert, burst, power forced */
optic_ll_tx_path_activate (OPTIC_BIAS, invert);
if (p_ctrl->config.mode == OPTIC_BOSA &&
is_falcon_chip_a1x() &&
p_ctrl->config.bias_polarity_regular == 0)
/* BIASPATH bit 3 is not working in A12,
therefore data_prg = 0 */
optic_ll_tx_biaspath_data_set (0);
else
optic_ll_tx_biaspath_data_set (0xF);
/* invert modulation polarity is mode dependend */
if (p_ctrl->config.mode == OPTIC_OMU)
invert = !p_ctrl->config.mod_polarity_regular;
else
invert = p_ctrl->config.mod_polarity_regular;
/* data path: flip, invert, burst, power forced */
optic_ll_tx_path_activate (OPTIC_MOD, invert);
ret = optic_ll_bert_analyzer_set (OPTIC_ENABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
/* activate data/bias path for bert */
/* only for datapath enable bert! */
ret = optic_ll_tx_path_bert_set (OPTIC_ENABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_counter_config (OPTIC_BERTCNT_RUN);
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/**
The bert_disable function is used to disable the
BERT unit within the GOI module.
It restores the invert bit settings
*/
enum optic_errorcode bert_disable ( struct optic_device *p_dev )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
enum optic_errorcode ret = OPTIC_STATUS_OK;
ret = optic_ll_bert_counter_config ( OPTIC_BERTCNT_FREEZE );
if (ret != OPTIC_STATUS_OK)
return ret;
/* reset values */
optic_ll_tx_path_init (p_ctrl->config.mode,
!p_ctrl->config.bias_polarity_regular,
!p_ctrl->config.mod_polarity_regular);
ret = optic_ll_bert_analyzer_set (OPTIC_DISABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
/* activate data/bias path for bert */
ret = optic_ll_tx_path_bert_set (OPTIC_DISABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/**
The bert_synchronize function is used to force synchronisation of the
received PRBS pattern to the internal PRBS generator within the GOI module.
*/
enum optic_errorcode bert_synchronize ( struct optic_device *p_dev )
{
(void) p_dev;
optic_ll_bert_sync ();
return OPTIC_STATUS_OK;
}
/**
The bert_status_get function is used to read back the status
of measurement unit within the GOI module.
*/
enum optic_errorcode bert_status_get ( struct optic_device *p_dev,
struct optic_bert_status *param )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
enum optic_activation mode;
(void) p_dev;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset(param, 0x00, sizeof(struct optic_bert_status));
ret = optic_ll_bert_analyzer_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->bert_enable = (mode == OPTIC_ENABLE) ? true : false;
ret = optic_ll_bert_counter_get ( &(param->word_cnt),
&(param->error_cnt) );
if (ret != OPTIC_STATUS_OK)
return ret;
return OPTIC_STATUS_OK;
}
/**
The bert_mode_set function is used to set one of the basic BERT
configurations.
*/
enum optic_errorcode bert_mode_set ( struct optic_device *p_dev,
const struct optic_bert_mode *param )
{
struct optic_bert_cfg bert_cfg;
uint8_t i;
bert_cfg.pattern_mode = 0;
switch (param->mode) {
case OPTIC_BERT_CONST_ZERO:
for (i=0; i<4; i++) {
bert_cfg.pattern_type[i] = 2;
bert_cfg.pattern_length[i] = 1;
bert_cfg.fixed_pattern[i] = 0;
}
bert_cfg.clock_period = 0;
bert_cfg.clock_high = 0;
bert_cfg.prbs_type = 0;
bert_cfg.datarate_tx_high = false;
bert_cfg.datarate_rx_high = false;
bert_cfg.loop_enable = false;
break;
case OPTIC_BERT_CONST_ONE:
for (i=0; i<4; i++) {
bert_cfg.pattern_type[i] = 2;
bert_cfg.pattern_length[i] = 1;
bert_cfg.fixed_pattern[i] = 255;
}
bert_cfg.clock_period = 0;
bert_cfg.clock_high = 0;
bert_cfg.prbs_type = 0;
bert_cfg.datarate_tx_high = false;
bert_cfg.datarate_rx_high = false;
bert_cfg.loop_enable = false;
break;
case OPTIC_BERT_CLOCK:
for (i=0; i<4; i++) {
bert_cfg.pattern_type[i] = 0;
bert_cfg.pattern_length[i] = 0;
bert_cfg.fixed_pattern[i] = 0;
}
bert_cfg.pattern_length[0] = 2;
bert_cfg.clock_period = 4;
bert_cfg.clock_high = 2;
bert_cfg.prbs_type = 0;
bert_cfg.datarate_tx_high = false;
bert_cfg.datarate_rx_high = true;
bert_cfg.loop_enable = false;
break;
case OPTIC_BERT_PRBS7:
case OPTIC_BERT_PRBS11:
case OPTIC_BERT_PRBS15:
case OPTIC_BERT_PRBS18:
case OPTIC_BERT_PRBS21:
case OPTIC_BERT_PRBS23:
case OPTIC_BERT_PRBS31:
for (i=0; i<4; i++) {
bert_cfg.pattern_type[i] = 1;
bert_cfg.pattern_length[i] = 2;
bert_cfg.fixed_pattern[i] = 0;
}
bert_cfg.clock_period = 0;
bert_cfg.clock_high = 0;
bert_cfg.prbs_type = param->mode;
bert_cfg.datarate_tx_high = false;
bert_cfg.datarate_rx_high = false;
bert_cfg.loop_enable = false;
break;
default:
return OPTIC_STATUS_POOR;
}
return bert_cfg_set ( p_dev, &bert_cfg );
}
/**
The bert counters are resetted.
*/
enum optic_errorcode bert_counter_reset ( struct optic_device *p_dev )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
(void) p_dev;
ret = optic_ll_bert_counter_config ( OPTIC_BERTCNT_RESET );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_counter_config ( OPTIC_BERTCNT_RUN );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry bert_function_table[OPTIC_BERT_MAX] =
{
/* 0 */ TE1in (FIO_BERT_CFG_SET, sizeof(struct optic_bert_cfg),
bert_cfg_set),
/* 1 */ TE1out (FIO_BERT_CFG_GET, sizeof(struct optic_bert_cfg),
bert_cfg_get),
/* 2 */ TE0 (FIO_BERT_ENABLE, bert_enable),
/* 3 */ TE0 (FIO_BERT_DISABLE, bert_disable),
/* 4 */ TE0 (FIO_BERT_SYNC, bert_synchronize),
/* 5 */ TE1out (FIO_BERT_STATUS_GET, sizeof(struct optic_bert_status),
bert_status_get),
/* 6 */ TE1in (FIO_BERT_MODE_SET, sizeof(struct optic_bert_mode),
bert_mode_set),
/* 7 */ TE0 (FIO_BERT_CNT_RESET, bert_counter_reset),
};
/*! @} */
/*! @} */

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src/drv_optic_bosa.c Normal file
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@ -0,0 +1,943 @@
/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, BOSA Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_BOSA_INTERNAL BOSA Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_bosa_interface.h"
#include "drv_optic_bosa.h"
#include "drv_optic_calc.h"
#include "drv_optic_fcsi.h"
#include "drv_optic_rx.h"
#include "drv_optic_tx.h"
#include "drv_optic_dcdc_apd.h"
#include "drv_optic_mpd.h"
#include "drv_optic_ll_fcsi.h"
#include "drv_optic_ll_mm.h"
#include "drv_optic_ll_mpd.h"
#include "drv_optic_ll_pll.h"
#include "drv_optic_ll_rx.h"
#include "drv_optic_ll_tx.h"
#include "drv_optic_ll_gpio.h"
#include "drv_optic_ll_int.h"
#include "drv_optic_ll_dcdc_apd.h"
/**
Set the BOSA receiver configuration
*/
enum optic_errorcode bosa_rx_cfg_set ( struct optic_device *p_dev,
const struct optic_bosa_rx_config
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_config_bosa *bosa = &(p_ctrl->config.bosa);
enum optic_errorcode ret = OPTIC_STATUS_OK;
if (param->threshold_lol_set > 100)
return OPTIC_STATUS_POOR;
if (param->threshold_lol_clear > 100)
return OPTIC_STATUS_POOR;
bosa->dead_zone_elimination = param->dead_zone_elimination;
bosa->threshold_lol_set = param->threshold_lol_set;
bosa->threshold_lol_clear = param->threshold_lol_clear;
bosa->threshold_los = param->threshold_los;
bosa->threshold_rx_overload = param->threshold_rx_overload;
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_BOSA_RX] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return ret;
}
/**
Read back the BOSA receiver configuration
*/
enum optic_errorcode bosa_rx_cfg_get ( struct optic_device *p_dev,
struct optic_bosa_rx_config *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_config_bosa *bosa = &(p_ctrl->config.bosa);
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_bosa_rx_config) );
param->dead_zone_elimination = bosa->dead_zone_elimination;
param->threshold_lol_set = bosa->threshold_lol_set;
param->threshold_lol_clear = bosa->threshold_lol_clear;
param->threshold_los = bosa->threshold_los;
param->threshold_rx_overload = bosa->threshold_rx_overload;
return OPTIC_STATUS_OK;
}
/**
Set the BOSA transmitter configuration
*/
enum optic_errorcode bosa_tx_cfg_set ( struct optic_device *p_dev,
const struct optic_bosa_tx_config
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_config_bosa *bosa = &(p_ctrl->config.bosa);
enum optic_errorcode ret = OPTIC_STATUS_OK;
uint8_t i;
bosa->loop_mode = param->loop_mode;
for (i=OPTIC_BIAS; i<=OPTIC_MOD; i++) {
bosa->intcoeff_init[i] = param->intcoeff_init[i];
bosa->updatethreshold[i] = param->updatethreshold[i];
bosa->learnthreshold[i] = param->learnthreshold[i];
bosa->stablethreshold[i] = param->stablethreshold[i];
bosa->resetthreshold[i] = param->resetthreshold[i];
}
bosa->pi_control = param->pi_control;
for (i=0; i<3; i++) {
bosa->p0[i] = param->p0[i];
bosa->p1[i] = param->p1[i];
}
bosa->pth = param->pth;
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_BOSA_TX] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return ret;
}
/**
Read back the BOSA transmitter configuration
*/
enum optic_errorcode bosa_tx_cfg_get ( struct optic_device *p_dev,
struct optic_bosa_tx_config
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_config_bosa *bosa = &(p_ctrl->config.bosa);
uint8_t i;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_bosa_tx_config) );
param->loop_mode = bosa->loop_mode;
for (i=OPTIC_BIAS; i<=OPTIC_MOD; i++) {
param->intcoeff_init[i] = bosa->intcoeff_init[i];
param->updatethreshold[i] = bosa->updatethreshold[i];
param->learnthreshold[i] = bosa->learnthreshold[i];
param->stablethreshold[i] = bosa->stablethreshold[i];
param->resetthreshold[i] = bosa->resetthreshold[i];
}
param->pi_control = bosa->pi_control;
for (i=0; i<3; i++) {
param->p0[i] = bosa->p0[i];
param->p1[i] = bosa->p1[i];
}
param->pth = bosa->pth;
return OPTIC_STATUS_OK;
}
/**
Set the power level
*/
enum optic_errorcode bosa_powerlevel_set ( struct optic_device *p_dev,
const struct optic_bosa_powerlevel
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
/* GPONSW-998: automatic smooth power scaling
* save the old powerlevel, this powerlevel will be
* returned to PLOAM state machine during powerlevel_get call
* if autolevel is switched on
*/
if(p_ctrl->config.measurement.RSSI_autolevel == true)
p_ctrl->calibrate.auto_powerlevel = param->powerlevel ;
return optic_bosa_powerlevel_set ( p_ctrl, param->powerlevel );
}
/**
Read the power level
*/
enum optic_errorcode bosa_powerlevel_get ( struct optic_device *p_dev,
struct optic_bosa_powerlevel
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
memset ( param, 0, sizeof(struct optic_bosa_powerlevel) );
/* in case of automatic smooth power scaling return
the true power level */
param->powerlevel = p_ctrl->calibrate.powerlevel;
return OPTIC_STATUS_OK;
}
/**
Configure the bosa loop mode
*/
enum optic_errorcode bosa_loopmode_set ( struct optic_device *p_dev,
const struct optic_bosa_loopmode
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
enum optic_errorcode ret = OPTIC_STATUS_OK;
struct optic_config_bosa *bosa = &(p_ctrl->config.bosa);
if (bosa->loop_mode == param->loop_mode)
return ret;
bosa->loop_mode = param->loop_mode;
if (p_ctrl->config.monitor.rogue_interburst ||
p_ctrl->config.monitor.rogue_intraburst)
optic_ll_mpd_rogue_int_set (0, 0);
ret = optic_mpd_loopmode ( p_ctrl );
return ret;
}
/**
Reads back loop mode
*/
enum optic_errorcode bosa_loopmode_get ( struct optic_device *p_dev,
struct optic_bosa_loopmode *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
memset ( param, 0, sizeof(struct optic_bosa_loopmode) );
param->loop_mode = p_ctrl->config.bosa.loop_mode;
return OPTIC_STATUS_OK;
}
/**
Enable the BOSA laser receiver input
*/
enum optic_errorcode bosa_rx_enable ( struct optic_device *p_dev )
{
enum optic_errorcode ret;
(void) p_dev;
ret = optic_ll_rx_dsm_switch(OPTIC_ENABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_rx_cdr_bpd(OPTIC_ENABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_rx_afectrl_set ( OPTIC_ENABLE, false );
if (ret != OPTIC_STATUS_OK)
return ret;
return OPTIC_STATUS_OK;
}
/**
Disable the BOSA laser receiver input
*/
enum optic_errorcode bosa_rx_disable ( struct optic_device *p_dev )
{
enum optic_errorcode ret;
(void) p_dev;
/* Switching on/off of RX slice via RSTN of PLL is not allowed
* Switching off RX slice is realized via
* switching off data path from GTC to PMA
*
* To enable the feature:
* "Disable CDR if RX not there but TX eye-measurement wanted"
*
* Disabling of bipolar phase detection must be disabled and
* LOAD bit in TX slice in register PI_CTRL needs to be set,
* in order to keep frequency and phase constant for TX and
* not having any RX CDR.
* (LOAD bit is always set, therefore no function call here)
* */
ret = optic_ll_rx_afectrl_set ( OPTIC_DISABLE, false );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_rx_cdr_bpd(OPTIC_DISABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_rx_dsm_switch(OPTIC_DISABLE);
if (ret != OPTIC_STATUS_OK)
return ret;
return OPTIC_STATUS_OK;
}
/**
Enable the BOSA laser transmitter output
*/
enum optic_errorcode bosa_tx_enable ( struct optic_device *p_dev )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
/* enable rougue ont interrupt */
if ((p_ctrl->config.monitor.rogue_interburst) ||
(p_ctrl->config.monitor.rogue_intraburst))
optic_ll_mpd_rogue_int_set (
p_ctrl->config.monitor.rogue_interburst,
p_ctrl->config.monitor.rogue_intraburst);
optic_ll_int_reset (&(p_ctrl->state.interrupts));
/* GPONSW-909
* Switching on the TX part via PLL reset bit is not allowed!
* For "software rogue" feature, TX shall be switched on by simple
* enabling laser light to fiber via switching on pre driver in PMD.
*
* The enable of pre driver at this position is allowed since
* the pre driver was configured properly already before !!!
* */
return optic_ll_fcsi_predriver_switch ( OPTIC_ENABLE);
}
/**
Disable the BOSA laser transmitter output
*/
enum optic_errorcode bosa_tx_disable ( struct optic_device *p_dev )
{
(void) p_dev;
/* GPONSW-909
* Switching off the TX part via PLL reset bit is not allowed!
* For "software rogue" feature, TX shall be switched off by simple
* "cutting" laser light to fiber via switching off pre driver in PMD
* */
return optic_ll_fcsi_predriver_switch ( OPTIC_DISABLE);
}
/**
Read the BOSA's receiver status
*/
enum optic_errorcode bosa_rx_status_get ( struct optic_device *p_dev,
struct optic_bosa_rx_status
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_interrupts *irq = &(p_ctrl->state.interrupts);
enum optic_activation mode;
struct optic_calibrate *cal = &(p_ctrl->calibrate);
enum optic_errorcode ret = OPTIC_STATUS_OK;
memset ( param, 0, sizeof(struct optic_bosa_rx_status) );
/* read bosa rx state */
ret = optic_ll_pll_module_get ( OPTIC_PLL_RX, &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->rx_enable = (mode == OPTIC_ENABLE) ? true : false;
param->meas_power_1490_rssi = cal->meas_power_1490_rssi;
param->meas_voltage_1490_rssi = cal->meas_voltage_1490_rssi;
param->meas_current_1490_rssi = cal->meas_current_1490_rssi;
param->meas_current_1490_rssi_is_positive =
cal->meas_current_1490_rssi_is_positive;
param->meas_voltage_1550_rssi = cal->meas_voltage_1550_rssi;
param->meas_voltage_1550_rf = cal->meas_voltage_1550_rf;
param->loss_of_signal = irq->signal_lost;
param->loss_of_lock = irq->rx_lock_lost;
return ret;
}
/**
Read the BOSA's transmitter status
*/
enum optic_errorcode bosa_tx_status_get ( struct optic_device *p_dev,
struct optic_bosa_tx_status
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_table_temperature_corr *table =
p_ctrl->table_temperature_corr;
uint16_t tbosa = optic_shift_temp_back (p_ctrl->calibrate.
temperature_ext);
uint16_t temp_index;
enum optic_activation mode, predrv_mode;
enum optic_errorcode ret = OPTIC_STATUS_OK;
memset ( param, 0, sizeof(struct optic_bosa_tx_status) );
/* read bosa tx state */
ret = optic_ll_pll_module_get ( OPTIC_PLL_TX, &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
/* read bosa predriver tx state */
ret = optic_ll_fcsi_predriver_switch_get (&predrv_mode);
if (ret == OPTIC_STATUS_OK && predrv_mode == OPTIC_DISABLE)
mode = OPTIC_DISABLE;
param->tx_enable = (mode == OPTIC_ENABLE) ? true : false;
/** abias/amod */
/* read (actual) bias current */
ret = optic_mpd_bias_get ( p_ctrl, false,
&(param->bias_current) );
if (ret != OPTIC_STATUS_OK)
return ret;
/* read (actual) modulation current */
ret = optic_mpd_mod_get ( p_ctrl, false,
&(param->modulation_current) );
if (ret != OPTIC_STATUS_OK)
return ret;
if (tbosa < p_ctrl->config.range.tabletemp_extcorr_min ||
tbosa > p_ctrl->config.range.tabletemp_extcorr_max) {
param->laser_threshold = 0xFFFF;
param->slope_efficiency = 0xFFFF;
} else {
temp_index = tbosa - p_ctrl->config.range.tabletemp_extcorr_min;
param->laser_threshold = table[temp_index].laserref.ith;
param->slope_efficiency = table[temp_index].laserref.se;
}
return ret;
}
/**
Read the BOSA's alarm status
*/
enum optic_errorcode bosa_alarm_status_get ( struct optic_device *p_dev,
struct optic_bosa_alarm
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
memset ( param, 0, sizeof(struct optic_bosa_alarm) );
param->loss_of_signal = p_ctrl->state.interrupts.signal_lost;
param->loss_of_lock = p_ctrl->state.interrupts.rx_lock_lost;
param->rx_overload = p_ctrl->state.interrupts.signal_overload;
param->laser_overload = p_ctrl->state.interrupts.tx_overcurrent;
param->bias_overload = p_ctrl->state.interrupts.tx_bias_limit;
param->modulation_overload = p_ctrl->state.interrupts.tx_mod_limit;
param->rogue_p0 = p_ctrl->state.interrupts.tx_p0_interburst_alarm;
param->rogue_p1 = p_ctrl->state.interrupts.tx_p1_interburst_alarm;
return OPTIC_STATUS_OK;
}
/**
Clear the BOSA's alarm status
*/
enum optic_errorcode bosa_alarm_status_clear ( struct optic_device *p_dev )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
return optic_ll_int_reset ( &(p_ctrl->state.interrupts) );
}
/**
Read the integration coefficients
*/
enum optic_errorcode bosa_int_coeff_get ( struct optic_device *p_dev,
struct optic_int_coeff *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
uint8_t i;
memset ( param, 0, sizeof(struct optic_int_coeff) );
for (i=OPTIC_BIAS; i<=OPTIC_MOD; i++) {
param->intcoeff[i] = p_ctrl->calibrate.intcoeff[i];
}
return OPTIC_STATUS_OK;
}
/**
Read the stable check for bias and modulation.
*/
enum optic_errorcode bosa_stable_get ( struct optic_device *p_dev,
struct optic_stable *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
uint8_t i;
memset ( param, 0, sizeof(struct optic_stable) );
for (i=OPTIC_BIAS; i<=OPTIC_MOD; i++) {
param->stable[i] = p_ctrl->calibrate.stable[i];
}
return OPTIC_STATUS_OK;
}
/* ----------------------------- NON IOCTL ---------------------------------- */
/**
The bosa_init function is used to initialize the on-chip hardware for
the receive and transmit path of the Bidirectional Optical Subassembly
(BOSA).
1. configure TX FIFO
2. init CDR (RX) <- dead_zone_elimination
3. set LOL thresholds
4. set LOS threshold
5. set RX overload threshold
6. set LSB-MSB flip for RX: data lo & hi, falling & rising edge, monitor
7. set LSB-MSB flip for TX: data path & bias path
8. disable receive data signals to GTC
9. disable receive DAC offset correction
10. configure PI Ctrl (TX)
11. MPD Calibration: optic_ll_mpd_calibrate()
12. Ibias/Imod init + activation dualloop
*/
enum optic_errorcode optic_bosa_init ( struct optic_control *p_ctrl )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
uint16_t temp_index = p_ctrl->config.temp_ref -
p_ctrl->config.range.tabletemp_extnom_min;
enum optic_powerlevel pl = p_ctrl->calibrate.powerlevel;
uint16_t ibias, imod;
bool ignore_error;
static const bool calibrate[2] = { OPTIC_MPD_CALIBRATE_P0,
OPTIC_MPD_CALIBRATE_P1 };
int16_t dac_coarse[2], dac_fine[2];
ignore_error = (p_ctrl->config.run_mode &
(1<<OPTIC_RUNMODE_ERROR_IGNORE)) ? true : false;
ret = optic_ll_pll_laser_set ( OPTIC_DISABLE );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_pll_laser_set: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_fcsi_predriver_update ( pl, &(p_ctrl->config.fcsi) );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_fcsi_predriver_update: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
return ret;
}
/* init APD DCDC */
ret = optic_ll_dcdc_apd_init ();
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_apd_init: %d", ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_dcdc_apd_update ( p_ctrl );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_dcdc_apd_update: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
/* activate APD DCDC */
ret = optic_ll_dcdc_apd_set ( OPTIC_ENABLE );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_apd_start: %d", ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_calc_thresh_current (
p_ctrl->config.measurement.rssi_1490_scal_ref,
p_ctrl->config.bosa.threshold_los,
&(p_ctrl->calibrate.thresh_current_los) );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/calc_thresh_current: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_calc_thresh_current (
p_ctrl->config.measurement.rssi_1490_scal_ref,
p_ctrl->config.bosa.threshold_rx_overload,
&(p_ctrl->calibrate.thresh_current_ovl) );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/calc_thresh_current_1490: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
/* \note: vapd_target has to be set (optic_dcdc_apd_voltage_set)
thresh_current_los, thresh_current_ovl have to be
calculated (optic_calc_thresh_current) */
ret = optic_calc_offset_and_thresh ( p_ctrl );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_calc_current_thresh: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_tx_init (OPTIC_BOSA, p_ctrl->config.bosa.pi_control,
p_ctrl->config.delay_tx_enable,
p_ctrl->config.delay_tx_disable,
p_ctrl->config.size_tx_fifo,
p_ctrl->config.bias_polarity_regular,
p_ctrl->config.mod_polarity_regular);
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_tx_init: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_rx_init ( OPTIC_BOSA,
p_ctrl->config.bosa.dead_zone_elimination,
p_ctrl->config.bosa.threshold_lol_clear,
p_ctrl->config.bosa.threshold_lol_set,
p_ctrl->config.rx_polarity_regular,
&(p_ctrl->calibrate.rx_offset) );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_rx_init: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
p_ctrl->calibrate.ratio_p0 = p_ctrl->config.monitor.ratio_coarse_fine;
p_ctrl->calibrate.ratio_p1 = p_ctrl->config.monitor.ratio_coarse_fine;
ret = optic_mpd_init ( p_ctrl );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_mpd_init: %d", ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
/* init mpd and set dual loop / open loop */
ret = optic_mpd_loopmode ( p_ctrl );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/bosa_dualloop_enable/disable: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
/* A1.1 workaround repeat BOSA fcsi init */
ret = optic_ll_fcsi_init_bosa_2nd ( );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_ll_fcsi_init: %d", ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_powersave_set ( p_ctrl );
if (ret != OPTIC_STATUS_OK)
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
/* BEGIN: do offset and gain correction like in dualloop(): */
/* standard flow: MPD calibration for P0 and P1 */
/* gain correction with offset cancelation */
ret = optic_mpd_calibrate_level ( p_ctrl,
OPTIC_MPD_CALIBRATE_OFFSET, calibrate,
dac_coarse, dac_fine);
if (ret != OPTIC_STATUS_OK)
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
ret = optic_mpd_codeword_calc ( p_ctrl, calibrate,
OPTIC_MPD_CALIBRATE_OFFSET,
dac_coarse, dac_fine );
if (ret != OPTIC_STATUS_OK)
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
/* END: do offset and gain correction like in dualloop(): */
#if (OPTIC_MPD_COARSE_FINE_RATIO_CALC == ACTIVE)
ret = optic_ll_mpd_ratio_measure ( p_ctrl );
if (ret != OPTIC_STATUS_OK)
return ret;
#endif
ibias = p_ctrl->table_temperature_corr[temp_index].ibiasimod.ibias[pl];
imod = p_ctrl->table_temperature_corr[temp_index].ibiasimod.imod[pl];
if (ibias != 0) {
ret = optic_mpd_bias_set ( p_ctrl, ibias );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_mpd_ibias_write: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
if (is_falcon_chip_a2x()){
/*configure the bias low saturation, let choose 90% of the actual resetthreshold*/
ibias = optic_int_div_rounded (ibias * (p_ctrl->config.bosa.resetthreshold[OPTIC_BIAS]), 100);
ibias = optic_int_div_rounded (ibias * 90, 100);
ret = optic_mpd_biaslowsat_set ( p_ctrl, ibias );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_mpd_ibias_write: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
}
}
if (imod != 0) {
ret = optic_mpd_mod_set ( p_ctrl, imod );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_mpd_imod_set: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
}
/* GPONSW-1035 activate predriver via FCSI at the end of init routine */
ret = optic_ll_fcsi_predriver_switch (OPTIC_ENABLE);
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/bosa_tx_enable: %d",
ret);
if (!ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
#if (OPTIC_BOSA_IRQ == ACTIVE)
/* enable interrupts */
ret = optic_ll_int_all_set ( OPTIC_ENABLE );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_int_set: %d",
ret);
return ret;
}
#else
/* disable interrupts */
ret = optic_ll_int_all_set ( OPTIC_DISABLE );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_bosa_init/optic_ll_int_set: %d",
ret);
return ret;
}
#endif
return ret;
}
enum optic_errorcode optic_powerlevel_set ( const uint8_t powerlevel )
{
enum optic_powerlevel pl;
struct optic_control *p_ctrl = &(optic_ctrl[0]);
pl = (enum optic_powerlevel) powerlevel;
/* GPONSW-998: automatic smooth power scaling
* save the old powerlevel, this powerlevel will be
* returned to PLOAM state machine during powerlevel_get call
* if autolevel is switched on
*/
if(p_ctrl->config.measurement.RSSI_autolevel == true)
p_ctrl->calibrate.auto_powerlevel = powerlevel ;
return optic_bosa_powerlevel_set ( p_ctrl, pl );
}
enum optic_errorcode optic_powerlevel_get ( uint8_t *powerlevel )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
enum optic_powerlevel pl;
struct optic_control *p_ctrl = &(optic_ctrl[0]);
if (powerlevel != NULL)
return OPTIC_STATUS_INVAL;
ret = optic_bosa_powerlevel_get ( p_ctrl, &pl );
*powerlevel = (uint8_t) pl;
/* GPONSW-998: automatic smooth power scaling
* save the old powerlevel, this powerlevel will be
* returned to PLOAM state machine during powerlevel_get call
* if autolevel is switched on
*/
if(p_ctrl->config.measurement.RSSI_autolevel == true)
*powerlevel = p_ctrl->calibrate.auto_powerlevel;
return ret;
}
enum optic_errorcode optic_bosa_powerlevel_set ( struct optic_control *p_ctrl,
const enum optic_powerlevel
powerlevel )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
struct optic_calibrate *cal = &(p_ctrl->calibrate);
struct optic_config_fcsi *fcsi = &(p_ctrl->config.fcsi);
int16_t dac_coarse[2], dac_fine[2];
static const bool calibrate[2] = { OPTIC_MPD_CALIBRATE_P0,
OPTIC_MPD_CALIBRATE_P1 };
enum optic_gainbank gainbank;
switch (powerlevel) {
case OPTIC_POWERLEVEL_0:
case OPTIC_POWERLEVEL_1:
case OPTIC_POWERLEVEL_2:
if (cal->powerlevel != powerlevel) {
cal->powerlevel = powerlevel;
if (p_ctrl->config.debug_mode == true)
return OPTIC_STATUS_OK;
ret = optic_powerlevel2gainbank ( powerlevel,
&gainbank );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_fcsi_predriver_update ( powerlevel, fcsi );
if (ret != OPTIC_STATUS_OK)
return ret;
if (IFXOS_MutexGet(&p_ctrl->access.dac_lock) !=
IFX_SUCCESS)
return ret;
ret = optic_mpd_gainctrl_set ( p_ctrl,
gainbank,
OPTIC_CAL_OFF );
if (ret == OPTIC_STATUS_OK)
ret = optic_mpd_tia_offset_set ( p_ctrl,
gainbank );
IFXOS_MutexRelease(&p_ctrl->access.dac_lock);
if (ret != OPTIC_STATUS_OK)
return ret;
/* MPD calibration: with offset cancellation,
for P0 and P1, with ibias/ imod update */
ret = optic_mpd_calibrate_level ( p_ctrl,
false,
calibrate,
dac_coarse,
dac_fine );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_mpd_codeword_calc ( p_ctrl,
calibrate, OPTIC_MPD_CALIBRATE_OFFSET,
dac_coarse, dac_fine);
/* update can throw
OPTIC_STATUS_MPD_UPDATE_THRES_NOT_REACHED */
if (ret == OPTIC_STATUS_OK)
ret = optic_mpd_biasmod_update ( p_ctrl,
OPTIC_BIAS );
if (ret >= OPTIC_STATUS_OK)
ret = optic_mpd_biasmod_update ( p_ctrl,
OPTIC_MOD );
}
break;
default:
return OPTIC_STATUS_POOR;
}
return ret;
}
/**
Read the power level
*/
enum optic_errorcode optic_bosa_powerlevel_get ( struct optic_control *p_ctrl,
enum optic_powerlevel
*powerlevel )
{
if (powerlevel != NULL)
*powerlevel = p_ctrl->calibrate.powerlevel;
return OPTIC_STATUS_OK;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry bosa_function_table[OPTIC_BOSA_MAX] =
{
/* 0 */ TE1in (FIO_BOSA_RX_CFG_SET, sizeof(struct optic_bosa_rx_config),
bosa_rx_cfg_set),
/* 1 */ TE1out (FIO_BOSA_RX_CFG_GET, sizeof(struct optic_bosa_rx_config),
bosa_rx_cfg_get),
/* 2 */ TE1in (FIO_BOSA_TX_CFG_SET, sizeof(struct optic_bosa_tx_config),
bosa_tx_cfg_set),
/* 3 */ TE1out (FIO_BOSA_TX_CFG_GET, sizeof(struct optic_bosa_tx_config),
bosa_tx_cfg_get),
/* 4 */ TE0 (FIO_BOSA_RX_ENABLE, bosa_rx_enable),
/* 5 */ TE0 (FIO_BOSA_RX_DISABLE, bosa_rx_disable),
/* 6 */ TE0 (FIO_BOSA_TX_ENABLE, bosa_tx_enable),
/* 7 */ TE0 (FIO_BOSA_TX_DISABLE, bosa_tx_disable),
/* 8 */ TE1in (FIO_BOSA_POWERLEVEL_SET, sizeof(struct optic_bosa_powerlevel),
bosa_powerlevel_set),
/* 9 */ TE1out (FIO_BOSA_POWERLEVEL_GET, sizeof(struct optic_bosa_powerlevel),
bosa_powerlevel_get),
/* 10 */ TE1in (FIO_BOSA_LOOPMODE_SET, sizeof(struct optic_bosa_loopmode),
bosa_loopmode_set),
/* 11 */ TE1out (FIO_BOSA_LOOPMODE_GET, sizeof(struct optic_bosa_loopmode),
bosa_loopmode_get),
/* 12 */ TE1out (FIO_BOSA_RX_STATUS_GET, sizeof(struct optic_bosa_rx_status),
bosa_rx_status_get),
/* 13 */ TE1out (FIO_BOSA_TX_STATUS_GET, sizeof(struct optic_bosa_tx_status),
bosa_tx_status_get),
/* 14 */ TE1out (FIO_BOSA_ALARM_STATUS_GET, sizeof(struct optic_bosa_alarm),
bosa_alarm_status_get),
/* 15 */ TE0 (FIO_BOSA_ALARM_STATUS_CLEAR, bosa_alarm_status_clear),
/* 16 */ TE1out (FIO_BOSA_INT_COEFF_GET, sizeof(struct optic_int_coeff),
bosa_int_coeff_get),
/* 17 */ TE1out (FIO_BOSA_STABLE_GET, sizeof(struct optic_stable),
bosa_stable_get),
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_bosa.h
*/
#ifndef _drv_optic_bosa_h
#define _drv_optic_bosa_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_BOSA_INTERNAL BOSA Module - Internal
@{
*/
enum optic_errorcode optic_bosa_init ( struct optic_control *p_ctrl );
enum optic_errorcode optic_powerlevel_set ( const uint8_t powerlevel );
enum optic_errorcode optic_powerlevel_get ( uint8_t *powerlevel );
enum optic_errorcode optic_bosa_powerlevel_set ( struct optic_control *p_ctrl,
const enum optic_powerlevel
powerlevel );
enum optic_errorcode optic_bosa_powerlevel_get ( struct optic_control *p_ctrl,
enum optic_powerlevel
*powerlevel );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_calc_h
#define _drv_optic_calc_h
#ifndef SYSTEM_SIMULATION
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_goi_interface.h"
#else
#include "drv_optic_simu.h"
#endif
EXTERN_C_BEGIN
/** \defgroup OPTIC_CALC_INTERNAL Common Driver Calculation Module
@{
*/
/* granularity of loarithm calculation in post commata binary
digits (10 ~ 0,002)*/
#define OPTIC_LOG_GRANULARITY 10
enum optic_dcdc_type
{
OPTIC_DCDC_APD,
OPTIC_DCDC_CORE,
OPTIC_DCDC_DDR,
};
int optic_in_range(void* ptr, ulong_t start, ulong_t end);
uint32_t optic_uint_div_rounded ( uint32_t divident, uint32_t divisor );
int32_t optic_int_div_rounded ( int32_t divident, int32_t divisor );
uint16_t optic_shift_temp_back ( const uint16_t temperature );
enum optic_errorcode optic_float2int ( int32_t float_val,
uint8_t shift,
uint16_t dec_factor,
int16_t *ib,
uint16_t *fb );
enum optic_errorcode optic_powerlevel2gainbank ( const enum optic_powerlevel
powerlevel,
enum optic_gainbank
*gainbank );
enum optic_errorcode optic_rangecheck_dcdc ( const struct optic_config_range
*range,
const enum optic_dcdc_type type,
const uint16_t dcdc_voltage );
enum optic_errorcode optic_rangecheck_itemp_nom ( const struct
optic_config_range *range,
const uint16_t itemp_nom );
enum optic_errorcode optic_rangecheck_itemp_corr ( const struct
optic_config_range *range,
const uint16_t itemp_corr );
enum optic_errorcode optic_rangecheck_etemp_nom ( const struct
optic_config_range *range,
const uint16_t etemp_nom,
uint16_t *temp_index );
enum optic_errorcode optic_rangecheck_etemp_corr ( const struct
optic_config_range *range,
const uint16_t extemp_corr,
uint16_t *temp_index );
enum optic_errorcode optic_calc_pn_gain_sel ( struct optic_control *p_ctrl );
enum optic_errorcode optic_fill_table_ipol ( struct optic_control *p_ctrl,
const enum optic_tabletype type,
const uint16_t offset,
const uint8_t size,
const uint16_t ipol_lb,
const uint16_t ipol_ub );
enum optic_errorcode optic_fill_table_const ( struct optic_control *p_ctrl,
const enum optic_tabletype type,
uint16_t offset,
uint8_t size,
int32_t val );
enum optic_errorcode optic_calc_ibiasimod ( struct optic_control *p_ctrl );
enum optic_errorcode optic_calc_ith_se ( struct optic_control *p_ctrl );
enum optic_errorcode optic_temperature_nom2corr ( const struct
optic_config_range *range,
const struct
optic_table_temperature_nom
*table_temperature_nom,
const uint16_t temp_nom,
uint16_t *temp_corr );
enum optic_errorcode optic_fusecorrect_temp ( struct optic_fuses *fuses,
uint16_t temp_nom,
uint16_t *temp_corr );
enum optic_errorcode optic_check_age ( struct optic_control *p_ctrl );
#if (OPTIC_FCSI_PREDRIVER_RANGECHECK == ACTIVE)
enum optic_errorcode optic_check_predriver ( uint8_t dd_loadn,
uint8_t dd_bias_en,
uint8_t dd_loadp,
uint8_t dd_cm_load,
uint8_t bd_loadn,
uint8_t bd_bias_en,
uint8_t bd_loadp,
uint8_t bd_cm_load );
#endif
enum optic_errorcode optic_check_temperature_alarm ( struct optic_control
*p_ctrl );
enum optic_errorcode optic_calc_gain_correct ( struct optic_control *p_ctrl,
const bool p0,
const int16_t dac_coarse,
const int16_t dac_fine,
uint16_t *gain_correct );
enum optic_errorcode optic_calc_codeword ( struct optic_control *p_ctrl,
const bool p0,
const uint16_t temp_ext_corr,
const int16_t gain_correct,
int32_t *codeword );
enum optic_errorcode optic_calc_bias2reg ( const uint8_t gain_dac_bias,
const uint8_t bias_max,
const uint16_t ibias,
uint16_t *dbias );
enum optic_errorcode optic_calc_reg2bias ( const uint8_t gain_dac_bias,
const uint8_t bias_max,
const uint16_t dbias,
uint16_t *bias );
enum optic_errorcode optic_calc_mod2reg ( const uint8_t gain_dac_drive,
const uint16_t scalefactor_mod,
const uint8_t mod_max,
const uint16_t imod,
uint16_t *dmod );
enum optic_errorcode optic_calc_reg2mod ( const uint8_t gain_dac_drive,
const uint16_t scalefactor_mod,
const uint8_t mod_max,
const uint16_t dmod,
uint16_t *mod );
enum optic_errorcode optic_calc_voltage ( const enum optic_measure_type type,
const enum optic_vref vref,
const struct optic_table_mm_gain
*gain,
const int16_t reg_value,
uint8_t *gain_selector,
uint16_t *voltage );
enum optic_errorcode optic_calc_digitword ( const enum optic_vref vref,
const struct optic_table_mm_gain
*gain,
const uint16_t voltage,
uint16_t *digitword );
enum optic_errorcode optic_calc_temperature_int ( const uint16_t voltage_vdd,
const uint16_t voltage_vbe1,
const uint16_t voltage_vbe2,
uint16_t *t_nom );
enum optic_errorcode optic_calc_temperature_ext ( const uint16_t
voltage_offset_pn,
const uint16_t tscal_ref,
const uint16_t voltage,
uint16_t *t_nom );
enum optic_errorcode optic_calc_voltage_digitword ( struct optic_control
*p_ctrl,
const enum
optic_measure_type type,
const uint16_t voltage,
uint16_t *digitword );
enum optic_errorcode optic_search_apd_saturation ( struct optic_control *p_ctrl,
const uint16_t vapd,
uint8_t *sat );
enum optic_errorcode optic_calc_duty_cycle ( struct optic_control *p_ctrl,
const enum optic_dcdc_type type,
const uint16_t voltage,
uint8_t *duty_cycle_min,
uint8_t *duty_cycle_max );
enum optic_errorcode optic_calc_rssi_1490_dark_corr ( const uint16_t
meas_voltage_1490_rssi,
const uint16_t ext_att,
const uint16_t
vapd_target,
const uint32_t *r_diff,
const uint16_t
rssi_1490_shunt_res,
uint16_t
*rssi_1490_dark_corr );
enum optic_errorcode optic_calc_current_offset ( const uint16_t
rssi_1490_dark_corr,
const uint16_t vapd_target,
const uint32_t *r_diff,
const uint16_t
rssi_1490_shunt_res,
uint16_t *current_offset );
enum optic_errorcode optic_calc_current_1490 ( const enum optic_rssi_1490_mode
rssi_1490_mode,
const uint16_t voltage_1490,
const uint16_t ext_att,
const uint16_t
rssi_1490_shunt_res,
const uint16_t current_offset,
struct optic_fuses *fuses,
uint16_t *current_1490,
bool *is_positive );
enum optic_errorcode optic_calc_power ( const enum optic_cfactor factor_index,
const struct optic_config_range *range,
const uint16_t temperature_ext,
struct optic_table_temperature_corr
*t_corr,
const uint16_t scal_ref,
const uint16_t meas_value,
uint16_t *power,
const uint16_t parabolic_ref,
const uint16_t dark_ref);
enum optic_errorcode optic_calc_thresh_current ( const uint16_t
rssi_1490_scal_ref,
const uint16_t threshold,
uint16_t *thresh_current );
enum optic_errorcode optic_calc_thresh_voltage_1490 ( const enum
optic_rssi_1490_mode
rssi_1490_mode,
const uint16_t
thresh_current,
const uint16_t ext_att,
const uint16_t
rssi_1490_shunt_res,
const uint16_t
current_offset,
struct optic_fuses *fuses,
const bool force,
uint16_t *thresh_voltage );
enum optic_errorcode optic_calc_offset_and_thresh ( struct optic_control
*p_ctrl );
enum optic_errorcode optic_calc_lol_thresh( const uint32_t base,
const uint8_t limit_low,
const uint8_t limit_high,
int32_t *low_tresh,
int32_t *high_tresh);
uint32_t optic_ln2_arithmentic ( void );
uint32_t optic_ld_arithmentic ( uint32_t value );
uint32_t optic_ln_arithmentic ( uint32_t value );
int32_t optic_ln_lookuptable ( uint32_t value );
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_cli_core.h
Device Driver, Command Line Interface
*/
#ifndef _optic_cli_h
#define _optic_cli_h
#include "drv_optic_std_defs.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
#ifdef INCLUDE_CLI_SUPPORT
/** @defgroup CLI_INTERFACE Command Line Interface
* This file contains the informations to access the device driver.
* @{
*/
/** empty command name */
#define CLI_EMPTY_CMD " "
/** help for empry command */
#define CLI_EMPTY_CMD_HELP "n/a"
/**
Initialize the command line interface.
\return
- 0 on success
- -1 on failure
*/
int optic_cli_init ( void );
/**
Clean command list.
\return
- 0 successful operation
*/
int optic_cli_shutdown ( void );
typedef int (*optic_cli_entry) ( struct optic_device *p_dev,
const char *p_cmds,
const uint32_t bufsize_max,
char *p_out );
/**
Add a command to the list.
\param short_name short command name
\param long_name long command name
\param func command entry point
\return
- -1 no more space left in command table
- 0 command added to the command table
*/
int optic_cli_command_add ( char const *short_name,
char const *long_name,
optic_cli_entry cli_entry );
/**
Execute CLI command.
\param devCtx device context
\param buffer command string buffer (in & out)
\param size maximum size of the buffer
\return
- number of bytes in return buffer on success
- -1 on failure
*/
int optic_cli_command_execute ( struct optic_device *p_dev,
char *buffer,
const uint32_t size );
/**
Register the non-generated commands.
*/
void optic_cli_misc_register ( void );
/**
Register the generated commands.
*/
void optic_cli_autogen_register ( void );
/**
sscanf implementation with uint8 support.
*/
int32_t optic_cli_sscanf ( const char *buf, char const *fmt,...);
/** @} */
#endif /* INCLUDE_CLI_SUPPORT */
EXTERN_C_END
#endif /* _optic_cli_h */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_cli_core.h"
#include "drv_optic_api.h"
#include "drv_optic_interface.h"
#include "drv_optic_goi_interface.h"
#include "drv_optic_bert_interface.h"
#include "ifxos_memory_alloc.h"
#ifdef INCLUDE_CLI_SUPPORT
extern int optic_cli_check_help(
const char *p_cmd,
const char *p_usage,
const uint32_t bufsize_max,
char *p_out);
/** \addtogroup OPTIC_CLI_COMMANDS
@{
*/
/** Handle command
\param[in] p_dev OPTIC device pointer
\param[in] p_cmd Input commands
\param[in] p_out Output FD
*/
static int cli_goi_lts_cfg_set(
struct optic_device *p_dev,
const char *p_cmd,
const uint32_t bufsize_max,
char *p_out)
{
int ret = 0;
enum optic_errorcode fct_ret = (enum optic_errorcode) 0;
struct optic_lts_config param;
#ifndef OPTIC_DEBUG_DISABLE
static const char usage[] =
"Long Form: goi_lts_cfg_set" OPTIC_CRLF
"Short Form: goilcs" OPTIC_CRLF
OPTIC_CRLF
"Input Parameter" OPTIC_CRLF
"- bool enable" OPTIC_CRLF
"- uint8_t pattern_length" OPTIC_CRLF
"- uint8_t pattern[78]" OPTIC_CRLF
OPTIC_CRLF
"Output Parameter" OPTIC_CRLF
"- enum optic_errorcode errorcode" OPTIC_CRLF
OPTIC_CRLF;
#else
#undef usage
#define usage ""
#endif
if ((ret = optic_cli_check_help(p_cmd, usage, bufsize_max, p_out)) >= 0) {
return ret;
}
ret = optic_cli_sscanf(p_cmd, "%bu %bu %bu[78]", &param.enable, &param.pattern_length, &param.pattern[0]);
if (ret != 80) {
return optic_cli_check_help("-h", usage, bufsize_max, p_out);
}
fct_ret = goi_lts_cfg_set(p_dev, &param);
return sprintf(p_out, "errorcode=%d " OPTIC_CRLF, (int)fct_ret);
}
/** Handle command
\param[in] p_dev OPTIC device pointer
\param[in] p_cmd Input commands
\param[in] p_out Output FD
*/
static int cli_goi_lts_cfg_get(
struct optic_device *p_dev,
const char *p_cmd,
const uint32_t bufsize_max,
char *p_out)
{
int ret = 0;
enum optic_errorcode fct_ret = (enum optic_errorcode) 0;
struct optic_lts_config param;
#ifndef OPTIC_DEBUG_DISABLE
static const char usage[] =
"Long Form: goi_lts_cfg_get" OPTIC_CRLF
"Short Form: goilcg" OPTIC_CRLF
OPTIC_CRLF
"Output Parameter" OPTIC_CRLF
"- enum optic_errorcode errorcode" OPTIC_CRLF
"- bool enable" OPTIC_CRLF
"- uint8_t pattern_length" OPTIC_CRLF
"- uint8_t pattern[78]" OPTIC_CRLF
OPTIC_CRLF;
#else
#undef usage
#define usage ""
#endif
if ((ret = optic_cli_check_help(p_cmd, usage, bufsize_max, p_out)) >= 0) {
return ret;
}
fct_ret = goi_lts_cfg_get(p_dev, &param);
return sprintf(p_out, "errorcode=%d enable=%u pattern_length=%u pattern=\"%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u\" " OPTIC_CRLF, (int)fct_ret, param.enable, param.pattern_length, param.pattern[0], param.pattern[1], param.pattern[2], param.pattern[3], param.pattern[4], param.pattern[5], param.pattern[6], param.pattern[7], param.pattern[8], param.pattern[9], param.pattern[10], param.pattern[11], param.pattern[12], param.pattern[13], param.pattern[14], param.pattern[15], param.pattern[16], param.pattern[17], param.pattern[18], param.pattern[19], param.pattern[20], param.pattern[21], param.pattern[22], param.pattern[23], param.pattern[24], param.pattern[25], param.pattern[26], param.pattern[27], param.pattern[28], param.pattern[29], param.pattern[30], param.pattern[31], param.pattern[32], param.pattern[33], param.pattern[34], param.pattern[35], param.pattern[36], param.pattern[37], param.pattern[38], param.pattern[39], param.pattern[40], param.pattern[41], param.pattern[42], param.pattern[43], param.pattern[44], param.pattern[45], param.pattern[46], param.pattern[47], param.pattern[48], param.pattern[49], param.pattern[50], param.pattern[51], param.pattern[52], param.pattern[53], param.pattern[54], param.pattern[55], param.pattern[56], param.pattern[57], param.pattern[58], param.pattern[59], param.pattern[60], param.pattern[61], param.pattern[62], param.pattern[63], param.pattern[64], param.pattern[65], param.pattern[66], param.pattern[67], param.pattern[68], param.pattern[69], param.pattern[70], param.pattern[71], param.pattern[72], param.pattern[73], param.pattern[74], param.pattern[75], param.pattern[76], param.pattern[77]);
}
/** Handle command
\param[in] p_dev OPTIC device pointer
\param[in] p_cmd Input commands
\param[in] p_out Output FD
*/
static int cli_bert_cfg_set(
struct optic_device *p_dev,
const char *p_cmd,
const uint32_t bufsize_max,
char *p_out)
{
int ret = 0;
enum optic_errorcode fct_ret = (enum optic_errorcode) 0;
struct optic_bert_cfg param;
#ifndef OPTIC_DEBUG_DISABLE
static const char usage[] =
"Long Form: bert_cfg_set" OPTIC_CRLF
"Short Form: bertcs" OPTIC_CRLF
OPTIC_CRLF
"Input Parameter" OPTIC_CRLF
"- uint8_t pattern_mode" OPTIC_CRLF
"- uint8_t pattern_type[4]" OPTIC_CRLF
"- uint8_t pattern_length[4]" OPTIC_CRLF
"- uint8_t fixed_pattern[78]" OPTIC_CRLF
"- uint8_t clock_period" OPTIC_CRLF
"- uint8_t clock_high" OPTIC_CRLF
"- uint8_t prbs_type" OPTIC_CRLF
"- bool datarate_tx_high \n false = 0\n true = 1" OPTIC_CRLF
"- bool datarate_rx_high \n false = 0\n true = 1" OPTIC_CRLF
"- bool loop_enable \n false = 0\n true = 1" OPTIC_CRLF
OPTIC_CRLF
"Output Parameter" OPTIC_CRLF
"- enum optic_errorcode errorcode" OPTIC_CRLF
OPTIC_CRLF;
#else
#undef usage
#define usage ""
#endif
if ((ret = optic_cli_check_help(p_cmd, usage, bufsize_max, p_out)) >= 0) {
return ret;
}
ret = optic_cli_sscanf(p_cmd, "%bu %bu[4] %bu[4] %bu[78] %bu %bu %bu %bu %bu %bu", &param.pattern_mode, &param.pattern_type[0], &param.pattern_length[0], &param.fixed_pattern[0], &param.clock_period, &param.clock_high, &param.prbs_type, &param.datarate_tx_high, &param.datarate_rx_high, &param.loop_enable);
if (ret != 93) {
return optic_cli_check_help("-h", usage, bufsize_max, p_out);
}
fct_ret = bert_cfg_set(p_dev, &param);
return sprintf(p_out, "errorcode=%d " OPTIC_CRLF, (int)fct_ret);
}
/** Handle command
\param[in] p_dev OPTIC device pointer
\param[in] p_cmd Input commands
\param[in] p_out Output FD
*/
static int cli_bert_cfg_get(
struct optic_device *p_dev,
const char *p_cmd,
const uint32_t bufsize_max,
char *p_out)
{
int ret = 0;
enum optic_errorcode fct_ret = (enum optic_errorcode) 0;
struct optic_bert_cfg param;
#ifndef OPTIC_DEBUG_DISABLE
static const char usage[] =
"Long Form: bert_cfg_get" OPTIC_CRLF
"Short Form: bertcg" OPTIC_CRLF
OPTIC_CRLF
"Output Parameter" OPTIC_CRLF
"- enum optic_errorcode errorcode" OPTIC_CRLF
"- uint8_t pattern_mode" OPTIC_CRLF
"- uint8_t pattern_type[4]" OPTIC_CRLF
"- uint8_t pattern_length[4]" OPTIC_CRLF
"- uint8_t fixed_pattern[78]" OPTIC_CRLF
"- uint8_t clock_period" OPTIC_CRLF
"- uint8_t clock_high" OPTIC_CRLF
"- uint8_t prbs_type" OPTIC_CRLF
"- bool datarate_tx_high \n false = 0\n true = 1" OPTIC_CRLF
"- bool datarate_rx_high \n false = 0\n true = 1" OPTIC_CRLF
"- bool loop_enable \n false = 0\n true = 1" OPTIC_CRLF
OPTIC_CRLF;
#else
#undef usage
#define usage ""
#endif
if ((ret = optic_cli_check_help(p_cmd, usage, bufsize_max, p_out)) >= 0) {
return ret;
}
fct_ret = bert_cfg_get(p_dev, &param);
return sprintf(p_out, "errorcode=%d pattern_mode=%u pattern_type=\"%u %u %u %u\" pattern_length=\"%u %u %u %u\" fixed_pattern=\"%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u\" clock_period=%u clock_high=%u prbs_type=%u datarate_tx_high=%u datarate_rx_high=%u loop_enable=%u " OPTIC_CRLF, (int)fct_ret, param.pattern_mode, param.pattern_type[0], param.pattern_type[1], param.pattern_type[2], param.pattern_type[3], param.pattern_length[0], param.pattern_length[1], param.pattern_length[2], param.pattern_length[3], param.fixed_pattern[0], param.fixed_pattern[1], param.fixed_pattern[2], param.fixed_pattern[3], param.fixed_pattern[4], param.fixed_pattern[5], param.fixed_pattern[6], param.fixed_pattern[7], param.fixed_pattern[8], param.fixed_pattern[9], param.fixed_pattern[10], param.fixed_pattern[11], param.fixed_pattern[12], param.fixed_pattern[13], param.fixed_pattern[14], param.fixed_pattern[15], param.fixed_pattern[16], param.fixed_pattern[17], param.fixed_pattern[18], param.fixed_pattern[19], param.fixed_pattern[20], param.fixed_pattern[21], param.fixed_pattern[22], param.fixed_pattern[23], param.fixed_pattern[24], param.fixed_pattern[25], param.fixed_pattern[26], param.fixed_pattern[27], param.fixed_pattern[28], param.fixed_pattern[29], param.fixed_pattern[30], param.fixed_pattern[31], param.fixed_pattern[32], param.fixed_pattern[33], param.fixed_pattern[34], param.fixed_pattern[35], param.fixed_pattern[36], param.fixed_pattern[37], param.fixed_pattern[38], param.fixed_pattern[39], param.fixed_pattern[40], param.fixed_pattern[41], param.fixed_pattern[42], param.fixed_pattern[43], param.fixed_pattern[44], param.fixed_pattern[45], param.fixed_pattern[46], param.fixed_pattern[47], param.fixed_pattern[48], param.fixed_pattern[49], param.fixed_pattern[50], param.fixed_pattern[51], param.fixed_pattern[52], param.fixed_pattern[53], param.fixed_pattern[54], param.fixed_pattern[55], param.fixed_pattern[56], param.fixed_pattern[57], param.fixed_pattern[58], param.fixed_pattern[59], param.fixed_pattern[60], param.fixed_pattern[61], param.fixed_pattern[62], param.fixed_pattern[63], param.fixed_pattern[64], param.fixed_pattern[65], param.fixed_pattern[66], param.fixed_pattern[67], param.fixed_pattern[68], param.fixed_pattern[69], param.fixed_pattern[70], param.fixed_pattern[71], param.fixed_pattern[72], param.fixed_pattern[73], param.fixed_pattern[74], param.fixed_pattern[75], param.fixed_pattern[76], param.fixed_pattern[77], param.clock_period, param.clock_high, param.prbs_type, param.datarate_tx_high, param.datarate_rx_high, param.loop_enable);
}
/** Handle command
\param[in] p_dev OPTIC device pointer
\param[in] p_cmd Input commands
\param[in] p_out Output FD
*/
static int cli_cal_measure_rssi_1490_get(
struct optic_device *p_dev,
const char *p_cmd,
const uint32_t bufsize_max,
char *p_out)
{
int ret = 0, length = 0;
enum optic_errorcode fct_ret = (enum optic_errorcode) 0;
union optic_measure_rssi_1490_get param;
uint8_t i, number;
uint16_t *p_data;
#ifndef OPTIC_DEBUG_DISABLE
static const char usage[] =
"Long Form: cal_measure_rssi_1490_get" OPTIC_CRLF
"Short Form: calmr1490" OPTIC_CRLF
OPTIC_CRLF
"Input Parameter" OPTIC_CRLF
"- uint8_t number" OPTIC_CRLF
OPTIC_CRLF
"Output Parameter" OPTIC_CRLF
"- enum optic_errorcode errorcode" OPTIC_CRLF
"- uint16_t measure_buffer" OPTIC_CRLF
OPTIC_CRLF;
#else
#undef usage
#define usage ""
#endif
if ((ret = optic_cli_check_help(p_cmd, usage, bufsize_max, p_out)) >= 0) {
return ret;
}
ret = optic_cli_sscanf(p_cmd, "%bu ", &param.in.number);
if (ret != 1) {
return optic_cli_check_help("-h", usage, bufsize_max, p_out);
}
param.in.p_data = IFXOS_MemAlloc ( sizeof(uint16_t) * param.in.number);
number = param.in.number;
p_data = param.in.p_data;
if (p_data == IFX_NULL) {
length = sprintf(p_out, "errorcode=-1");
return length;
}
fct_ret = cal_measure_rssi_1490_get(p_dev, &param.in, &param.out);
length = sprintf(p_out, "errorcode=%d", (int)fct_ret);
if (fct_ret >= 0) {
length += sprintf(&(p_out[length]), " measure_buffer[%u]= ", number);
for (i=0; i<number; i++)
length += sprintf(&(p_out[length]), "%hu ", p_data[i] );
}
IFXOS_MemFree (p_data);
length += sprintf(&(p_out[length]), "measure_average= %d", param.out.average );
length += sprintf(&(p_out[length]), OPTIC_CRLF );
return length;
}
/** Register misc commands */
void optic_cli_misc_register ( void )
{
optic_cli_command_add("goilcs", "goi_lts_cfg_set", cli_goi_lts_cfg_set);
optic_cli_command_add("goilcg", "goi_lts_cfg_get", cli_goi_lts_cfg_get);
optic_cli_command_add("bertcs", "bert_cfg_set", cli_bert_cfg_set);
optic_cli_command_add("bertcg", "bert_cfg_get", cli_bert_cfg_get);
optic_cli_command_add("calmr1490g", "cal_measure_rssi_1490_get", cli_cal_measure_rssi_1490_get);
}
/*! @} */
#endif

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/* src/drv_optic_config.h.in. Generated from configure.in by autoheader. */
/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _GPON_OPTIC_CONFIG_H
#define _GPON_OPTIC_CONFIG_H
/* compile for linux kernel */
#undef ENABLE_LINUX
/* enable event logger debugging */
#undef EVENT_LOGGER_DEBUG
/* Define to 1 if you have the <inttypes.h> header file. */
#undef HAVE_INTTYPES_H
/* Define to 1 if you have the <memory.h> header file. */
#undef HAVE_MEMORY_H
/* Define to 1 if you have the <stdint.h> header file. */
#undef HAVE_STDINT_H
/* Define to 1 if you have the <stdlib.h> header file. */
#undef HAVE_STDLIB_H
/* Define to 1 if you have the <strings.h> header file. */
#undef HAVE_STRINGS_H
/* Define to 1 if you have the <string.h> header file. */
#undef HAVE_STRING_H
/* Define to 1 if you have the <sys/stat.h> header file. */
#undef HAVE_SYS_STAT_H
/* Define to 1 if you have the <sys/types.h> header file. */
#undef HAVE_SYS_TYPES_H
/* Define to 1 if the system has the type `ulong_t'. */
#undef HAVE_ULONG_T
/* Define to 1 if you have the <unistd.h> header file. */
#undef HAVE_UNISTD_H
/* Command Line Interface */
#undef INCLUDE_CLI_SUPPORT
/* Debug Support */
#undef INCLUDE_DEBUG_SUPPORT
/* proc filesystem */
#undef INCLUDE_PROCFS_SUPPORT
/* Enable remote-only ONU */
#undef INCLUDE_REMOTE_ONLY_ONU
/* Enable remote ONU */
#undef INCLUDE_REMOTE_ONU
/* Define to 1 if your C compiler doesn't accept -c and -o together. */
#undef NO_MINUS_C_MINUS_O
/* OPTIC library */
#undef OPTIC_LIBRARY
/* OPTIC simulation */
#undef OPTIC_SIMULATION
/* Name of package */
#undef PACKAGE
/* Define to the address where bug reports for this package should be sent. */
#undef PACKAGE_BUGREPORT
/* Define to the full name of this package. */
#undef PACKAGE_NAME
/* Define to the full name and version of this package. */
#undef PACKAGE_STRING
/* Define to the one symbol short name of this package. */
#undef PACKAGE_TARNAME
/* Define to the version of this package. */
#undef PACKAGE_VERSION
/* Define to 1 if you have the ANSI C header files. */
#undef STDC_HEADERS
/* Version number of package */
#undef VERSION
#endif /* _GPON_OPTIC_CONFIG_H */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, DC/DC APD Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_DCDC_APD_INTERNAL DC/DC APD Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_dcdc_apd_interface.h"
#include "drv_optic_calc.h"
#include "drv_optic_dcdc_apd.h"
#include "drv_optic_ll_dcdc_apd.h"
/**
Read apd configuration data into the context.
*/
enum optic_errorcode dcdc_apd_cfg_set ( struct optic_device *p_dev,
const struct optic_dcdc_apd_config
*param )
{
uint8_t i;
uint32_t temp;
struct optic_control *p_ctrl = p_dev->p_ctrl;
if (param == NULL)
return OPTIC_STATUS_ERR;
p_ctrl->config.dcdc_apd.v_ext = param->v_ext;
for (i=0; i<2; i++)
p_ctrl->config.dcdc_apd.r_diff[i] = param->r_diff[i];
/* r_diff[1] = Rdiv_high
r_diff[0] = Rdiv_low
ext_att = (r_diff[1] + r_diff[0]) / r_diff[0] */
temp = (p_ctrl->config.dcdc_apd.r_diff[0] +
p_ctrl->config.dcdc_apd.r_diff[1])
<< OPTIC_FLOAT2INTSHIFT_EXTATT;
temp = optic_uint_div_rounded ( temp,
p_ctrl->config.dcdc_apd.r_diff[0] );
p_ctrl->config.dcdc_apd.ext_att = (uint16_t) temp;
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_DCDC_APD] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return OPTIC_STATUS_OK;
}
/**
Returns apd configuration.
*/
enum optic_errorcode dcdc_apd_cfg_get ( struct optic_device *p_dev,
struct optic_dcdc_apd_config *param )
{
uint8_t i;
struct optic_control *p_ctrl = p_dev->p_ctrl;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_dcdc_apd_config) );
for (i=0; i<2; i++)
param->r_diff[i] = p_ctrl->config.dcdc_apd.r_diff[i];
param->v_ext = p_ctrl->config.dcdc_apd.v_ext;
return OPTIC_STATUS_OK;
}
enum optic_errorcode dcdc_apd_enable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_dcdc_apd_set ( OPTIC_ENABLE );
}
enum optic_errorcode dcdc_apd_disable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_dcdc_apd_set ( OPTIC_DISABLE );
}
bool dcdc_apd_disabled (void) {
enum optic_activation mode;
optic_ll_dcdc_apd_get(&mode);
return (mode == OPTIC_DISABLE)? true : false;
}
enum optic_errorcode dcdc_apd_status_get ( struct optic_device *p_dev,
struct optic_dcdc_apd_status
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
enum optic_errorcode ret;
enum optic_activation mode;
uint16_t voltage;
int32_t temp;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_dcdc_apd_status) );
ret = optic_ll_dcdc_apd_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->enable = (mode == OPTIC_ENABLE)? true : false;
param->target_voltage = p_ctrl->calibrate.vapd_target;
ret = optic_dcdc_apd_voltage_get ( p_ctrl, &voltage,
&(param->regulation_error) );
if (ret != OPTIC_STATUS_OK)
return ret;
if (mode == OPTIC_ENABLE) {
temp = voltage;
temp = temp - param->regulation_error;
param->voltage = (int16_t) temp;
} else { /* OPTIC_DISABLE */
param->voltage = (int16_t) p_ctrl->config.dcdc_apd.v_ext;
}
ret = optic_ll_dcdc_apd_saturation_get ( &(param->saturation) );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ----------------------------- NON IOCTL ---------------------------------- */
/**
set DCDC APD voltage - at maximum in range of 1V, in this case timer
will be started to set target voltage (or next step) in next cycle
*/
enum optic_errorcode optic_dcdc_apd_voltage_set ( struct optic_control *p_ctrl,
const uint16_t vapd_desired,
const uint8_t sat )
{
struct optic_fuses *fuses = &(p_ctrl->config.fuses);
struct optic_config *config = &(p_ctrl->config);
uint16_t vapd_actual;
static uint16_t vapd_actual_cnt = 0;
uint8_t sat_target = sat;
enum optic_errorcode ret;
if (p_ctrl->calibrate.vapd_target != vapd_desired) {
/* first "loop" of timer -> apd voltage set */
ret = optic_rangecheck_dcdc ( &(p_ctrl->config.range),
OPTIC_DCDC_APD, vapd_desired );
if (ret != OPTIC_STATUS_OK)
return ret;
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("optic_dcdc_apd_voltage_set(): vapd_desired=%d, sat=%d",
vapd_desired, sat);
#endif
p_ctrl->calibrate.vapd_target = vapd_desired;
p_ctrl->calibrate.sat_target = sat;
}
/* ret = 0 -> no adaptation necessary */
ret = optic_ll_dcdc_apd_voltage_set ( fuses->offset_dcdc_apd,
fuses->gain_dcdc_apd,
config->dcdc_apd.ext_att,
vapd_desired,
&vapd_actual );
switch(ret) {
case OPTIC_STATUS_DCDC_APD_RAMP_WAIT:
vapd_actual_cnt++;
/* If the HW loop does not converge, we
cannot wait too much, therefore we wait up to 10*10ms
Note: the HW loop always runs in background.
We monitor the regulation every 10ms. */
if(vapd_actual_cnt >= OPTIC_TIMER_DCDCAPD_REG_CYCLE_MAX) {
OPTIC_DEBUG_ERR("optic_dcdc_apd_voltage_set() regulation"
"error after %d tries",
vapd_actual_cnt);
vapd_actual_cnt = 0;
return OPTIC_STATUS_REGULATION;
}
/* reload timer: 10 ms */
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("reload APD timer ...");
#endif
optic_timer_start (OPTIC_TIMER_ID_APD_ADAPT,
OPTIC_TIMER_DCDCAPD_RAMP);
ret = OPTIC_STATUS_OK;
break;
case OPTIC_STATUS_DCDC_APD_RAMP:
/* count for each 1V voltage step from 0 */
vapd_actual_cnt = 0;
/* saturation for vapd step */
if (vapd_actual != vapd_desired) {
/* search for saturation value */
ret = optic_search_apd_saturation ( p_ctrl,
vapd_actual,
&sat_target );
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("vapd_actual: %d vapd_desired: %d, sat_target: %d",
vapd_actual, vapd_desired, sat_target);
#endif
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("search_apd_saturation(): %d",
ret);
}
ret = optic_ll_dcdc_apd_saturation_set ( sat_target );
}
/* reload timer: 10 ms */
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("reload APD timer ...");
#endif
optic_timer_start (OPTIC_TIMER_ID_APD_ADAPT,
OPTIC_TIMER_DCDCAPD_RAMP);
ret = OPTIC_STATUS_OK;
break;
case OPTIC_STATUS_DCDC_APD_CHANGE:
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("sat: %d", sat);
#endif
ret = optic_ll_dcdc_apd_saturation_set ( sat );
break;
default:
break;
}
return ret;
}
/**
timer for next step of SW ramp
*/
void optic_timer_dcdc_apd_adapt ( struct optic_control *p_ctrl )
{
/* set target voltage (maybe in next step of SW ramp */
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("optic_timer_dcdc_apd_adapt vapd: %d, sat:%d ",
p_ctrl->calibrate.vapd_target,
p_ctrl->calibrate.sat_target );
#endif
optic_dcdc_apd_voltage_set ( p_ctrl, p_ctrl->calibrate.vapd_target,
p_ctrl->calibrate.sat_target );
}
enum optic_errorcode optic_dcdc_apd_voltage_get ( struct optic_control *p_ctrl,
uint16_t *vapd,
int16_t *regulation_error )
{
struct optic_fuses *fuses = &(p_ctrl->config.fuses);
struct optic_config *config = &(p_ctrl->config);
enum optic_errorcode ret;
enum optic_activation mode;
ret = optic_ll_dcdc_apd_get(&mode);
if (ret != OPTIC_STATUS_OK)
return ret;
if (mode == OPTIC_ENABLE) {
ret = optic_ll_dcdc_apd_voltage_get ( fuses->offset_dcdc_apd,
fuses->gain_dcdc_apd,
config->dcdc_apd.ext_att,
vapd, regulation_error );
if (ret != OPTIC_STATUS_OK)
return ret;
/*
ret = optic_rangecheck_dcdc ( &(p_ctrl->config.range),
OPTIC_DCDC_APD, *vapd);
if (ret != OPTIC_STATUS_OK)
return ret;
*/
} else {
*vapd = (uint16_t) p_ctrl->config.dcdc_apd.v_ext;
*regulation_error = 0;
}
return ret;
}
/**
Updates vapd target and duty cycle saturation for current external
temperature.
*/
enum optic_errorcode optic_dcdc_apd_update ( struct optic_control *p_ctrl )
{
enum optic_errorcode ret;
uint16_t temp_index;
struct optic_calibrate *cal = &(p_ctrl->calibrate);
struct optic_table_temperature_corr *tab;
static uint16_t temp_index_old = 0;
ret = optic_rangecheck_etemp_corr ( &(p_ctrl->config.range),
cal->temperature_ext,
&temp_index );
if (ret != OPTIC_STATUS_OK)
return ret;
if (temp_index != temp_index_old) {
temp_index_old = temp_index;
tab = &(p_ctrl->table_temperature_corr[temp_index]);
OPTIC_DEBUG_MSG("update dcdc apd settings: "
"vref=%d.%02d, sat=%d",
tab->vapd.vref >> OPTIC_FLOAT2INTSHIFT_VOLTAGE,
((tab->vapd.vref * 100) % 100)
>> OPTIC_FLOAT2INTSHIFT_VOLTAGE,
tab->vapd.sat);
if (p_ctrl->config.debug_mode == true)
return ret;
ret = optic_dcdc_apd_voltage_set ( p_ctrl,
tab->vapd.vref,
tab->vapd.sat );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_dcdc_apd_voltage_set(): %d",
ret);
return ret;
}
}
return ret;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry dcdc_apd_function_table[OPTIC_DCDC_APD_MAX] =
{
/* 0 */ TE1in (FIO_DCDC_APD_CFG_SET, sizeof(struct optic_dcdc_apd_config),
dcdc_apd_cfg_set),
/* 1 */ TE1out (FIO_DCDC_APD_CFG_GET, sizeof(struct optic_dcdc_apd_config),
dcdc_apd_cfg_get),
/* 2 */ TE0 (FIO_DCDC_APD_ENABLE, dcdc_apd_enable),
/* 3 */ TE0 (FIO_DCDC_APD_DISABLE, dcdc_apd_disable),
/* 4 */ TE1out (FIO_DCDC_APD_STATUS_GET, sizeof(struct optic_dcdc_apd_status),
dcdc_apd_status_get),
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_dcdc_apd.h
*/
#ifndef _drv_optic_dcdc_apd_h
#define _drv_optic_dcdc_apd_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_DCDC_APD_INTERNAL DCDC APD Module - Internal
@{
*/
enum optic_errorcode optic_dcdc_apd_voltage_set ( struct optic_control *p_ctrl,
const uint16_t vapd,
const uint8_t sat );
void optic_timer_dcdc_apd_adapt (struct optic_control *p_ctrl);
enum optic_errorcode optic_dcdc_apd_voltage_get ( struct optic_control *p_ctrl,
uint16_t *vapd,
int16_t *regulation_error );
enum optic_errorcode optic_dcdc_apd_update ( struct optic_control *p_ctrl );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, DC/DC CORE Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_DCDC_CORE_INTERNAL DC/DC CORE Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_dcdc_core_interface.h"
#include "drv_optic_calc.h"
#include "drv_optic_dcdc_core.h"
#include "drv_optic_ll_dcdc_core.h"
/**
Read core configuration data into the context.
*/
enum optic_errorcode dcdc_core_cfg_set ( struct optic_device *p_dev,
const struct optic_dcdc_core_config
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
p_ctrl->config.dcdc_core.v_min = param->v_min;
p_ctrl->config.dcdc_core.v_max = param->v_max;
p_ctrl->config.dcdc_core.v_tolerance_input = param->v_tolerance_input;
p_ctrl->config.dcdc_core.v_tolerance_target = param->v_tolerance_target;
/** Dead zone timing to avoid switching transistor overlap.
The absolute value to be used depends on the selected external switching
transistor types for the NMOS and the PMOS switching transistor.
The time is given in units of ns.
The configurable range for each value is from 0 to 31 ns.
The hardware setting resolution is in steps of 2 ns,
so the LSB is of no significance.
The allowed value range is from 0x1 to 0xB. */
#if OPTIC_USE_DCDC_DEADZONE == ACTIVE
if (param->pmos_on_delay < 0x1 ||
param->pmos_on_delay > 0xB ||
param->nmos_on_delay < 0x1 ||
param->nmos_on_delay > 0xB) {
return OPTIC_STATUS_ERR;
} else {
p_ctrl->config.dcdc_core.pmos_on_delay = param->pmos_on_delay;
p_ctrl->config.dcdc_core.nmos_on_delay = param->nmos_on_delay;
}
#else
p_ctrl->config.dcdc_core.pmos_on_delay = 4;
p_ctrl->config.dcdc_core.nmos_on_delay = 7;
#endif
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_DCDC_CORE] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return OPTIC_STATUS_OK;
}
/**
Returns core configuration.
*/
enum optic_errorcode dcdc_core_cfg_get ( struct optic_device *p_dev,
struct optic_dcdc_core_config *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_dcdc_core_config) );
param->v_min = p_ctrl->config.dcdc_core.v_min;
param->v_max = p_ctrl->config.dcdc_core.v_max;
param->v_tolerance_input = p_ctrl->config.dcdc_core.v_tolerance_input;
param->v_tolerance_target = p_ctrl->config.dcdc_core.v_tolerance_target;
param->pmos_on_delay = p_ctrl->config.dcdc_core.pmos_on_delay;
param->nmos_on_delay = p_ctrl->config.dcdc_core.nmos_on_delay;
return OPTIC_STATUS_OK;
}
enum optic_errorcode dcdc_core_enable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_dcdc_core_set ( OPTIC_ENABLE );
}
enum optic_errorcode dcdc_core_disable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_dcdc_core_set ( OPTIC_DISABLE );
}
enum optic_errorcode dcdc_core_status_get ( struct optic_device *p_dev,
struct optic_dcdc_core_status
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
enum optic_errorcode ret;
enum optic_activation mode;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_dcdc_core_status) );
ret = optic_ll_dcdc_core_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->enable = (mode == OPTIC_ENABLE)? true : false;
ret = optic_dcdc_core_voltage_get ( p_ctrl, &(param->voltage) );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ----------------------------- NON IOCTL ---------------------------------- */
/**
set DCDC CORE voltage
*/
enum optic_errorcode optic_dcdc_core_voltage_set ( struct optic_control *p_ctrl,
const uint16_t vcore )
{
struct optic_fuses *fuses = &(p_ctrl->config.fuses);
enum optic_errorcode ret;
ret = optic_rangecheck_dcdc ( &(p_ctrl->config.range),
OPTIC_DCDC_CORE, vcore);
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_dcdc_core_voltage_set ( fuses->offset_dcdc_core,
fuses->gain_dcdc_core,
vcore );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/**
read DCDC CORE voltage
*/
enum optic_errorcode optic_dcdc_core_voltage_get ( struct optic_control *p_ctrl,
uint16_t *vcore )
{
struct optic_fuses *fuses = &(p_ctrl->config.fuses);
enum optic_errorcode ret;
ret = optic_ll_dcdc_core_voltage_get ( fuses->offset_dcdc_core,
fuses->gain_dcdc_core,
vcore );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_rangecheck_dcdc ( &(p_ctrl->config.range),
OPTIC_DCDC_CORE, *vcore);
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry dcdc_core_function_table[OPTIC_DCDC_CORE_MAX] =
{
/* 0 */ TE1in (FIO_DCDC_CORE_CFG_SET, sizeof(struct optic_dcdc_core_config),
dcdc_core_cfg_set),
/* 1 */ TE1out (FIO_DCDC_CORE_CFG_GET, sizeof(struct optic_dcdc_core_config),
dcdc_core_cfg_get),
/* 2 */ TE0 (FIO_DCDC_CORE_ENABLE, dcdc_core_enable),
/* 3 */ TE0 (FIO_DCDC_CORE_DISABLE, dcdc_core_disable),
/* 4 */ TE1out (FIO_DCDC_CORE_STATUS_GET, sizeof(struct optic_dcdc_core_status),
dcdc_core_status_get),
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_dcdc_core.h
*/
#ifndef _drv_optic_dcdc_core_h
#define _drv_optic_dcdc_core_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_DCDC_APD_INTERNAL DCDC CORE Module - Internal
@{
*/
enum optic_errorcode optic_dcdc_core_voltage_set ( struct optic_control *p_ctrl,
const uint16_t vcore );
enum optic_errorcode optic_dcdc_core_voltage_get ( struct optic_control *p_ctrl,
uint16_t *vcore );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, DC/DC DDR Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_DCDC_DDR_INTERNAL DC/DC DDR Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_dcdc_ddr_interface.h"
#include "drv_optic_calc.h"
#include "drv_optic_dcdc_ddr.h"
#include "drv_optic_ll_dcdc_ddr.h"
/**
Read core configuration data into the context.
*/
enum optic_errorcode dcdc_ddr_cfg_set ( struct optic_device *p_dev,
const struct optic_dcdc_ddr_config
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
p_ctrl->config.dcdc_ddr.v_min = param->v_min;
p_ctrl->config.dcdc_ddr.v_max = param->v_max;
p_ctrl->config.dcdc_ddr.v_tolerance_input = param->v_tolerance_input;
p_ctrl->config.dcdc_ddr.v_tolerance_target = param->v_tolerance_target;
/** Dead zone timing to avoid switching transistor overlap.
The absolute value to be used depends on the selected external switching
transistor types for the NMOS and the PMOS switching transistor.
The time is given in units of ns.
The configurable range for each value is from 0 to 31 ns.
The hardware setting resolution is in steps of 2 ns,
so the LSB is of no significance.
The allowed value range is from 0x1 to 0xB. */
#if OPTIC_USE_DCDC_DEADZONE == ACTIVE
if (param->pmos_on_delay < 0x1 ||
param->pmos_on_delay > 0xB ||
param->nmos_on_delay < 0x1 ||
param->nmos_on_delay > 0xB) {
return OPTIC_STATUS_ERR;
} else {
p_ctrl->config.dcdc_ddr.pmos_on_delay = param->pmos_on_delay;
p_ctrl->config.dcdc_ddr.nmos_on_delay = param->nmos_on_delay;
}
#else
p_ctrl->config.dcdc_ddr.pmos_on_delay = 4;
p_ctrl->config.dcdc_ddr.nmos_on_delay = 7;
#endif
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_DCDC_DDR] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return OPTIC_STATUS_OK;
}
/**
Returns core configuration.
*/
enum optic_errorcode dcdc_ddr_cfg_get ( struct optic_device *p_dev,
struct optic_dcdc_ddr_config *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_dcdc_ddr_config) );
param->v_min = p_ctrl->config.dcdc_ddr.v_min;
param->v_max = p_ctrl->config.dcdc_ddr.v_max;
param->v_tolerance_input = p_ctrl->config.dcdc_ddr.v_tolerance_input;
param->v_tolerance_target = p_ctrl->config.dcdc_ddr.v_tolerance_target;
param->pmos_on_delay = p_ctrl->config.dcdc_ddr.pmos_on_delay;
param->nmos_on_delay = p_ctrl->config.dcdc_ddr.nmos_on_delay;
return OPTIC_STATUS_OK;
}
enum optic_errorcode dcdc_ddr_enable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_dcdc_ddr_set ( OPTIC_ENABLE );
}
enum optic_errorcode dcdc_ddr_disable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_dcdc_ddr_set ( OPTIC_DISABLE );
}
enum optic_errorcode dcdc_ddr_status_get ( struct optic_device *p_dev,
struct optic_dcdc_ddr_status
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
enum optic_errorcode ret;
enum optic_activation mode;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_dcdc_ddr_status) );
ret = optic_ll_dcdc_ddr_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->enable = (mode == OPTIC_ENABLE)? true : false;
ret = optic_dcdc_ddr_voltage_get ( p_ctrl, &(param->voltage) );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ----------------------------- NON IOCTL ---------------------------------- */
/**
set DCDC DDR voltage
*/
enum optic_errorcode optic_dcdc_ddr_voltage_set ( struct optic_control *p_ctrl,
const uint16_t vddr )
{
struct optic_fuses *fuses = &(p_ctrl->config.fuses);
enum optic_errorcode ret;
ret = optic_rangecheck_dcdc ( &(p_ctrl->config.range),
OPTIC_DCDC_DDR, vddr);
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_dcdc_ddr_voltage_set ( fuses->offset_dcdc_ddr,
fuses->gain_dcdc_ddr,
vddr );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/**
read DCDC DDR voltage
*/
enum optic_errorcode optic_dcdc_ddr_voltage_get ( struct optic_control *p_ctrl,
uint16_t *vddr )
{
struct optic_fuses *fuses = &(p_ctrl->config.fuses);
enum optic_errorcode ret;
ret = optic_ll_dcdc_ddr_voltage_get ( fuses->offset_dcdc_ddr,
fuses->gain_dcdc_ddr,
vddr );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_rangecheck_dcdc ( &(p_ctrl->config.range),
OPTIC_DCDC_DDR, *vddr );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry dcdc_ddr_function_table[OPTIC_DCDC_DDR_MAX] =
{
/* 0 */ TE1in (FIO_DCDC_DDR_CFG_SET, sizeof(struct optic_dcdc_ddr_config),
dcdc_ddr_cfg_set),
/* 1 */ TE1out (FIO_DCDC_DDR_CFG_GET, sizeof(struct optic_dcdc_ddr_config),
dcdc_ddr_cfg_get),
/* 2 */ TE0 (FIO_DCDC_DDR_ENABLE, dcdc_ddr_enable),
/* 3 */ TE0 (FIO_DCDC_DDR_DISABLE, dcdc_ddr_disable),
/* 4 */ TE1out (FIO_DCDC_DDR_STATUS_GET, sizeof(struct optic_dcdc_ddr_status),
dcdc_ddr_status_get),
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_dcdc_ddr.h
*/
#ifndef _drv_optic_dcdc_ddr_h
#define _drv_optic_dcdc_ddr_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_DCDC_APD_INTERNAL DCDC DDR Module - Internal
@{
*/
enum optic_errorcode optic_dcdc_ddr_voltage_set ( struct optic_control *p_ctrl,
const uint16_t vddr );
enum optic_errorcode optic_dcdc_ddr_voltage_get ( struct optic_control *p_ctrl,
uint16_t *vddr );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_debug_h
#define _drv_optic_debug_h
/** \addtogroup MAPI_REFERENCE_GOI Optical Interface API Reference
@{
*/
/** \defgroup OPTIC_DEBUG Debug Interface
@{
*/
#ifdef EVENT_LOGGER_DEBUG
#define IFXOS_LIBRARY_USED
#include <el_log_macros.h>
#endif /* EVENT_LOGGER_DEBUG */
#if defined(WIN32)
# define OPTIC_CRLF "\r\n"
#else
# define OPTIC_CRLF "\n"
#endif
#undef IFXOS_CRLF
#define IFXOS_CRLF OPTIC_CRLF
#if defined(_DEBUG) && !defined(WIN32)
/** enable debug printouts */
# define INCLUDE_DEBUG_SUPPORT
#endif
/** OPTIC Debug Levels */
enum optic_debug_levels {
/** Message */
OPTIC_DBG_MSG,
/** Warning */
OPTIC_DBG_WRN,
/** Error */
OPTIC_DBG_ERR,
/** Off */
OPTIC_DBG_OFF
};
/** Debug message prefix */
#define DEBUG_PREFIX "[optic]"
#ifdef INCLUDE_DEBUG_SUPPORT
extern enum optic_debug_levels optic_debug_level;
# if defined(__GNUC__)
int optic_debug_print ( const enum optic_debug_levels level,
const char *format, ... );
# else
int optic_debug_print_err ( const char *format, ... );
int optic_debug_print_wrn ( const char *format, ... );
int optic_debug_print_msg ( const char *format, ... );
# endif
# define DEBUG_ENABLE_ERR
# define DEBUG_ENABLE_WRN
# define DEBUG_ENABLE_MSG
# define STATIC
# define INLINE
# ifdef __GNUC__
# define OPTIC_DEBUG_ERR(fmt, args...) optic_debug_print(OPTIC_DBG_ERR, fmt, ##args)
# define OPTIC_DEBUG_WRN(fmt, args...) optic_debug_print(OPTIC_DBG_WRN, fmt, ##args)
# define OPTIC_DEBUG_MSG(fmt, args...) optic_debug_print(OPTIC_DBG_MSG, fmt, ##args)
# else /* __GNUC__ */
# ifdef DEBUG_ENABLE_ERR
# define OPTIC_DEBUG_ERR optic_debug_print_err
# endif /* DEBUG_ENABLE_ERR */
# ifdef DEBUG_ENABLE_WRN
# define OPTIC_DEBUG_WRN optic_debug_print_wrn
# endif /* DEBUG_ENABLE_WRN */
# ifdef DEBUG_ENABLE_MSG
# define OPTIC_DEBUG_MSG optic_debug_print_msg
# endif /* DEBUG_ENABLE_MSG */
# endif /* __GNUC__ */
#endif /* INCLUDE_DEBUG_SUPPORT */
#ifndef INLINE
# ifdef WIN32
# define INLINE __inline
# else
# define INLINE inline
# endif
#endif
#ifndef STATIC
# define STATIC static
#endif
#ifndef OPTIC_DEBUG_ERR
# if defined(__GNUC__)
# define OPTIC_DEBUG_ERR(fmt, args...) do{}while(0)
# else
# define OPTIC_DEBUG_ERR {}
# endif
#endif
#ifndef OPTIC_DEBUG_WRN
# if defined(__GNUC__)
# define OPTIC_DEBUG_WRN(fmt, args...) do{}while(0)
# else
# define OPTIC_DEBUG_WRN {}
# endif
#endif
#ifndef OPTIC_DEBUG_MSG
# if defined(__GNUC__)
# define OPTIC_DEBUG_MSG(fmt, args...) do{}while(0)
# else
# define OPTIC_DEBUG_MSG {}
# endif
#endif
/*! @} */
/*! @} */
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_SIMULATION_INTERNAL Simulation Specific Implementation - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_timer.h"
#ifdef OPTIC_SIMULATION
#include <stdlib.h>
#include "ifxos_device_io.h"
#include "ifxos_memory_alloc.h"
#include "ifxos_time.h"
#include "ifxos_event.h"
#include "drv_optic_cli_core.h"
#include "drv_optic_event_interface.h"
#include "drv_optic_timer.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_simulator.h"
#include "drv_optic_ll_fcsi.h"
#include "ifxos_event.h"
#include "ifxos_thread.h"
struct timer_list
{
ulong_t data;
bool start;
uint32_t delay;
IFXOS_event_t timeout_event;
void (*function) (ulong_t param);
IFXOS_ThreadCtrl_t thread_context;
};
#define IFXOS_BlockAlloc IFXOS_MemAlloc
#define IFXOS_BlockFree IFXOS_MemFree
long optic_open ( void *ctrl,
const char *appendix );
int optic_release ( void *dev );
int optic_write ( void *dev,
const char *p_src,
const int length );
int optic_read( void *dev,
char *p_dst,
const int length );
int optic_ioctl ( void *dev,
unsigned int cmd,
ulong_t arg );
int optic_poll ( void *dev );
STATIC unsigned int major_number;
#ifdef INCLUDE_DEBUG_SUPPORT
enum optic_debug_levels optic_debug_level = OPTIC_DBG_OFF;
#endif
STATIC struct timer_list optic_timer[OPTIC_TIMER_GLOBAL_MAX];
void *current = NULL;
/**
Open the device.
At the first time:
- allocating internal memory for each new device
- initialize the device
\return
- 0 - if error,
- device context - if success
*/
long optic_open ( void *ctrl, const char *appendix)
{
struct optic_device *p_dev = (struct optic_device *)
IFXOS_MemAlloc(sizeof(struct optic_device));
(void) appendix;
if (optic_device_open ( (struct optic_control *) ctrl,
p_dev ) != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("Init failed");
goto OPEN_ERROR;
}
return (long) p_dev;
OPEN_ERROR:
optic_device_close ( p_dev );
return 0;
}
/**
Release the device.
\param inode pointer to the inode
\param filp pointer to the file descriptor
\return
- 0 - on success
- otherwise error code
*/
int optic_release ( void *dev )
{
struct optic_device *p_dev = (struct optic_device *) dev;
if (p_dev == NULL)
return -1;
if (optic_devicelist_delete ( p_dev->p_ctrl, p_dev ) ==
OPTIC_STATUS_ERR)
return -1;
optic_device_close( p_dev );
return 0;
}
/**
Writes data to the device.
\param filp pointer to the file descriptor
\param buf source buffer
\param count data length
\param ppos unused
\return
length or a negative error code
*/
int optic_write ( void *dev, const char *p_src, const int length )
{
int total = 0;
struct optic_device *p_dev = (struct optic_device *) dev;
(void) p_dev;
(void) p_src;
(void) length;
return total;
}
/**
Reads data from the device.
\param filp pointer to the file descriptor
\param buf destination buffer
\param count max size of data to read
\param ppos unused
\return
len - data length
*/
int optic_read ( void *dev, char *p_dst, const int length )
{
int len = 0;
struct optic_device *p_dev = (struct optic_device *) dev;
(void) p_dev;
(void) p_dst;
(void) length;
return len;
}
/**
The select function of the driver.
A user space program may sleep until the driver it wakes up.
\param
filp - pointer to the file descriptor
\param
wait - wait table
\return
- POLLIN - data available
- 0 - no data
- POLLERR - device pointer is zero
*/
int optic_poll ( void *dev )
{
struct optic_device *p_dev = (struct optic_device *) dev;
/* data available */
if (IFX_Var_Fifo_isEmpty (&p_dev->fifo_nfc.data) == 0) {
return 1;
} else {
p_dev->nfc_need_wakeup = true;
}
return 0;
}
static void cp ( struct optic_device *p_dev,
const struct optic_entry *table,
struct optic_exchange *p_exchange,
uint32_t nr,
uint8_t *buf )
{
if (_IOC_DIR(table[nr].id) & _IOC_WRITE)
memcpy(buf, p_exchange->p_data, table[nr].size_in);
if (table[nr].p_entry0) {
p_exchange->error = table[nr].p_entry0(p_dev);
} else
if (table[nr].p_entry1) {
p_exchange->error = table[nr].p_entry1(p_dev, p_dev->io_buf);
} else
if (table[nr].p_entry2) {
p_exchange->error = table[nr].p_entry2(p_dev, p_dev->io_buf,
p_dev->io_buf);
}
if (_IOC_DIR(table[nr].id) & _IOC_READ) {
memcpy (p_exchange->p_data, buf, table[nr].size_out);
p_exchange->length = table[nr].size_out;
} else {
p_exchange->length = 0;
}
}
/**
Configuration and control interface of the device.
\param inode pointer to the inode
\param filp pointer to the file descriptor
\param cmd function id's
\param arg optional argument
\return
- 0 and positive values - success,
- negative value - ioctl failed
*/
int optic_ioctl ( void *dev, unsigned int cmd, ulong_t arg)
{
int32_t ret = -1, i;
struct optic_device *p_dev = (struct optic_device *) dev;
uint8_t *buf;
struct optic_exchange *p_exchange = (struct optic_exchange *) arg;
uint32_t type = _IOC_TYPE(cmd);
uint32_t nr = _IOC_NR(cmd);
/* uint32_t size = _IOC_SIZE(cmd); */
uint32_t dir = _IOC_DIR(cmd);
(void) dir;
buf = &p_dev->io_buf[0];
#ifndef OPTIC_SIMULATION
if (size >= OPTIC_IO_BUF_SIZE)
return ret;
#endif
if ((type == OPTIC_MAGIC) && (nr < OPTIC_MAX) &&
(nr == _IOC_NR(optic_function_table[nr].id))) {
cp ( p_dev, optic_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_GOI_MAGIC) && (nr < OPTIC_GOI_MAX) &&
(nr == _IOC_NR(goi_function_table[nr].id))) {
cp ( p_dev, goi_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_FCSI_MAGIC) && (nr < OPTIC_FCSI_MAX) &&
(nr == _IOC_NR(fcsi_function_table[nr].id))) {
cp ( p_dev, fcsi_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_MM_MAGIC) && (nr < OPTIC_MM_MAX) &&
(nr == _IOC_NR(mm_function_table[nr].id))) {
cp ( p_dev, mm_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_MPD_MAGIC) && (nr < OPTIC_MPD_MAX) &&
(nr == _IOC_NR(mpd_function_table[nr].id))) {
cp ( p_dev, mpd_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_BERT_MAGIC) && (nr < OPTIC_BERT_MAX) &&
(nr == _IOC_NR(bert_function_table[nr].id))) {
cp ( p_dev, bert_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_OMU_MAGIC) && (nr < OPTIC_OMU_MAX) &&
(nr == _IOC_NR(omu_function_table[nr].id))) {
cp ( p_dev, omu_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_BOSA_MAGIC) && (nr < OPTIC_BOSA_MAX) &&
(nr == _IOC_NR(bosa_function_table[nr].id))) {
cp ( p_dev, bosa_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_CAL_MAGIC) && (nr < OPTIC_CAL_MAX) &&
(nr == _IOC_NR(cal_function_table[nr].id))) {
cp ( p_dev, cal_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_DCDC_APD_MAGIC) && (nr < OPTIC_DCDC_APD_MAX) &&
(nr == _IOC_NR(dcdc_apd_function_table[nr].id))) {
cp ( p_dev, dcdc_apd_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_DCDC_CORE_MAGIC) && (nr < OPTIC_DCDC_CORE_MAX) &&
(nr == _IOC_NR(dcdc_core_function_table[nr].id))) {
cp ( p_dev, dcdc_core_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_DCDC_DDR_MAGIC) && (nr < OPTIC_DCDC_DDR_MAX) &&
(nr == _IOC_NR(dcdc_ddr_function_table[nr].id))) {
cp ( p_dev, dcdc_ddr_function_table, p_exchange, nr, buf );
} else
if ((type == OPTIC_LDO_MAGIC) && (nr < OPTIC_LDO_MAX) &&
(nr == _IOC_NR(ldo_function_table[nr].id))) {
cp ( p_dev, ldo_function_table, p_exchange, nr, buf );
} else
#ifdef INCLUDE_CLI_SUPPORT
if ((type == _IOC_TYPE(FIO_OPTIC_CLI)) &&
(nr == _IOC_NR(FIO_OPTIC_CLI))) {
if (p_exchange->length<(OPTIC_IO_BUF_SIZE-1)) {
memcpy(buf, p_exchange->p_data, p_exchange->length + 1);
i = optic_cli ( p_dev, (char*)buf );
if ((i >= 0) && (i<(OPTIC_IO_BUF_SIZE-1))) {
memcpy(p_exchange->p_data, buf, i + 1);
p_exchange->length = i + 1;
p_exchange->error = 0;
} else {
p_exchange->length = 0;
p_exchange->error = -1;
}
}
} else
#endif
if ((type == _IOC_TYPE(FIO_OPTIC_EVENT_FIFO)) &&
(nr == _IOC_NR(FIO_OPTIC_EVENT_FIFO))) {
uint32_t len = 0;
struct optic_fifo_data *p_data = (struct optic_fifo_data *)
IFX_Var_Fifo_peekElement(&p_dev->fifo_nfc.data, &len);
if (p_data) {
memcpy(p_exchange->p_data, p_data, len);
p_exchange->length = len;
p_exchange->error = 0;
optic_fifo_read ( &p_dev->fifo_nfc, IFX_NULL, &len );
} else {
p_exchange->length = 0;
p_exchange->error = -1;
}
} else
if ((type == _IOC_TYPE(FIO_OPTIC_EVENT_SET)) &&
(nr == _IOC_NR(FIO_OPTIC_EVENT_SET))) {
enum optic_activation *p_data = (enum optic_activation *)
p_exchange->p_data;
p_dev->fifo_nfc.enable = (*p_data == OPTIC_ENABLE)?
true : false;
} else
if ((type == _IOC_TYPE(FIO_OPTIC_EVENT_GET)) &&
(nr == _IOC_NR(FIO_OPTIC_EVENT_GET))) {
enum optic_activation *p_data = (enum optic_activation *)
p_exchange->p_data;
*p_data = (p_dev->fifo_nfc.enable == true)?
OPTIC_ENABLE : OPTIC_DISABLE;
} else {
return ret;
}
return 0;
}
/**
Start optic timer
\param timer Timer Index
\param timeout Timeout in mseconds.
*/
void optic_timer_start(const uint32_t timer_no, uint32_t timeout)
{
struct timer_list *timer = &optic_timer[timer_no];
if (timer->start == false) {
timer->delay = timeout;
timer->start = true;
IFXOS_EventWakeUp(&timer->timeout_event);
}
}
/**
Stop Timer
\param timer Timer Index
*/
void optic_timer_stop ( const uint32_t timer_no )
{
struct timer_list *timer = &optic_timer[timer_no];
timer->delay = 0;
timer->start = false;
}
void optic_udelay ( uint32_t u_sec )
{
(void) u_sec;
}
#ifdef OPTIC_STATE_HOTPLUG_EVENT
void optic_hotplug_state ( const enum optic_statetype state )
{
(void) state;
}
#endif
void optic_hotplug_timestamp (const uint32_t timestamp)
{
(void) timestamp;
}
int optic_signal_pending(void *sig)
{
(void) sig;
return 0;
}
int32_t optic_spinlock_init ( optic_lock *id, const char *name )
{
if (IFXOS_MutexInit (id) != IFX_SUCCESS) {
OPTIC_DEBUG_ERR("Can't initialize %s mutex.", name);
return -1;
}
/* clear warning for unused parameter (OPTIC_DEBUG_ERR predefined) */
(void) name;
return 0;
}
int32_t optic_spinlock_delete ( optic_lock *id )
{
return IFXOS_MutexDelete(id);
}
int32_t optic_spinlock_get ( optic_lock *id, ulong_t *flags )
{
IFXOS_MutexGet(id);
(void) flags;
return 0;
}
int32_t optic_spinlock_release ( optic_lock *id, ulong_t c )
{
IFXOS_MutexRelease(id);
(void) c;
return 0;
}
int32_t optic_timer_thread ( IFXOS_ThreadParams_t *param )
{
struct timer_list *p_timer = (struct timer_list *) param->nArg1;
while (1) {
if ((p_timer->start) && (p_timer->delay)) {
IFXOS_MSecSleep (p_timer->delay);
if (p_timer->start)
p_timer->function (p_timer->data);
} else {
/* wait for Activating */
IFXOS_EventWait (&p_timer->timeout_event, 1000, NULL);
}
}
}
void init_timer ( struct timer_list *timer )
{
static uint8_t nr = 0;
char buffer[20];
sprintf(buffer, "optic-timer-%2d", nr ++);
timer->start = false;
/* Initialize timeout event */
if (IFXOS_EventInit (&timer->timeout_event) == IFX_SUCCESS) {
if (IFXOS_ThreadInit ( &timer->thread_context, buffer,
optic_timer_thread,
OPTIC_TIMER_THREAD_STACK_SIZE,
OPTIC_TIMER_THREAD_PRIO,
(ulong_t) timer, 0) == IFX_SUCCESS ) {
return;
}
}
OPTIC_DEBUG_ERR("can't start timer thread %d", nr-1);
}
void del_timer ( struct timer_list *timer )
{
IFXOS_ThreadDelete ( &timer->thread_context, 0 );
IFXOS_EventDelete ( &timer->timeout_event );
}
void optic_enable_irq (uint32_t irq)
{
(void) irq;
}
void optic_disable_irq (uint32_t irq)
{
(void) irq;
}
/**
Initialize the driver module.
\return
- 0 on success
- Error code
\remarks
Called by the kernel.
*/
int optic_init ( void )
{
char buf[64];
uint32_t i;
#ifdef INCLUDE_DEBUG_SUPPORT
optic_debug_level = (enum optic_debug_levels) 0;
#endif
OPTIC_DEBUG_MSG("DEVIO - SIMULATION ");
OPTIC_DEBUG_MSG("%s", &optic_whatversion[4]);
major_number = DEVIO_driver_install ( optic_open,
optic_release,
optic_read,
optic_write,
optic_ioctl,
optic_poll );
if (major_number == (unsigned)-1) {
OPTIC_DEBUG_ERR("can't get major %d", major_number);
return -1;
}
/*for (i = 0; i < OPTIC_TIMER_GLOBAL_MAX; i++) {
init_timer ( &optic_timer[i] );
optic_timer[i].data = i;
optic_timer[i].function = optic_timer_handler;
}*/
memset(optic_ctrl, 0x00, sizeof(optic_ctrl));
for (i = 0; i < OPTIC_INSTANCES_MAX; i++) {
sprintf(buf, "%s%d", DRV_IO_GPON_OPTIC, i);
if ((signed) DEVIO_device_add ( &optic_ctrl[i], &buf[0],
major_number) == IFX_ERROR) {
OPTIC_DEBUG_ERR("unable to create device.");
goto OPTIC_INIT_ERROR;
}
if (optic_context_init ( &optic_ctrl[i], i ) !=
OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("can't init optic context %d", i);
continue;
}
/*
OPTIC_TimerStart(&optic_timer[i], 5000);
*/
}
#ifdef INCLUDE_CLI_SUPPORT
optic_cli_init();
#endif
return 0;
OPTIC_INIT_ERROR:
optic_exit();
return -1;
}
/**
Clean up the module if unloaded.
\remarks
Called by the kernel.
*/
void optic_exit ( void )
{
int i;
DEVIO_driver_remove ( major_number, 1 );
for (i = 0; i < OPTIC_INSTANCES_MAX; i++) {
optic_context_free ( &optic_ctrl[i] );
}
OPTIC_DEBUG_MSG("cleanup successful");
}
#endif /* OPTIC_SIMULATION */
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, FCSI Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_FCSI_INTERNAL FCSI Register Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_fcsi_interface.h"
#include "drv_optic_calc.h"
#include "drv_optic_fcsi.h"
#include "drv_optic_ll_fcsi.h"
/**
Read fcsi configuration data into the context.
*/
enum optic_errorcode fcsi_cfg_set ( struct optic_device *p_dev,
const struct optic_fcsi_config *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
p_ctrl->config.fcsi.gvs = param->gvs;
if (is_falcon_chip_a2x()) { /* A21 */
p_ctrl->config.fcsi.dd_loadn[OPTIC_POWERLEVEL_0] = DD_LOADN_0_A21;
p_ctrl->config.fcsi.dd_bias_en[OPTIC_POWERLEVEL_0] = DD_BIAS_EN_0_A21;
p_ctrl->config.fcsi.dd_loadp[OPTIC_POWERLEVEL_0] = DD_LOADP_0_A21;
p_ctrl->config.fcsi.dd_cm_load[OPTIC_POWERLEVEL_0] = DD_CM_LOAD_0_A21;
p_ctrl->config.fcsi.bd_loadn[OPTIC_POWERLEVEL_0] = BD_LOADN_0_A21;
p_ctrl->config.fcsi.bd_bias_en[OPTIC_POWERLEVEL_0] = BD_BIAS_EN_0_A21;
p_ctrl->config.fcsi.bd_loadp[OPTIC_POWERLEVEL_0] = BD_LOADP_0_A21;
p_ctrl->config.fcsi.bd_cm_load[OPTIC_POWERLEVEL_0] = BD_CM_LOAD_0_A21;
p_ctrl->config.fcsi.dd_loadn[OPTIC_POWERLEVEL_1] = DD_LOADN_1_A21;
p_ctrl->config.fcsi.dd_bias_en[OPTIC_POWERLEVEL_1] = DD_BIAS_EN_1_A21;
p_ctrl->config.fcsi.dd_loadp[OPTIC_POWERLEVEL_1] = DD_LOADP_1_A21;
p_ctrl->config.fcsi.dd_cm_load[OPTIC_POWERLEVEL_1] = DD_CM_LOAD_1_A21;
p_ctrl->config.fcsi.bd_loadn[OPTIC_POWERLEVEL_1] = BD_LOADN_1_A21;
p_ctrl->config.fcsi.bd_bias_en[OPTIC_POWERLEVEL_1] = BD_BIAS_EN_1_A21;
p_ctrl->config.fcsi.bd_loadp[OPTIC_POWERLEVEL_1] = BD_LOADP_1_A21;
p_ctrl->config.fcsi.bd_cm_load[OPTIC_POWERLEVEL_1] = BD_CM_LOAD_1_A21;
p_ctrl->config.fcsi.dd_loadn[OPTIC_POWERLEVEL_2] = DD_LOADN_2_A21;
p_ctrl->config.fcsi.dd_bias_en[OPTIC_POWERLEVEL_2] = DD_BIAS_EN_2_A21;
p_ctrl->config.fcsi.dd_loadp[OPTIC_POWERLEVEL_2] = DD_LOADP_2_A21;
p_ctrl->config.fcsi.dd_cm_load[OPTIC_POWERLEVEL_2] = DD_CM_LOAD_2_A21;
p_ctrl->config.fcsi.bd_loadn[OPTIC_POWERLEVEL_2] = BD_LOADN_2_A21;
p_ctrl->config.fcsi.bd_bias_en[OPTIC_POWERLEVEL_2] = BD_BIAS_EN_2_A21;
p_ctrl->config.fcsi.bd_loadp[OPTIC_POWERLEVEL_2] = BD_LOADP_2_A21;
p_ctrl->config.fcsi.bd_cm_load[OPTIC_POWERLEVEL_2] = BD_CM_LOAD_2_A21;
} else { /* A12 */
p_ctrl->config.fcsi.dd_loadn[OPTIC_POWERLEVEL_0] = DD_LOADN_0;
p_ctrl->config.fcsi.dd_bias_en[OPTIC_POWERLEVEL_0] = DD_BIAS_EN_0;
p_ctrl->config.fcsi.dd_loadp[OPTIC_POWERLEVEL_0] = DD_LOADP_0;
p_ctrl->config.fcsi.dd_cm_load[OPTIC_POWERLEVEL_0] = DD_CM_LOAD_0;
p_ctrl->config.fcsi.bd_loadn[OPTIC_POWERLEVEL_0] = BD_LOADN_0;
p_ctrl->config.fcsi.bd_bias_en[OPTIC_POWERLEVEL_0] = BD_BIAS_EN_0;
p_ctrl->config.fcsi.bd_loadp[OPTIC_POWERLEVEL_0] = BD_LOADP_0;
p_ctrl->config.fcsi.bd_cm_load[OPTIC_POWERLEVEL_0] = BD_CM_LOAD_0;
p_ctrl->config.fcsi.dd_loadn[OPTIC_POWERLEVEL_1] = DD_LOADN_1;
p_ctrl->config.fcsi.dd_bias_en[OPTIC_POWERLEVEL_1] = DD_BIAS_EN_1;
p_ctrl->config.fcsi.dd_loadp[OPTIC_POWERLEVEL_1] = DD_LOADP_1;
p_ctrl->config.fcsi.dd_cm_load[OPTIC_POWERLEVEL_1] = DD_CM_LOAD_1;
p_ctrl->config.fcsi.bd_loadn[OPTIC_POWERLEVEL_1] = BD_LOADN_1;
p_ctrl->config.fcsi.bd_bias_en[OPTIC_POWERLEVEL_1] = BD_BIAS_EN_1;
p_ctrl->config.fcsi.bd_loadp[OPTIC_POWERLEVEL_1] = BD_LOADP_1;
p_ctrl->config.fcsi.bd_cm_load[OPTIC_POWERLEVEL_1] = BD_CM_LOAD_1;
p_ctrl->config.fcsi.dd_loadn[OPTIC_POWERLEVEL_2] = DD_LOADN_2;
p_ctrl->config.fcsi.dd_bias_en[OPTIC_POWERLEVEL_2] = DD_BIAS_EN_2;
p_ctrl->config.fcsi.dd_loadp[OPTIC_POWERLEVEL_2] = DD_LOADP_2;
p_ctrl->config.fcsi.dd_cm_load[OPTIC_POWERLEVEL_2] = DD_CM_LOAD_2;
p_ctrl->config.fcsi.bd_loadn[OPTIC_POWERLEVEL_2] = BD_LOADN_2;
p_ctrl->config.fcsi.bd_bias_en[OPTIC_POWERLEVEL_2] = BD_BIAS_EN_2;
p_ctrl->config.fcsi.bd_loadp[OPTIC_POWERLEVEL_2] = BD_LOADP_2;
p_ctrl->config.fcsi.bd_cm_load[OPTIC_POWERLEVEL_2] = BD_CM_LOAD_2;
}
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_FCSI] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return OPTIC_STATUS_OK;
}
/**
Returns fcsi configuration.
*/
enum optic_errorcode fcsi_cfg_get ( struct optic_device *p_dev,
struct optic_fcsi_config *param )
{
struct optic_bfd bfd;
enum optic_errorcode ret;
/* unused parameter */
(void)p_dev;
if (param == NULL)
return OPTIC_STATUS_ERR;
ret = optic_ll_fcsi_bfd_get (&bfd);
if (ret != OPTIC_STATUS_OK)
return ret;
param->gvs = bfd.gvs;
param->ctrl0 = bfd.ctrl0;
return OPTIC_STATUS_OK;
}
/* ----------------------------- NON IOCTL ---------------------------------- */
/**
Manages FCSI predriver configuration - dependent on power level
\remark don't call in debug mode (p_ctrl->config.debug_mode == true)
\param p_ctrl - control context
\param powerlevel - power level
\return
- OPTIC_STATUS_OK - success,
- OPTIC_STATUS_FCSI_READTIMEOUT - read failed
- OPTIC_STATUS_FCSI_WRITETIMEOUT - write failed
*/
enum optic_errorcode optic_fcsi_predriver_update ( const enum optic_powerlevel
powerlevel,
const struct
optic_config_fcsi *fcsi )
{
if (fcsi == NULL)
return OPTIC_STATUS_ERR;
return optic_fcsi_predriver_set ( fcsi->dd_loadn[powerlevel],
fcsi->dd_bias_en[powerlevel],
fcsi->dd_loadp[powerlevel],
fcsi->dd_cm_load[powerlevel],
fcsi->bd_loadn[powerlevel],
fcsi->bd_bias_en[powerlevel],
fcsi->bd_loadp[powerlevel],
fcsi->bd_cm_load[powerlevel]);
}
enum optic_errorcode optic_fcsi_predriver_set ( uint8_t dd_loadn,
uint8_t dd_bias_en,
uint8_t dd_loadp,
uint8_t dd_cm_load,
uint8_t bd_loadn,
uint8_t bd_bias_en,
uint8_t bd_loadp,
uint8_t bd_cm_load )
{
enum optic_errorcode ret;
#if (OPTIC_FCSI_PREDRIVER_RANGECHECK == ACTIVE)
ret = optic_check_predriver ( dd_loadn, dd_bias_en,
dd_loadp, dd_cm_load,
bd_loadn, bd_bias_en,
bd_loadp, bd_cm_load );
if (ret != OPTIC_STATUS_OK)
return ret;
#endif
ret = optic_ll_fcsi_predriver_set ( dd_loadn, dd_bias_en,
dd_loadp, dd_cm_load,
bd_loadn, bd_bias_en,
bd_loadp, bd_cm_load );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
enum optic_errorcode optic_fcsi_predriver_get ( uint8_t *dd_loadn,
uint8_t *dd_bias_en,
uint8_t *dd_loadp,
uint8_t *dd_cm_load,
uint8_t *bd_loadn,
uint8_t *bd_bias_en,
uint8_t *bd_loadp,
uint8_t *bd_cm_load )
{
enum optic_errorcode ret;
ret = optic_ll_fcsi_predriver_get ( dd_loadn, dd_bias_en,
dd_loadp, dd_cm_load,
bd_loadn, bd_bias_en,
bd_loadp, bd_cm_load );
if (ret != OPTIC_STATUS_OK)
return ret;
#if (OPTIC_FCSI_PREDRIVER_RANGECHECK == ACTIVE)
ret = optic_check_predriver ( *dd_loadn, *dd_bias_en,
*dd_loadp, *dd_cm_load,
*bd_loadn, *bd_bias_en,
*bd_loadp, *bd_cm_load );
if (ret != OPTIC_STATUS_OK)
return ret;
#endif
return ret;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry fcsi_function_table[OPTIC_FCSI_MAX] =
{
/* 0 */ TE1in (FIO_FCSI_CFG_SET, sizeof(struct optic_fcsi_config),
fcsi_cfg_set),
/* 1 */ TE1out (FIO_FCSI_CFG_GET, sizeof(struct optic_fcsi_config),
fcsi_cfg_get),
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_fcsi.h
*/
#ifndef _drv_optic_fcsi_h
#define _drv_optic_fcsi_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_FCSI_INTERNAL FCSI Module - Internal
@{
*/
enum optic_errorcode optic_fcsi_predriver_update ( const enum optic_powerlevel
powerlevel,
const struct
optic_config_fcsi *fcsi );
enum optic_errorcode optic_fcsi_predriver_set ( uint8_t dd_loadn,
uint8_t dd_bias_en,
uint8_t dd_loadp,
uint8_t dd_cm_load,
uint8_t bd_loadn,
uint8_t bd_bias_en,
uint8_t bd_loadp,
uint8_t bd_cm_load );
enum optic_errorcode optic_fcsi_predriver_get ( uint8_t *dd_loadn,
uint8_t *dd_bias_en,
uint8_t *dd_loadp,
uint8_t *dd_cm_load,
uint8_t *bd_loadn,
uint8_t *bd_bias_en,
uint8_t *bd_loadp,
uint8_t *bd_cm_load );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, linear LDO Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_LDO_INTERNAL Linear LDO Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_ldo_interface.h"
#include "drv_optic_ll_sys1.h"
enum optic_errorcode ldo_enable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_sys1_ldo_set ( OPTIC_ENABLE );
}
enum optic_errorcode ldo_disable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_sys1_ldo_set ( OPTIC_DISABLE );
}
enum optic_errorcode ldo_status_get ( struct optic_device *p_dev,
struct optic_ldo_status *param )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
enum optic_activation mode;
(void) p_dev;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset ( param, 0, sizeof(struct optic_ldo_status) );
ret = optic_ll_sys1_ldo_get ( &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->enable = (mode == OPTIC_ENABLE)? true : false;
return ret;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry ldo_function_table[OPTIC_LDO_MAX] =
{
/* 0 */ TE0 (FIO_LDO_ENABLE, ldo_enable),
/* 1 */ TE0 (FIO_LDO_DISABLE, ldo_disable),
/* 2 */ TE1out (FIO_LDO_STATUS_GET, sizeof(struct optic_ldo_status),
ldo_status_get),
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, PMA BERT Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_PMA_BERT_INTERNAL BERT Module - Internal
@{
*/
#include "drv_optic_ll_bert.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_pma.h"
enum optic_errorcode optic_ll_bert_init ( void )
{
enum optic_errorcode ret;
ret = optic_ll_bert_pattern_set ( 0xAAAAAAAA, 1, 1, 1, 1 );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_muxsel_set ( 2, 2, 2, 2 );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_bert_analyzer_set ( OPTIC_DISABLE );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
enum optic_errorcode optic_ll_bert_analyzer_set ( const enum optic_activation
mode )
{
pma_w32_mask ( PMA_BERT_CONTROL_ANALYZER_EN,
(mode == OPTIC_ENABLE) ? PMA_BERT_CONTROL_ANALYZER_EN: 0,
gpon_bert_pdi_bert_control );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_analyzer_get ( enum optic_activation *mode )
{
uint32_t reg;
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg = pma_r32 (gpon_bert_pdi_bert_control);
*mode = (reg & PMA_BERT_CONTROL_ANALYZER_EN) ?
OPTIC_ENABLE : OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
/** Toggles the BERT sync bit */
void optic_ll_bert_sync ()
{
uint32_t reg;
reg = pma_r32 (gpon_bert_pdi_bert_control);
/* activate sync */
pma_w32 (reg | PMA_BERT_CONTROL_SELFSYNC_EN,
gpon_bert_pdi_bert_control );
/* clear again, SW should be slow enough */
pma_w32(reg, gpon_bert_pdi_bert_control);
}
enum optic_errorcode optic_ll_bert_muxsel_set ( const uint8_t muxsel1,
const uint8_t muxsel2,
const uint8_t muxsel3,
const uint8_t muxsel4 )
{
uint32_t clear, set;
if ((muxsel1 > 3) || (muxsel2 > 3) || (muxsel3 > 3) || (muxsel4 > 3))
return OPTIC_STATUS_POOR;
clear = PMA_BERT_CONTROL_MUX_SEL1_MASK |
PMA_BERT_CONTROL_MUX_SEL2_MASK |
PMA_BERT_CONTROL_MUX_SEL3_MASK |
PMA_BERT_CONTROL_MUX_SEL4_MASK;
set = ((muxsel1 << PMA_BERT_CONTROL_MUX_SEL1_OFFSET) &
PMA_BERT_CONTROL_MUX_SEL1_MASK) |
((muxsel2 << PMA_BERT_CONTROL_MUX_SEL2_OFFSET) &
PMA_BERT_CONTROL_MUX_SEL2_MASK) |
((muxsel3 << PMA_BERT_CONTROL_MUX_SEL3_OFFSET) &
PMA_BERT_CONTROL_MUX_SEL3_MASK) |
((muxsel4 << PMA_BERT_CONTROL_MUX_SEL4_OFFSET) &
PMA_BERT_CONTROL_MUX_SEL4_MASK);
pma_w32_mask ( clear, set, gpon_bert_pdi_bert_control);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_muxsel_get ( uint8_t *muxsel1,
uint8_t *muxsel2,
uint8_t *muxsel3,
uint8_t *muxsel4 )
{
uint32_t reg;
if ((muxsel1 == NULL) || (muxsel2 == NULL) ||
(muxsel3 == NULL) || (muxsel4 == NULL))
return OPTIC_STATUS_ERR;
reg = pma_r32 (gpon_bert_pdi_bert_control);
*muxsel1 = (reg & PMA_BERT_CONTROL_MUX_SEL1_MASK) >>
PMA_BERT_CONTROL_MUX_SEL1_OFFSET;
*muxsel2 = (reg & PMA_BERT_CONTROL_MUX_SEL2_MASK) >>
PMA_BERT_CONTROL_MUX_SEL2_OFFSET;
*muxsel3 = (reg & PMA_BERT_CONTROL_MUX_SEL3_MASK) >>
PMA_BERT_CONTROL_MUX_SEL3_OFFSET;
*muxsel4 = (reg & PMA_BERT_CONTROL_MUX_SEL4_MASK) >>
PMA_BERT_CONTROL_MUX_SEL4_OFFSET;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_pattern_set ( const uint32_t pattern,
const uint8_t ecount1,
const uint8_t ecount2,
const uint8_t ecount3,
const uint8_t ecount4 )
{
uint32_t reg;
reg = (pattern << PMA_BERT_PATTERN_FIXEDIN_OFFSET) &
PMA_BERT_PATTERN_FIXEDIN_MASK;
pma_w32 ( reg, gpon_bert_pdi_bert_pattern);
reg = ((ecount1 << PMA_BERT_CNT_ENDCOUNTER_1_OFFSET) &
PMA_BERT_CNT_ENDCOUNTER_1_MASK) |
((ecount2 << PMA_BERT_CNT_ENDCOUNTER_2_OFFSET) &
PMA_BERT_CNT_ENDCOUNTER_2_MASK) |
((ecount3 << PMA_BERT_CNT_ENDCOUNTER_3_OFFSET) &
PMA_BERT_CNT_ENDCOUNTER_3_MASK) |
((ecount4 << PMA_BERT_CNT_ENDCOUNTER_4_OFFSET) &
PMA_BERT_CNT_ENDCOUNTER_4_MASK);
pma_w32 ( reg, gpon_bert_pdi_bert_cnt);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_pattern_get ( uint32_t *pattern,
uint8_t *ecount1,
uint8_t *ecount2,
uint8_t *ecount3,
uint8_t *ecount4 )
{
uint32_t reg;
if (pattern == NULL)
return OPTIC_STATUS_ERR;
if ((ecount1 == NULL) || (ecount2 == NULL) ||
(ecount3 == NULL) || (ecount4 == NULL))
return OPTIC_STATUS_ERR;
reg = pma_r32 ( gpon_bert_pdi_bert_pattern );
*pattern = (reg & PMA_BERT_PATTERN_FIXEDIN_MASK) >>
PMA_BERT_PATTERN_FIXEDIN_OFFSET;
reg = pma_r32 (gpon_bert_pdi_bert_cnt);
*ecount1 = (reg & PMA_BERT_CNT_ENDCOUNTER_1_MASK) >>
PMA_BERT_CNT_ENDCOUNTER_1_OFFSET;
*ecount2 = (reg & PMA_BERT_CNT_ENDCOUNTER_2_MASK) >>
PMA_BERT_CNT_ENDCOUNTER_2_OFFSET;
*ecount3 = (reg & PMA_BERT_CNT_ENDCOUNTER_3_MASK) >>
PMA_BERT_CNT_ENDCOUNTER_3_OFFSET;
*ecount4 = (reg & PMA_BERT_CNT_ENDCOUNTER_4_MASK) >>
PMA_BERT_CNT_ENDCOUNTER_4_OFFSET;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_clk_set ( const uint8_t clk_period,
const uint8_t clk_high )
{
uint32_t reg;
reg = ((clk_period << PMA_BERT_CLK_GENCLKPERIOD_OFFSET) &
PMA_BERT_CLK_GENCLKPERIOD_MASK) |
((clk_high << PMA_BERT_CLK_GENCLKHI_OFFSET) &
PMA_BERT_CLK_GENCLKHI_MASK);
pma_w32 ( reg, gpon_bert_pdi_bert_clk );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_clk_get ( uint8_t *clk_period,
uint8_t *clk_high )
{
uint32_t reg;
if ((clk_period == NULL) || (clk_high == NULL))
return OPTIC_STATUS_ERR;
reg = pma_r32 ( gpon_bert_pdi_bert_clk );
*clk_period = (reg & PMA_BERT_CLK_GENCLKPERIOD_MASK) >>
PMA_BERT_CLK_GENCLKPERIOD_OFFSET;
*clk_high = (reg & PMA_BERT_CLK_GENCLKHI_MASK) >>
PMA_BERT_CLK_GENCLKHI_OFFSET;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_prbs_set ( const uint8_t prbsType )
{
pma_w32_mask ( PMA_BERT_CONTROL_PRBS_SEL_MASK,
(prbsType << PMA_BERT_CONTROL_PRBS_SEL_OFFSET) &
PMA_BERT_CONTROL_PRBS_SEL_MASK,
gpon_bert_pdi_bert_control );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_prbs_get ( uint8_t *prbs_type )
{
uint32_t reg;
if (prbs_type == NULL)
return OPTIC_STATUS_ERR;
reg = pma_r32 ( gpon_bert_pdi_bert_control );
*prbs_type = (reg & PMA_BERT_CONTROL_PRBS_SEL_MASK) >>
PMA_BERT_CONTROL_PRBS_SEL_OFFSET;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_speed_set ( const bool speedrate_high_tx,
const bool speedrate_high_rx )
{
uint32_t clear = PMA_BERT_CONTROL_MODE_2G5_TX |
PMA_BERT_CONTROL_MODE_2G5_RX;
uint32_t set =0;
if (speedrate_high_tx == true)
set |= PMA_BERT_CONTROL_MODE_2G5_TX;
if (speedrate_high_rx == true)
set |= PMA_BERT_CONTROL_MODE_2G5_RX;
pma_w32_mask ( clear, set, gpon_bert_pdi_bert_control );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_speed_get ( bool *speedrate_high_tx,
bool *speedrate_high_rx )
{
uint32_t reg;
if ((speedrate_high_tx == NULL) || (speedrate_high_rx == NULL))
return OPTIC_STATUS_ERR;
reg = pma_r32 ( gpon_bert_pdi_bert_control );
*speedrate_high_tx = (reg & PMA_BERT_CONTROL_MODE_2G5_TX)? true : false;
*speedrate_high_rx = (reg & PMA_BERT_CONTROL_MODE_2G5_RX)? true : false;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_loop_set ( const enum optic_activation mode )
{
pma_w32_mask ( PMA_BERT_CONTROL_LOOPBACK_ENABLE,
(mode == OPTIC_ENABLE) ?
PMA_BERT_CONTROL_LOOPBACK_ENABLE: 0,
gpon_bert_pdi_bert_control );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_loop_get ( enum optic_activation *mode )
{
uint32_t reg;
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg = pma_r32 (gpon_bert_pdi_bert_control);
*mode = (reg & PMA_BERT_CONTROL_LOOPBACK_ENABLE) ?
OPTIC_ENABLE : OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_counter_get ( uint32_t *word_cnt,
uint32_t *error_cnt )
{
if (word_cnt != NULL)
*word_cnt = pma_r32 (gpon_bert_pdi_bert_wrdcnt);
if (error_cnt != NULL)
*error_cnt = pma_r32 (gpon_bert_pdi_bert_errcnt);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_bert_counter_config ( const enum optic_bert_cnt
mode )
{
uint32_t reg;
switch (mode) {
case OPTIC_BERTCNT_RESET:
reg = PMA_BERT_STATUSCTRL_WORD_RESET |
PMA_BERT_STATUSCTRL_ERROR_RESET;
break;
case OPTIC_BERTCNT_FREEZE:
reg = PMA_BERT_STATUSCTRL_COUNTER_FREEZE;
break;
case OPTIC_BERTCNT_RUN:
reg = 0;
break;
default:
return OPTIC_STATUS_POOR;
}
pma_w32 (reg, gpon_bert_pdi_bert_statusctrl);
return OPTIC_STATUS_OK;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_bert.h
*/
#ifndef _drv_optic_ll_bert_h
#define _drv_optic_ll_bert_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_PMA_BERT_INTERNAL BERT Module - Internal
@{
*/
enum optic_bert_cnt
{
OPTIC_BERTCNT_RESET,
OPTIC_BERTCNT_FREEZE,
OPTIC_BERTCNT_RUN
};
enum optic_errorcode optic_ll_bert_init ( void );
enum optic_errorcode optic_ll_bert_analyzer_set ( const enum optic_activation mode );
enum optic_errorcode optic_ll_bert_analyzer_get ( enum optic_activation *mode );
void optic_ll_bert_sync ( void );
enum optic_errorcode optic_ll_bert_muxsel_set ( const uint8_t muxsel1,
const uint8_t muxsel2,
const uint8_t muxsel3,
const uint8_t muxsel4 );
enum optic_errorcode optic_ll_bert_muxsel_get ( uint8_t *muxsel1,
uint8_t *muxsel2,
uint8_t *muxsel3,
uint8_t *muxsel4 );
enum optic_errorcode optic_ll_bert_endcounter_set ( const uint8_t ecount1,
const uint8_t ecount2,
const uint8_t ecount3,
const uint8_t ecount4 );
enum optic_errorcode optic_ll_bert_endcounter_get ( uint8_t *ecount1,
uint8_t *ecount2,
uint8_t *ecount3,
uint8_t *ecount4 );
enum optic_errorcode optic_ll_bert_pattern_set ( const uint32_t pattern,
const uint8_t ecount1,
const uint8_t ecount2,
const uint8_t ecount3,
const uint8_t ecount4 );
enum optic_errorcode optic_ll_bert_pattern_get ( uint32_t *pattern,
uint8_t *ecount1,
uint8_t *ecount2,
uint8_t *ecount3,
uint8_t *ecount4 );
enum optic_errorcode optic_ll_bert_clk_set ( const uint8_t clk_period,
const uint8_t clk_high );
enum optic_errorcode optic_ll_bert_clk_get ( uint8_t *clk_period,
uint8_t *clk_high );
enum optic_errorcode optic_ll_bert_prbs_set ( const uint8_t prbs_type );
enum optic_errorcode optic_ll_bert_prbs_get ( uint8_t *prbs_type );
enum optic_errorcode optic_ll_bert_speed_set ( const bool speedrate_high_tx,
const bool speedrate_high_rx );
enum optic_errorcode optic_ll_bert_speed_get ( bool *speedrate_high_tx,
bool *speedrate_high_rx );
enum optic_errorcode optic_ll_bert_loop_set ( const enum optic_activation mode );
enum optic_errorcode optic_ll_bert_loop_get ( enum optic_activation *mode );
enum optic_errorcode optic_ll_bert_counter_get ( uint32_t *word_cnt,
uint32_t *error_cnt );
enum optic_errorcode optic_ll_bert_counter_config ( const enum optic_bert_cnt
mode );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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src/drv_optic_ll_dcdc_apd.c Normal file
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@ -0,0 +1,605 @@
/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, DCDC APD Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_STATUS_DCDC_APD_INTERNAL DC/DC APD Converter Module - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_calc.h"
#include "drv_optic_ll_dcdc_apd.h"
#if (defined(LINUX) && defined(__KERNEL__)) || defined(OPTIC_LIBRARY)
#if defined(OPTIC_LIBRARY)
#include <sysctrl.h>
#include <reg/sys1_reg.h>
#else
#include <falcon/sysctrl.h>
#include <falcon/sys1_reg.h>
#endif
#endif
#include "drv_optic_reg_dcdc.h"
/**
init APD DCDC module
- DCDC_PID_HI_B0 = 0
- DCDC_PID_LO_B0 = 0
- DCDC_PID_HI_B1 = 0xF6 Kp = 1/Ks
- DCDC_PID_LO_B1 = 0
- DCDC_PID_HI_B2 = 0x0A
- DCDC_PID_LO_B2 = 0x01
- DCDC_CLK_SET0 = 0x26 1440 MHz VDSL, 1000MHz non-VDSL
- DCDC_CLK_SET1 = 0x01 bias resistance = 1
- DCDC_PWM0 = 0xFF Counter pre-load = 255
- DCDC_PWM1 = 0 Static Duty Cycle Value = 0
- DCDC_BIAS_VREG = 0x10 vreg_sel = nominal value 1.05V
- DCDC_PDI_DIG_REF = 0x7F v=127, nominal value 1,0V
- DCDC_GENERAL = 0x8C OS_EN=1, SET_LSB_DIGREF=1
- DCDC_ADC0 = 0x62 SET_COMP2ARITH=2, SET_COMP2ARRAY=4,
SET_ROM_SEL=1
- DCDC_ADC1 = 0x12 SET_OFFSET_CAL_EN=1, SET_COMP_CURR=4
- DCDC_ADC2 = 0x77 SET_ROM_START=7, SET_START=7
- DCDC_CONF_TEST_ANA_NOAUTO = 0x78
- DCDC_CONF_TEST_ANA_NOAUTO = 0
- DCDC_DUTY_CYCLE = 0
- DCDC_NON_OV_DELAY = 0x47
- DCDC_ANALOG_GAIN = 0
- DCDC_DUTY_CYCLE_MAX_SAT = 0x34
- DCDC_DUTY_CYCLE_MIN_SAT = 0x07
- DCDC_DUTY_CYCLE_MAX = 0xFF
- DCDC_DUTY_CYCLE_MIN = 0
- DCDC_ERROR_MAX = 0xFF
- DCDC_DELAY_DEGLITCH = 0x7F 128 DCDC cycle, deglitch 15 DCDC cycles
- DCDC_LATCH_CONTROL_NOAUTO = 0x01 CAP_CLK_MODE=1
- DCDC_CAP_CLK_CNT = 0x80
- DCDC_MDLL_DIVIDER = 0x03 DIVIDER=3, divide by 4
*/
enum optic_errorcode optic_ll_dcdc_apd_init ( void )
{
#if (defined(LINUX) && defined(__KERNEL__)) || defined(OPTIC_LIBRARY)
/* fbs0/sys1 clock enable for DCDC APD */
sys1_hw_activate ( CLKS_DCDCAPD_EN );
#endif
/* reset */
dcdc_apd_w8( 0x00, pdi_pid_hi_b0);
dcdc_apd_w8( 0x00, pdi_pid_lo_b0);
/* Kp = 1/Ks */
dcdc_apd_w8( 0xF6, pdi_pid_hi_b1);
dcdc_apd_w8( 0x00, pdi_pid_lo_b1);
/*
dcdc_apd_w8( 0x91, pdi_pid_hi_b2);
dcdc_apd_w8( 0x84, pdi_pid_lo_b2);
*/
dcdc_apd_w8( 0x0A, pdi_pid_hi_b2);
dcdc_apd_w8( 0x01, pdi_pid_lo_b2);
/* 1440 MHz VDSL, 1000MHz non-VDSL */
dcdc_apd_w8( 0x26, pdi_clk_set0);
/* bias resistance = 1 */
dcdc_apd_w8( 0x01, pdi_clk_set1);
/* Counter pre-load = 255 */
dcdc_apd_w8( 0xFF, pdi_pwm0);
/* Static Duty Cycle Value = 0 */
dcdc_apd_w8( 0x00, pdi_pwm1);
/* vreg_sel = nominal value 1.05V */
dcdc_apd_w8( 0x10, pdi_bias_vreg);
/* v=127, nominal value 1,0V */
/* dcdc_apd_w8( 0xB2, dcdc_pdi_dig_ref); */
dcdc_apd_w8( 0x53, pdi_dig_ref);
/* OS_EN=1, SET_LSB_DIGREF=1
!! instead of 0x8c: the output needs to be inverted!! */
dcdc_apd_w8( 0x9C, pdi_general);
/* SET_COMP2ARITH=2, SET_COMP2ARRAY=4, SET_ROM_SEL=1 */
dcdc_apd_w8( 0x62, pdi_adc0);
/* SET_OFFSET_CAL_EN=1, SET_COMP_CURR=4 */
dcdc_apd_w8( 0x12, pdi_adc1);
/* SET_ROM_START=7, SET_START=7 */
dcdc_apd_w8( 0x77, pdi_adc2);
dcdc_apd_w8( 0x78, pdi_conf_test_ana_noauto);
dcdc_apd_w8( 0x00, pdi_conf_test_dig_noauto);
dcdc_apd_w8( 0x00, pdi_duty_cycle);
dcdc_apd_w8( 0x47, pdi_non_ov_delay);
dcdc_apd_w8( 0x00, pdi_analog_gain);
/* dcdc_apd_w8( 0x6C, dcdc_pdi_duty_cycle_max_sat); */
dcdc_apd_w8( 0x34, pdi_duty_cycle_max_sat);
dcdc_apd_w8( 0x07, pdi_duty_cycle_min_sat);
dcdc_apd_w8( 0xFF, pdi_duty_cycle_max);
dcdc_apd_w8( 0x00, pdi_duty_cycle_min);
dcdc_apd_w8( 0xFF, pdi_error_max);
/* 128 DCDC cycle, deglitch 15 DCDC cycles */
dcdc_apd_w8( 0x07, pdi_delay_deglitch);
/* CAP_CLK_MODE=1 */
dcdc_apd_w8( 0x21, pdi_latch_control_noauto);
dcdc_apd_w8( 0x80, pdi_cap_clk_cnt);
/* DIVIDER=3, divide by 4 */
dcdc_apd_w8( 0x03, pdi_mdll_divider);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
optic_ll_dcdc_apd_dump ();
#endif
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_apd_exit ( void )
{
#if defined(LINUX) && defined(__KERNEL__)
/* fbs0/sys1 clock disable for DCDC APD */
sys1_hw_deactivate ( CLKS_DCDCAPD_EN );
#endif
/* reset */
dcdc_apd_w8( 0x00, pdi_pid_hi_b0);
dcdc_apd_w8( 0x00, pdi_pid_lo_b0);
dcdc_apd_w8( 0x00, pdi_pid_hi_b1);
dcdc_apd_w8( 0x00, pdi_pid_lo_b1);
dcdc_apd_w8( 0x00, pdi_pid_hi_b2);
dcdc_apd_w8( 0x00, pdi_pid_lo_b2);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP == ACTIVE))
optic_ll_dcdc_apd_dump ();
#endif
return OPTIC_STATUS_OK;
}
/**
Activates/deactivates APD DCDC.
*/
enum optic_errorcode optic_ll_dcdc_apd_set ( const enum optic_activation mode )
{
uint32_t reg;
enum optic_activation mode_actual;
if (mode == OPTIC_ENABLE) {
/* if already enabled do not enable again
* as it influences HW regulation */
optic_ll_dcdc_apd_get(&mode_actual);
if (mode_actual == OPTIC_ENABLE)
return OPTIC_STATUS_OK;
reg = DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_ADC_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_MDLL_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_DPWM_N;
dcdc_apd_w8( reg, pdi_conf_test_ana_noauto);
/* perform 1-0-1 transition for pid bit */
dcdc_apd_w8( DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_PID_N,
pdi_conf_test_dig_noauto);
dcdc_apd_w8( 0x00, pdi_conf_test_dig_noauto);
reg = DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_PID_N |
DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_RAMPUP_N;
dcdc_apd_w8( reg, pdi_conf_test_dig_noauto);
dcdc_apd_w8_mask( DCDC_LATCH_CONTROL_NOAUTO_NFORCE_EN,
DCDC_LATCH_CONTROL_NOAUTO_CAP_CLK_MODE,
pdi_latch_control_noauto);
} else {
dcdc_apd_w8( DCDC_LATCH_CONTROL_NOAUTO_CAP_CLK_MODE |
DCDC_LATCH_CONTROL_NOAUTO_NFORCE_EN,
pdi_latch_control_noauto);
dcdc_apd_w8( 0x78, pdi_conf_test_ana_noauto);
dcdc_apd_w8( 0x00, pdi_conf_test_dig_noauto);
}
return OPTIC_STATUS_OK;
}
/**
Reads back DCDC APD mode (enable/disable).
*/
enum optic_errorcode optic_ll_dcdc_apd_get ( enum optic_activation *mode )
{
uint32_t reg_ana, reg_dig;
uint32_t reg_ana_enable, reg_dig_enable;
reg_ana_enable = (DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_ADC_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_MDLL_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_DPWM_N);
reg_dig_enable = (DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_PID_N |
DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_RAMPUP_N);
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg_ana = dcdc_apd_r8( pdi_conf_test_ana_noauto);
reg_dig = dcdc_apd_r8( pdi_conf_test_dig_noauto);
if ((reg_ana & reg_ana_enable) != reg_ana_enable) {
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
if ((reg_dig & reg_dig_enable) != reg_dig_enable) {
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
*mode = OPTIC_ENABLE;
return OPTIC_STATUS_OK;
}
/**
Set the APD Voltage.
This function controls the APD DC/DC converter.
If the APD voltage is to be switched on, a voltage ramp is generated.
If already on, and the voltage difference is < 1V,
only the voltage values is changed.
If already on, and the voltage change is greater than 1 V,
the voltage shall be changed gradually to avoid overshoots
(>1 ms wait time between the voltage steps, 1 V per step).
*/
enum optic_errorcode optic_ll_dcdc_apd_voltage_set (
const int8_t offset_dcdc_apd,
const uint8_t gain_dcdc_apd,
const uint16_t ext_att,
const uint16_t vapd_desired,
uint16_t *vapd_actual )
{
enum optic_errorcode ret = OPTIC_STATUS_OK;
uint16_t vapd_read;
int16_t regulation_error;
uint16_t vapd_target;
uint16_t vapd_regulation = (1 << OPTIC_FLOAT2INTSHIFT_VOLTAGE)/4;
/* dig. representation of 1V at the ADC output, used for voltage ramp */
uint16_t vapd_step = (1 << OPTIC_FLOAT2INTSHIFT_VOLTAGE);
uint16_t vapd_min = (20 << OPTIC_FLOAT2INTSHIFT_VOLTAGE); /* same for 20V */
uint32_t reg_write, reg_read;
uint32_t temp;
if (vapd_desired == 0)
return OPTIC_STATUS_ERR;
/* &vapd_read = [dig] actual DCDC Voltage at the ADC output.FdS=1V=2^9 */
/* &regulation_error = reg.error at the ADC output, not used here at the moment */
ret = optic_ll_dcdc_apd_voltage_get ( offset_dcdc_apd,
gain_dcdc_apd,
ext_att,
&vapd_read,
&regulation_error );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_ll_dcdc_apd_voltage_get(): %d", ret);
return ret;
}
/* DCDC APD not ready for next step: regulation error < threshold */
if (abs(regulation_error) > vapd_regulation) {
return OPTIC_STATUS_DCDC_APD_RAMP_WAIT;
}
/* SW ramp: change of the ramp target of +/- 1V respect to the read value,
allowed if the error is more than 1V,
determine direction of SW ramp */
if (vapd_read >= (vapd_desired + vapd_step)) {
/*if the read value is too big, reduce the target by 1V */
vapd_target = vapd_read - vapd_step;
}
else
{
if(vapd_read <= (vapd_desired - vapd_step)) {
/*if the read value is too low, increase the target by 1V */
vapd_target = vapd_read + vapd_step;
}
else {
/* desired value vapd_desired is kept as it is */
vapd_target = vapd_desired;
}
}
if (vapd_target < vapd_min)
vapd_target = vapd_min;
/**
VAPD * 512
---------- - 3
extAtt fuse_gain * 0.2
VREF = ---------------- * ( 0.9 + --------------- ) + fuse_offset
4 64
VAPD * 512
---------- - 3
extAtt 288 + fuse_gain
VREF = --------------- * ----------------- + fuse_offset
4 320
VAPD [<<OPTIC_FLOAT2INTSHIFT_VOLTAGE]
extAtt [<<OPTIC_FLOAT2INTSHIFT_EXTATT]
VAPD * 512 << OPTIC_FLOAT2INTSHIFT_EXTATT
----------------------------------------- - (3 << OPTIC_FLOAT2INTSHIFT_VOLTAGE)
extAtt 288 + fuse_gain
VREF = ---------------------------------------------------------------------------------- * ------------------------------------- + fuse_offset
4 320 << OPTIC_FLOAT2INTSHIFT_VOLTAGE
VAPD << (OPTIC_FLOAT2INTSHIFT_EXTATT +7) 288 + fuse_gain
VREF = ( ------------------------------------------ - (3 << OPTIC_FLOAT2INTSHIFT_VOLTAGE-2) ) * ------------------------------------ + fuse_offset
extAtt 320 << OPTIC_FLOAT2INTSHIFT_VOLTAGE
*/
temp = vapd_target << (OPTIC_FLOAT2INTSHIFT_EXTATT + 7);
temp = optic_uint_div_rounded ( temp, ext_att );
temp -= (3 << (OPTIC_FLOAT2INTSHIFT_VOLTAGE-2));
temp *= (288 + gain_dcdc_apd);
temp = optic_uint_div_rounded ( temp,
320 <<
OPTIC_FLOAT2INTSHIFT_VOLTAGE );
reg_write = temp + offset_dcdc_apd;
/* read "last" reference value */
reg_read = dcdc_apd_r8 ( pdi_dig_ref );
if(reg_read != reg_write) {
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("writing pdi_dig_ref = %d now...", reg_write);
#endif
/* set reference value */
dcdc_apd_w8 ( reg_write, pdi_dig_ref );
}
if (vapd_target == vapd_desired) {
/* desired voltage has been reached */
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("OPTIC_STATUS_DCDC_APD_CHANGE vapd_desired=%d vapd_target=%d", vapd_desired, vapd_target);
#endif
ret = OPTIC_STATUS_DCDC_APD_CHANGE;
} else {
/* desired voltage has not been reached, we still need to ramp with steps */
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("OPTIC_STATUS_DCDC_APD_RAMP vapd_desired=%d vapd_target=%d", vapd_desired, vapd_target);
#endif
/* return the actual voltage to the top level function */
*vapd_actual = vapd_target;
ret = OPTIC_STATUS_DCDC_APD_RAMP;
}
return ret;
}
enum optic_errorcode optic_ll_dcdc_apd_voltage_get ( const int8_t
offset_dcdc_apd,
const uint8_t
gain_dcdc_apd,
const uint16_t ext_att,
uint16_t *vapd_read,
int16_t *regulation_error )
{
uint32_t reg;
uint32_t temp;
int32_t tempi;
int32_t pdi_error;
if (vapd_read == NULL)
return OPTIC_STATUS_ERR;
if (regulation_error == NULL)
return OPTIC_STATUS_ERR;
/**
VAPD * 512
---------- - 3
extAtt fuse_gain * 0.2
VREF = ---------------- * ( 0.9 + --------------- ) + fuse_offset
4 64
VAPD * 512
---------- - 3
extAtt 288 + fuse_gain
VREF = --------------- * ----------------- + fuse_offset
4 320
VAPD * 512
---------- - 3
extAtt ( VREF - fuse_offset ) * 320
--------------- = -----------------------------
4 288 + fuse_gain
VAPD * 512 ( VREF - fuse_offset ) * 1280
---------- = ------------------------------ + 3
extAtt 288 + fuse_gain
( VREF - fuse_offset ) * 1280 extAtt
VAPD = (------------------------------ + 3 ) * ------
288 + fuse_gain 512
VAPD [<<OPTIC_FLOAT2INTSHIFT_VOLTAGE]
extAtt [<<OPTIC_FLOAT2INTSHIFT_EXTATT]
( VREF - fuse_offset ) * 1280 <<OPTIC_FLOAT2INTSHIFT_VOLTAGE
VAPD = (------------------------------ ------------------------------- + 3 <<OPTIC_FLOAT2INTSHIFT_VOLTAGE ) * extAtt >> (OPTIC_FLOAT2INTSHIFT_EXTATT + 9)
288 + fuse_gain
*/
reg = dcdc_apd_r8 ( pdi_dig_ref );
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("optic_ll_dcdc_apd_voltage_get: digref %d", reg);
#endif
/* the uint temp must not be negative!! */
tempi = reg-offset_dcdc_apd;
if (tempi < 0)
tempi = 0;
temp = tempi * (1280 << OPTIC_FLOAT2INTSHIFT_VOLTAGE);
temp = optic_uint_div_rounded ( temp , 288 + gain_dcdc_apd );
temp += (3 << OPTIC_FLOAT2INTSHIFT_VOLTAGE);
temp = optic_uint_div_rounded ( temp , 1 << 9 );
temp *= ext_att;
*vapd_read = (uint16_t) optic_uint_div_rounded ( temp,
1 << OPTIC_FLOAT2INTSHIFT_EXTATT );
/* register value 1 digit = 120mV */
reg = dcdc_apd_r8 ( pdi_error_read );
pdi_error = (int8_t) reg;
#if (OPTIC_APD_DEBUG == ACTIVE)
OPTIC_DEBUG_ERR("optic_ll_dcdc_apd_voltage_get: "
"pdi_error(bit) = %d, vapd_read = %d",
pdi_error,
*vapd_read);
#endif
pdi_error = pdi_error * (60 << OPTIC_FLOAT2INTSHIFT_VOLTAGE); /* 60 [V] */
*regulation_error = (int16_t) optic_int_div_rounded ( pdi_error, 1000 ); /* [V] scaling */
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_apd_saturation_set ( const uint8_t sat )
{
uint32_t reg = sat;
/* set duty cycle saturation */
dcdc_apd_w8 ( reg, pdi_duty_cycle_max_sat );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_apd_saturation_get ( uint8_t *sat )
{
uint32_t reg;
if (sat == NULL)
return OPTIC_STATUS_ERR;
/* set duty cycle saturation */
reg = dcdc_apd_r8 ( pdi_duty_cycle_max_sat );
*sat = reg & 0xFF;
return OPTIC_STATUS_OK;
}
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
enum optic_errorcode optic_ll_dcdc_apd_dump ( void )
{
OPTIC_DEBUG_WRN("DCDC APD #0: 0x%02X",
dcdc_apd_r8(pdi_pid_hi_b0));
OPTIC_DEBUG_WRN("DCDC APD #1: 0x%02X",
dcdc_apd_r8(pdi_pid_lo_b0));
OPTIC_DEBUG_WRN("DCDC APD #2: 0x%02X",
dcdc_apd_r8(pdi_pid_hi_b1));
OPTIC_DEBUG_WRN("DCDC APD #3: 0x%02X",
dcdc_apd_r8(pdi_pid_lo_b1));
OPTIC_DEBUG_WRN("DCDC APD #4: 0x%02X",
dcdc_apd_r8(pdi_pid_hi_b2));
OPTIC_DEBUG_WRN("DCDC APD #5: 0x%02X",
dcdc_apd_r8(pdi_pid_lo_b2));
OPTIC_DEBUG_WRN("DCDC APD #6: 0x%02X",
dcdc_apd_r8(pdi_clk_set0));
OPTIC_DEBUG_WRN("DCDC APD #7: 0x%02X",
dcdc_apd_r8(pdi_clk_set1));
OPTIC_DEBUG_WRN("DCDC APD #8: 0x%02X",
dcdc_apd_r8(pdi_pwm0));
OPTIC_DEBUG_WRN("DCDC APD #9: 0x%02X",
dcdc_apd_r8(pdi_pwm1));
OPTIC_DEBUG_WRN("DCDC APD #10: 0x%02X",
dcdc_apd_r8(pdi_bias_vreg));
OPTIC_DEBUG_WRN("DCDC APD #11: 0x%02X",
dcdc_apd_r8(pdi_dig_ref));
OPTIC_DEBUG_WRN("DCDC APD #12: 0x%02X",
dcdc_apd_r8(pdi_general));
OPTIC_DEBUG_WRN("DCDC APD #13: 0x%02X",
dcdc_apd_r8(pdi_adc0));
OPTIC_DEBUG_WRN("DCDC APD #14: 0x%02X",
dcdc_apd_r8(pdi_adc1));
OPTIC_DEBUG_WRN("DCDC APD #15: 0x%02X",
dcdc_apd_r8(pdi_adc2));
OPTIC_DEBUG_WRN("DCDC APD #16: 0x%02X",
dcdc_apd_r8(pdi_conf_test_ana));
OPTIC_DEBUG_WRN("DCDC APD #17: 0x%02X",
dcdc_apd_r8(pdi_conf_test_dig));
OPTIC_DEBUG_WRN("DCDC APD #18: 0x%02X",
dcdc_apd_r8(pdi_conf_test_ana_noauto));
OPTIC_DEBUG_WRN("DCDC APD #19: 0x%02X",
dcdc_apd_r8(pdi_conf_test_dig_noauto));
OPTIC_DEBUG_WRN("DCDC APD #20: 0x%02X",
dcdc_apd_r8(pdi_dcdc_status));
OPTIC_DEBUG_WRN("DCDC APD #21: 0x%02X",
dcdc_apd_r8(pdi_pid_status));
OPTIC_DEBUG_WRN("DCDC APD #22: 0x%02X",
dcdc_apd_r8(pdi_duty_cycle));
OPTIC_DEBUG_WRN("DCDC APD #23: 0x%02X",
dcdc_apd_r8(pdi_non_ov_delay));
OPTIC_DEBUG_WRN("DCDC APD #24: 0x%02X",
dcdc_apd_r8(pdi_analog_gain));
OPTIC_DEBUG_WRN("DCDC APD #25: 0x%02X",
dcdc_apd_r8(pdi_duty_cycle_max_sat));
OPTIC_DEBUG_WRN("DCDC APD #26: 0x%02X",
dcdc_apd_r8(pdi_duty_cycle_min_sat));
OPTIC_DEBUG_WRN("DCDC APD #27: 0x%02X",
dcdc_apd_r8(pdi_duty_cycle_max));
OPTIC_DEBUG_WRN("DCDC APD #28: 0x%02X",
dcdc_apd_r8(pdi_duty_cycle_min));
OPTIC_DEBUG_WRN("DCDC APD #29: 0x%02X",
dcdc_apd_r8(pdi_error_max));
OPTIC_DEBUG_WRN("DCDC APD #30: 0x%02X",
dcdc_apd_r8(pdi_error_read));
OPTIC_DEBUG_WRN("DCDC APD #31: 0x%02X",
dcdc_apd_r8(pdi_delay_deglitch));
OPTIC_DEBUG_WRN("DCDC APD #32: 0x%02X",
dcdc_apd_r8(pdi_latch_control));
OPTIC_DEBUG_WRN("DCDC APD #33: 0x%02X",
dcdc_apd_r8(pdi_latch_control_noauto));
OPTIC_DEBUG_WRN("DCDC APD #34: 0x%02X",
dcdc_apd_r8(pdi_cap_clk_cnt));
OPTIC_DEBUG_WRN("DCDC APD #35: 0x%02X",
dcdc_apd_r8(pdi_mdll_divider));
return OPTIC_STATUS_OK;
}
#endif
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_dcdc_apd.h
*/
#ifndef _drv_optic_ll_dcdc_apd_h
#define _drv_optic_ll_dcdc_apd_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_DCDC_APD_INTERNAL DC/DC APD Converter Module - Internal
@{
*/
enum optic_errorcode optic_ll_dcdc_apd_init ( void );
enum optic_errorcode optic_ll_dcdc_apd_exit ( void );
enum optic_errorcode optic_ll_dcdc_apd_set ( const enum optic_activation mode );
enum optic_errorcode optic_ll_dcdc_apd_get ( enum optic_activation *mode );
enum optic_errorcode optic_ll_dcdc_apd_voltage_set ( const int8_t
offset_dcdc_apd,
const uint8_t
gain_dcdc_apd,
const uint16_t ext_att,
const uint16_t vapd_desired,
uint16_t *vapd_actual
);
enum optic_errorcode optic_ll_dcdc_apd_voltage_get ( const int8_t
offset_dcdc_apd,
const uint8_t
gain_dcdc_apd,
const uint16_t ext_att,
uint16_t *vapd_read,
int16_t *reg_error );
enum optic_errorcode optic_ll_dcdc_apd_saturation_set ( const uint8_t sat );
enum optic_errorcode optic_ll_dcdc_apd_saturation_get ( uint8_t *sat );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
enum optic_errorcode optic_ll_dcdc_apd_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, DCDC CORE Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_STATUS_DCDC_CORE_INTERNAL DC/DC CORE Converter Module - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_calc.h"
#include "drv_optic_ll_dcdc_core.h"
#if defined(LINUX) && defined(__KERNEL__)
#include <falcon/sys1_reg.h>
#include <falcon/sysctrl.h>
#endif
#include "drv_optic_reg_dcdc.h"
/**
Activates/deactivates DCDC CORE.
*/
enum optic_errorcode optic_ll_dcdc_core_set ( const enum optic_activation mode )
{
uint32_t reg;
if (mode == OPTIC_ENABLE) {
reg = DCDC_CONF_TEST_ANA_SOFT_RES_ADC_N |
DCDC_CONF_TEST_ANA_SOFT_RES_MDLL_N |
DCDC_CONF_TEST_ANA_SOFT_RES_DPWM_N;
dcdc_core_w8( reg, pdi_conf_test_ana);
reg = DCDC_CONF_TEST_DIG_SOFT_RES_PID_N |
DCDC_CONF_TEST_DIG_SOFT_RES_RAMPUP_N;
dcdc_core_w8( reg, pdi_conf_test_dig);
} else {
reg = DCDC_CONF_TEST_ANA_PD_ADC |
DCDC_CONF_TEST_ANA_RESERVED0 |
DCDC_CONF_TEST_ANA_PD_PFMCOMP |
DCDC_CONF_TEST_ANA_DPWM_BYP;
dcdc_core_w8( reg, pdi_conf_test_ana );
dcdc_core_w8( 0x00, pdi_conf_test_dig );
}
return OPTIC_STATUS_OK;
}
/**
Reads back DCDC CORE mode (enable/disable).
*/
enum optic_errorcode optic_ll_dcdc_core_get ( enum optic_activation *mode )
{
uint32_t reg_ana, reg_dig;
uint32_t reg_ana_enable, reg_dig_enable;
reg_ana_enable = (DCDC_CONF_TEST_ANA_SOFT_RES_ADC_N |
DCDC_CONF_TEST_ANA_SOFT_RES_MDLL_N |
DCDC_CONF_TEST_ANA_SOFT_RES_DPWM_N);
reg_dig_enable = (DCDC_CONF_TEST_DIG_SOFT_RES_PID_N |
DCDC_CONF_TEST_DIG_SOFT_RES_RAMPUP_N);
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg_ana = dcdc_core_r8( pdi_conf_test_ana );
reg_dig = dcdc_core_r8( pdi_conf_test_dig );
if ((reg_ana & reg_ana_enable) != reg_ana_enable) {
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
if ((reg_dig & reg_dig_enable) != reg_dig_enable) {
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
*mode = OPTIC_ENABLE;
return OPTIC_STATUS_OK;
}
/**
Set the CORE Voltage.
This function controls the DC/DC CORE converter.
*/
enum optic_errorcode optic_ll_dcdc_core_voltage_set ( const int8_t
offset_dcdc_core,
const uint8_t
gain_dcdc_core,
const uint16_t vcore )
{
uint32_t reg;
uint32_t temp;
/**
VCORE * 512 - 3 fuse_gain * 0.2
VREF = ----------------- * ( 0.9 + --------------- ) + fuse_offset
4 64
VCORE * 512 - 3 288 + fuse_gain
VREF = ----------------- * ----------------- + fuse_offset
4 320
VCORE [<<OPTIC_FLOAT2INTSHIFT_VOLTAGE]
288 + fuse_gain
VREF = ((VCORE << 9) - 3) * ------------------------------------------ + fuse_offset
320 << (OPTIC_FLOAT2INTSHIFT_VOLTAGE + 2)
*/
temp = (vcore << 9) - 3;
temp *= (288 + gain_dcdc_core);
temp = optic_uint_div_rounded ( temp,
320 << (OPTIC_FLOAT2INTSHIFT_VOLTAGE + 2) );
reg = temp + offset_dcdc_core;
/* set reference value */
dcdc_core_w8 ( reg, pdi_dig_ref );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_core_voltage_get ( const int8_t
offset_dcdc_core,
const uint8_t
gain_dcdc_core,
uint16_t *vcore )
{
uint32_t reg;
uint32_t temp;
uint8_t shift = OPTIC_FLOAT2INTSHIFT_VOLTAGE - 9;
if (vcore == NULL)
return OPTIC_STATUS_ERR;
/**
VCORE * 512 - 3 fuse_gain * 0.2
VREF = ------------------ * ( 0.9 + --------------- ) + fuse_offset
4 64
VCORE * 512 - 3 288 + fuse_gain
VREF = ----------------- * ----------------- + fuse_offset
4 320
VCORE * 512 - 3 ( VREF - fuse_offset ) * 320
------------------ = -----------------------------
4 288 + fuse_gain
( VREF - fuse_offset ) * 1280
------------------------------- + 3
288 + fuse_gain
VCORE = ---------------------------------------
512
VCORE [<<OPTIC_FLOAT2INTSHIFT_VOLTAGE]
( VREF - fuse_offset ) * 1280
VCORE = ( ------------------------------- + 3 ) << (OPTIC_FLOAT2INTSHIFT_VOLTAGE - 9)
288 + fuse_gain
shift = OPTIC_FLOAT2INTSHIFT_VOLTAGE - 9
( VREF - fuse_offset ) * (1280 << shift)
VCORE = ---------------------------------------- + (3 << shift)
288 + fuse_gain
*/
reg = dcdc_core_r8 ( pdi_dig_ref );
temp = (reg - offset_dcdc_core) * (1280 << shift);
temp = optic_uint_div_rounded ( temp, 288 + gain_dcdc_core );
temp += (3 << shift);
*vcore = (uint16_t) temp;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_core_dutycycle_set ( const uint8_t min,
const uint8_t max )
{
uint32_t reg;
/* set duty cycle min/max */
reg = min;
dcdc_core_w8 ( reg, pdi_duty_cycle_min );
reg = max;
dcdc_core_w8 ( reg, pdi_duty_cycle_max );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_core_deadzone_set ( const uint8_t del_p,
const uint8_t del_n )
{
uint32_t reg;
reg = ((del_n << DCDC_NON_OV_DELAY_DEL_N_OFFSET)
& DCDC_NON_OV_DELAY_DEL_N_MASK) |
((del_p << DCDC_NON_OV_DELAY_DEL_P_OFFSET)
& DCDC_NON_OV_DELAY_DEL_P_MASK);
dcdc_core_w8 ( reg, pdi_non_ov_delay );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_core_dutycycle_get ( uint8_t *min,
uint8_t *max )
{
uint32_t reg;
if ((min == NULL) || (max == NULL))
return OPTIC_STATUS_ERR;
/* get duty cycle min/max */
reg = dcdc_core_r8 ( pdi_duty_cycle_min );
*min = reg & 0xFF;
reg = dcdc_core_r8 ( pdi_duty_cycle_max );
*max = reg & 0xFF;
return OPTIC_STATUS_OK;
}
static void wait_and_print_dcdc_err(uint32_t m_sec, const char *txt)
{
OPTIC_DEBUG_MSG("%s: error_read %d",
txt,
(int8_t)dcdc_core_r8(pdi_error_read));
if (m_sec) {
/* wait X ms for stabilisation */
optic_udelay(m_sec*1000);
OPTIC_DEBUG_MSG("after %d ms: error_read %d",
m_sec,
(int8_t)dcdc_core_r8(pdi_error_read));
}
}
enum optic_errorcode optic_ll_dcdc_core_restore_hw_values (void)
{
uint32_t duty_cycle_av, i;
uint8_t duty_cycle_curr, duty_cycle_min, duty_cycle_max;
const uint32_t DUTY_CYCLE_TIMES = 500;
int8_t error_read;
/* set voltage to HW reset value */
dcdc_core_w8(DCDC_DIG_REF_V_NOMINAL, pdi_dig_ref);
wait_and_print_dcdc_err(1, "switch voltage");
dcdc_core_w8(0xFF, pdi_pwm0);
wait_and_print_dcdc_err(1, "switch freq");
duty_cycle_av = 0;
duty_cycle_min = 0xFF;
duty_cycle_max = 0;
for (i=0; i<DUTY_CYCLE_TIMES; i++) {
duty_cycle_curr = dcdc_core_r8(pdi_duty_cycle);
duty_cycle_av += duty_cycle_curr;
if (duty_cycle_curr < duty_cycle_min)
duty_cycle_min = duty_cycle_curr;
if (duty_cycle_curr > duty_cycle_max)
duty_cycle_max = duty_cycle_curr;
optic_udelay(10);
}
duty_cycle_av = duty_cycle_av / DUTY_CYCLE_TIMES;
OPTIC_DEBUG_MSG("duty_cycle: average = %d, min = %d, max = %d",
duty_cycle_av, duty_cycle_min, duty_cycle_max);
/* restrict duty cycle range around average */
dcdc_core_w8(duty_cycle_av+10, pdi_duty_cycle_max_sat);
dcdc_core_w8(duty_cycle_av-10, pdi_duty_cycle_min_sat);
/* force static duty cycle value during coefficient programming */
dcdc_core_w8(duty_cycle_av, pdi_pwm1);
dcdc_core_w8_mask(0, DCDC_CONF_TEST_DIG_SOFT_PRESET_PID |
DCDC_CONF_TEST_DIG_FREEZE_PID,
pdi_conf_test_dig);
/* write HW default coefficients */
dcdc_core_w8(DCDC_PID_HI_B0_B_KP_3, pdi_pid_hi_b0);
dcdc_core_w8(DCDC_PID_LO_B0_B_KP_3, pdi_pid_lo_b0);
dcdc_core_w8(DCDC_PID_HI_B1_B_KP_3, pdi_pid_hi_b1);
dcdc_core_w8(DCDC_PID_LO_B1_B_KP_3, pdi_pid_lo_b1);
dcdc_core_w8(DCDC_PID_HI_B2_B_KP_3, pdi_pid_hi_b2);
dcdc_core_w8(DCDC_PID_LO_B2_B_KP_3, pdi_pid_lo_b2);
error_read = (int8_t)dcdc_core_r8(pdi_error_read);
/* unfreeze PID */
dcdc_core_w8_mask(DCDC_CONF_TEST_DIG_SOFT_PRESET_PID |
DCDC_CONF_TEST_DIG_FREEZE_PID,
0, pdi_conf_test_dig);
OPTIC_DEBUG_MSG("before unfreeze: error_read %d", error_read);
wait_and_print_dcdc_err(1, "unfreeze");
return OPTIC_STATUS_OK;
}
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
enum optic_errorcode optic_ll_dcdc_core_dump ( void )
{
OPTIC_DEBUG_WRN("DCDC CORE #0: 0x%02X",
dcdc_core_r8(pdi_pid_hi_b0));
OPTIC_DEBUG_WRN("DCDC CORE #1: 0x%02X",
dcdc_core_r8(pdi_pid_lo_b0));
OPTIC_DEBUG_WRN("DCDC CORE #2: 0x%02X",
dcdc_core_r8(pdi_pid_hi_b1));
OPTIC_DEBUG_WRN("DCDC CORE #3: 0x%02X",
dcdc_core_r8(pdi_pid_lo_b1));
OPTIC_DEBUG_WRN("DCDC CORE #4: 0x%02X",
dcdc_core_r8(pdi_pid_hi_b2));
OPTIC_DEBUG_WRN("DCDC CORE #5: 0x%02X",
dcdc_core_r8(pdi_pid_lo_b2));
OPTIC_DEBUG_WRN("DCDC CORE #6: 0x%02X",
dcdc_core_r8(pdi_clk_set0));
OPTIC_DEBUG_WRN("DCDC CORE #7: 0x%02X",
dcdc_core_r8(pdi_clk_set1));
OPTIC_DEBUG_WRN("DCDC CORE #8: 0x%02X",
dcdc_core_r8(pdi_pwm0));
OPTIC_DEBUG_WRN("DCDC CORE #9: 0x%02X",
dcdc_core_r8(pdi_pwm1));
OPTIC_DEBUG_WRN("DCDC CORE #10: 0x%02X",
dcdc_core_r8(pdi_bias_vreg));
OPTIC_DEBUG_WRN("DCDC CORE #11: 0x%02X",
dcdc_core_r8(pdi_dig_ref));
OPTIC_DEBUG_WRN("DCDC CORE #12: 0x%02X",
dcdc_core_r8(pdi_general));
OPTIC_DEBUG_WRN("DCDC CORE #13: 0x%02X",
dcdc_core_r8(pdi_adc0));
OPTIC_DEBUG_WRN("DCDC CORE #14: 0x%02X",
dcdc_core_r8(pdi_adc1));
OPTIC_DEBUG_WRN("DCDC CORE #15: 0x%02X",
dcdc_core_r8(pdi_adc2));
OPTIC_DEBUG_WRN("DCDC CORE #16: 0x%02X",
dcdc_core_r8(pdi_conf_test_ana));
OPTIC_DEBUG_WRN("DCDC CORE #17: 0x%02X",
dcdc_core_r8(pdi_conf_test_dig));
OPTIC_DEBUG_WRN("DCDC CORE #18: 0x%02X",
dcdc_core_r8(pdi_conf_test_ana_noauto));
OPTIC_DEBUG_WRN("DCDC CORE #19: 0x%02X",
dcdc_core_r8(pdi_conf_test_dig_noauto));
OPTIC_DEBUG_WRN("DCDC CORE #20: 0x%02X",
dcdc_core_r8(pdi_dcdc_status));
OPTIC_DEBUG_WRN("DCDC CORE #21: 0x%02X",
dcdc_core_r8(pdi_pid_status));
OPTIC_DEBUG_WRN("DCDC CORE #22: 0x%02X",
dcdc_core_r8(pdi_duty_cycle));
OPTIC_DEBUG_WRN("DCDC CORE #23: 0x%02X",
dcdc_core_r8(pdi_non_ov_delay));
OPTIC_DEBUG_WRN("DCDC CORE #24: 0x%02X",
dcdc_core_r8(pdi_analog_gain));
OPTIC_DEBUG_WRN("DCDC CORE #25: 0x%02X",
dcdc_core_r8(pdi_duty_cycle_max_sat));
OPTIC_DEBUG_WRN("DCDC CORE #26: 0x%02X",
dcdc_core_r8(pdi_duty_cycle_min_sat));
OPTIC_DEBUG_WRN("DCDC CORE #27: 0x%02X",
dcdc_core_r8(pdi_duty_cycle_max));
OPTIC_DEBUG_WRN("DCDC CORE #28: 0x%02X",
dcdc_core_r8(pdi_duty_cycle_min));
OPTIC_DEBUG_WRN("DCDC CORE #29: 0x%02X",
dcdc_core_r8(pdi_error_max));
OPTIC_DEBUG_WRN("DCDC CORE #30: 0x%02X",
dcdc_core_r8(pdi_error_read));
OPTIC_DEBUG_WRN("DCDC CORE #31: 0x%02X",
dcdc_core_r8(pdi_delay_deglitch));
OPTIC_DEBUG_WRN("DCDC CORE #32: 0x%02X",
dcdc_core_r8(pdi_latch_control));
OPTIC_DEBUG_WRN("DCDC CORE #33: 0x%02X",
dcdc_core_r8(pdi_latch_control_noauto));
OPTIC_DEBUG_WRN("DCDC CORE #34: 0x%02X",
dcdc_core_r8(pdi_cap_clk_cnt));
OPTIC_DEBUG_WRN("DCDC CORE #35: 0x%02X",
dcdc_core_r8(pdi_mdll_divider));
return OPTIC_STATUS_OK;
}
#endif
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_dcdc_core.h
*/
#ifndef _drv_optic_ll_dcdc_core_h
#define _drv_optic_ll_dcdc_core_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_DCDC_CORE_INTERNAL DC/DC CORE Converter Module - Internal
@{
*/
enum optic_errorcode optic_ll_dcdc_core_set ( const enum optic_activation
mode );
enum optic_errorcode optic_ll_dcdc_core_get ( enum optic_activation *mode );
enum optic_errorcode optic_ll_dcdc_core_voltage_set ( const int8_t
offset_dcdc_core,
const uint8_t
gain_dcdc_core,
const uint16_t vcore );
enum optic_errorcode optic_ll_dcdc_core_voltage_get ( const int8_t
offset_dcdc_core,
const uint8_t
gain_dcdc_core,
uint16_t *vcore );
enum optic_errorcode optic_ll_dcdc_core_dutycycle_set ( const uint8_t min,
const uint8_t max );
enum optic_errorcode optic_ll_dcdc_core_dutycycle_get ( uint8_t *min,
uint8_t *max );
enum optic_errorcode optic_ll_dcdc_core_deadzone_set ( const uint8_t del_p,
const uint8_t del_n );
enum optic_errorcode optic_ll_dcdc_core_restore_hw_values (void);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
enum optic_errorcode optic_ll_dcdc_core_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, DCDC DDR Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_STATUS_DCDC_DDR_INTERNAL DC/DC DDR Converter Module - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_calc.h"
#include "drv_optic_ll_dcdc_ddr.h"
#if defined(LINUX) && defined(__KERNEL__)
#include <falcon/sys1_reg.h>
#include <falcon/sysctrl.h>
#endif
#include "drv_optic_reg_dcdc.h"
/**
Activates/deactivates DCDC DDR.
*/
enum optic_errorcode optic_ll_dcdc_ddr_set ( const enum optic_activation mode )
{
uint32_t reg;
if (mode == OPTIC_ENABLE) {
reg = DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_ADC_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_MDLL_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_DPWM_N;
dcdc_ddr_w8( reg, pdi_conf_test_ana_noauto);
reg = DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_PID_N |
DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_RAMPUP_N;
dcdc_ddr_w8( reg, pdi_conf_test_dig_noauto);
} else {
reg = DCDC_CONF_TEST_ANA_NOAUTO_PD_ADC |
DCDC_CONF_TEST_ANA_NOAUTO_RESERVED0 |
DCDC_CONF_TEST_ANA_NOAUTO_PD_PFMCOMP |
DCDC_CONF_TEST_ANA_NOAUTO_DPWM_BYP;
dcdc_ddr_w8( reg, pdi_conf_test_ana_noauto);
dcdc_ddr_w8( 0x00, pdi_conf_test_dig_noauto);
}
return OPTIC_STATUS_OK;
}
/**
Reads back DCDC DDR mode (enable/disable).
*/
enum optic_errorcode optic_ll_dcdc_ddr_get ( enum optic_activation *mode )
{
uint32_t reg_ana, reg_dig;
uint32_t reg_ana_enable, reg_dig_enable;
reg_ana_enable = (DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_ADC_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_MDLL_N |
DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_DPWM_N);
reg_dig_enable = (DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_PID_N |
DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_RAMPUP_N);
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg_ana = dcdc_ddr_r8( pdi_conf_test_ana_noauto);
reg_dig = dcdc_ddr_r8( pdi_conf_test_dig_noauto);
if ((reg_ana & reg_ana_enable) != reg_ana_enable) {
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
if ((reg_dig & reg_dig_enable) != reg_dig_enable) {
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
*mode = OPTIC_ENABLE;
return OPTIC_STATUS_OK;
}
/**
Set the DDR Voltage.
This function controls the DC/DC DDR converter.
*/
enum optic_errorcode optic_ll_dcdc_ddr_voltage_set ( const int8_t
offset_dcdc_ddr,
const uint8_t
gain_dcdc_ddr,
const uint16_t vddr )
{
uint32_t reg;
uint32_t temp;
/**
(VDDR/2 + 0,5) * 512 - 3 fuse_gain * 0.2
VREF = ------------------------- * ( 0.9 + --------------- ) + fuse_offset
4 64
VDDR * 256 + 253 288 + fuse_gain
VREF = ----------------- * ----------------- + fuse_offset
4 320
VDDR [<<OPTIC_FLOAT2INTSHIFT_VOLTAGE]
288 + fuse_gain
VREF = ((VDDR << 8) + 253) * ------------------------------------------ + fuse_offset
320 << (OPTIC_FLOAT2INTSHIFT_VOLTAGE + 2)
*/
temp = (vddr << 8) + 253;
temp *= (288 + gain_dcdc_ddr);
temp = optic_uint_div_rounded ( temp,
320 << (OPTIC_FLOAT2INTSHIFT_VOLTAGE + 2) );
reg = temp + offset_dcdc_ddr;
/* set reference value */
dcdc_ddr_w8 ( reg, pdi_dig_ref );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_ddr_voltage_get ( const int8_t
offset_dcdc_ddr,
const uint8_t
gain_dcdc_ddr,
uint16_t *vddr )
{
uint32_t reg;
uint32_t temp;
uint8_t shift = OPTIC_FLOAT2INTSHIFT_VOLTAGE - 8;
if (vddr == NULL)
return OPTIC_STATUS_ERR;
/**
(VDDR/2 + 0,5) * 512 - 3 fuse_gain * 0.2
VREF = ------------------------- * ( 0.9 + --------------- ) + fuse_offset
4 64
VDDR * 256 + 253 288 + fuse_gain
VREF = ----------------- * ----------------- + fuse_offset
4 320
VDDR * 256 + 253 ( VREF - fuse_offset ) * 320
------------------ = -----------------------------
4 288 + fuse_gain
( VREF - fuse_offset ) * 1280
------------------------------- - 253
288 + fuse_gain
VDDR = ---------------------------------------
256
VDDR [<<OPTIC_FLOAT2INTSHIFT_VOLTAGE]
( VREF - fuse_offset ) * 1280
VDDR = ( ------------------------------- - 253 ) << (OPTIC_FLOAT2INTSHIFT_VOLTAGE - 8)
288 + fuse_gain
shift = OPTIC_FLOAT2INTSHIFT_VOLTAGE - 8
( VREF - fuse_offset ) * (1280 << shift)
VDDR = ---------------------------------------- - (253 << shift)
288 + fuse_gain
*/
reg = dcdc_ddr_r8 ( pdi_dig_ref );
temp = (reg - offset_dcdc_ddr) * (1280 << shift);
temp = optic_uint_div_rounded ( temp, 288 + gain_dcdc_ddr );
temp -= (253 << shift);
*vddr = (uint16_t) temp;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_ddr_dutycycle_set ( const uint8_t min,
const uint8_t max )
{
uint32_t reg;
/* set duty cycle min/max */
reg = min;
dcdc_ddr_w8 ( reg, pdi_duty_cycle_min );
reg = max;
dcdc_ddr_w8 ( reg, pdi_duty_cycle_max );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_ddr_deadzone_set ( const uint8_t del_p,
const uint8_t del_n )
{
uint32_t reg;
reg = ((del_n << DCDC_NON_OV_DELAY_DEL_N_OFFSET)
& DCDC_NON_OV_DELAY_DEL_N_MASK) |
((del_p << DCDC_NON_OV_DELAY_DEL_P_OFFSET)
& DCDC_NON_OV_DELAY_DEL_P_MASK);
dcdc_ddr_w8 ( reg, pdi_non_ov_delay );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_dcdc_ddr_dutycycle_get ( uint8_t *min,
uint8_t *max )
{
uint32_t reg;
if ((min == NULL) || (max == NULL))
return OPTIC_STATUS_ERR;
/* get duty cycle min/max */
reg = dcdc_ddr_r8 ( pdi_duty_cycle_min );
*min = reg & 0xFF;
reg = dcdc_ddr_r8 ( pdi_duty_cycle_max );
*max = reg & 0xFF;
return OPTIC_STATUS_OK;
}
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
enum optic_errorcode optic_ll_dcdc_ddr_dump ( void )
{
OPTIC_DEBUG_WRN("DCDC DDR #0: 0x%02X",
dcdc_ddr_r8(pdi_pid_hi_b0));
OPTIC_DEBUG_WRN("DCDC DDR #1: 0x%02X",
dcdc_ddr_r8(pdi_pid_lo_b0));
OPTIC_DEBUG_WRN("DCDC DDR #2: 0x%02X",
dcdc_ddr_r8(pdi_pid_hi_b1));
OPTIC_DEBUG_WRN("DCDC DDR #3: 0x%02X",
dcdc_ddr_r8(pdi_pid_lo_b1));
OPTIC_DEBUG_WRN("DCDC DDR #4: 0x%02X",
dcdc_ddr_r8(pdi_pid_hi_b2));
OPTIC_DEBUG_WRN("DCDC DDR #5: 0x%02X",
dcdc_ddr_r8(pdi_pid_lo_b2));
OPTIC_DEBUG_WRN("DCDC DDR #6: 0x%02X",
dcdc_ddr_r8(pdi_clk_set0));
OPTIC_DEBUG_WRN("DCDC DDR #7: 0x%02X",
dcdc_ddr_r8(pdi_clk_set1));
OPTIC_DEBUG_WRN("DCDC DDR #8: 0x%02X",
dcdc_ddr_r8(pdi_pwm0));
OPTIC_DEBUG_WRN("DCDC DDR #9: 0x%02X",
dcdc_ddr_r8(pdi_pwm1));
OPTIC_DEBUG_WRN("DCDC DDR #10: 0x%02X",
dcdc_ddr_r8(pdi_bias_vreg));
OPTIC_DEBUG_WRN("DCDC DDR #11: 0x%02X",
dcdc_ddr_r8(pdi_dig_ref));
OPTIC_DEBUG_WRN("DCDC DDR #12: 0x%02X",
dcdc_ddr_r8(pdi_general));
OPTIC_DEBUG_WRN("DCDC DDR #13: 0x%02X",
dcdc_ddr_r8(pdi_adc0));
OPTIC_DEBUG_WRN("DCDC DDR #14: 0x%02X",
dcdc_ddr_r8(pdi_adc1));
OPTIC_DEBUG_WRN("DCDC DDR #15: 0x%02X",
dcdc_ddr_r8(pdi_adc2));
OPTIC_DEBUG_WRN("DCDC DDR #16: 0x%02X",
dcdc_ddr_r8(pdi_conf_test_ana));
OPTIC_DEBUG_WRN("DCDC DDR #17: 0x%02X",
dcdc_ddr_r8(pdi_conf_test_dig));
OPTIC_DEBUG_WRN("DCDC DDR #18: 0x%02X",
dcdc_ddr_r8(pdi_conf_test_ana_noauto));
OPTIC_DEBUG_WRN("DCDC DDR #19: 0x%02X",
dcdc_ddr_r8(pdi_conf_test_dig_noauto));
OPTIC_DEBUG_WRN("DCDC DDR #20: 0x%02X",
dcdc_ddr_r8(pdi_dcdc_status));
OPTIC_DEBUG_WRN("DCDC DDR #21: 0x%02X",
dcdc_ddr_r8(pdi_pid_status));
OPTIC_DEBUG_WRN("DCDC DDR #22: 0x%02X",
dcdc_ddr_r8(pdi_duty_cycle));
OPTIC_DEBUG_WRN("DCDC DDR #23: 0x%02X",
dcdc_ddr_r8(pdi_non_ov_delay));
OPTIC_DEBUG_WRN("DCDC DDR #24: 0x%02X",
dcdc_ddr_r8(pdi_analog_gain));
OPTIC_DEBUG_WRN("DCDC DDR #25: 0x%02X",
dcdc_ddr_r8(pdi_duty_cycle_max_sat));
OPTIC_DEBUG_WRN("DCDC DDR #26: 0x%02X",
dcdc_ddr_r8(pdi_duty_cycle_min_sat));
OPTIC_DEBUG_WRN("DCDC DDR #27: 0x%02X",
dcdc_ddr_r8(pdi_duty_cycle_max));
OPTIC_DEBUG_WRN("DCDC DDR #28: 0x%02X",
dcdc_ddr_r8(pdi_duty_cycle_min));
OPTIC_DEBUG_WRN("DCDC DDR #29: 0x%02X",
dcdc_ddr_r8(pdi_error_max));
OPTIC_DEBUG_WRN("DCDC DDR #30: 0x%02X",
dcdc_ddr_r8(pdi_error_read));
OPTIC_DEBUG_WRN("DCDC DDR #31: 0x%02X",
dcdc_ddr_r8(pdi_delay_deglitch));
OPTIC_DEBUG_WRN("DCDC DDR #32: 0x%02X",
dcdc_ddr_r8(pdi_latch_control));
OPTIC_DEBUG_WRN("DCDC DDR #33: 0x%02X",
dcdc_ddr_r8(pdi_latch_control_noauto));
OPTIC_DEBUG_WRN("DCDC DDR #34: 0x%02X",
dcdc_ddr_r8(pdi_cap_clk_cnt));
OPTIC_DEBUG_WRN("DCDC DDR #35: 0x%02X",
dcdc_ddr_r8(pdi_mdll_divider));
return OPTIC_STATUS_OK;
}
#endif
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_dcdc_ddr.h
*/
#ifndef _drv_optic_ll_dcdc_ddr_h
#define _drv_optic_ll_dcdc_ddr_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_DCDC_DDR_INTERNAL DC/DC DDR Converter Module - Internal
@{
*/
enum optic_errorcode optic_ll_dcdc_ddr_set ( const enum optic_activation
mode );
enum optic_errorcode optic_ll_dcdc_ddr_get ( enum optic_activation *mode );
enum optic_errorcode optic_ll_dcdc_ddr_voltage_set ( const int8_t
offset_dcdc_ddr,
const uint8_t
gain_dcdc_ddr,
const uint16_t vddr );
enum optic_errorcode optic_ll_dcdc_ddr_voltage_get ( const int8_t
offset_dcdc_ddr,
const uint8_t
gain_dcdc_ddr,
uint16_t *vddr );
enum optic_errorcode optic_ll_dcdc_ddr_dutycycle_set ( const uint8_t min,
const uint8_t max );
enum optic_errorcode optic_ll_dcdc_ddr_dutycycle_get ( uint8_t *min,
uint8_t *max );
enum optic_errorcode optic_ll_dcdc_ddr_deadzone_set ( const uint8_t del_p,
const uint8_t del_n );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_DCDC == ACTIVE))
enum optic_errorcode optic_ll_dcdc_ddr_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_fcsi.h
*/
#ifndef _drv_optic_ll_fcsi_h
#define _drv_optic_ll_fcsi_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
#include "drv_optic_reg_fcsi_base.h"
#include "drv_optic_reg_fcsi_txbosa.h"
#include "drv_optic_reg_fcsi_txomu.h"
#include "drv_optic_reg_fcsi_rxbosa.h"
#include "drv_optic_reg_fcsi_rxomu.h"
#include "drv_optic_reg_fcsi_mm.h"
#include "drv_optic_reg_fcsi_vdac.h"
#include "drv_optic_reg_fcsi_bfd.h"
#include "drv_optic_reg_fcsi_vdac.h"
#include "drv_optic_reg_fcsi_cbias.h"
#include "drv_optic_reg_fcsi_vdll.h"
struct fcsi_addr_val {
vuint16_t *addr;
uint32_t val;
};
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_FCSI_INTERNAL FCSI Register Interface - Internal
@{
*/
#define OPTIC_FCSI_BASE FCSI_TXBOSA_BASE
#define OPTIC_FCSI_END FCSI_VDLL_END
#define OPTIC_FCSI_SIZE (FCSI_TXBOSA_BASE - FCSI_VDLL_END)
/* Power level dependent DDC0, DDC1, BDC0, BDC1 settings */
/* "0x1F" # [-] FCSI DDC0.RTN setting for reference transmit power */
#define DD_LOADN_0 0x1F
#define DD_LOADN_0_A21 0x1F
/* "0x7" # [-] FCSI DDC0.FT setting for reference transmit power */
#define DD_BIAS_EN_0 0x7
#define DD_BIAS_EN_0_A21 0xF
/* "0x1F" # [-] FCSI DDC1.RTP setting for reference transmit power */
#define DD_LOADP_0 0x1F
#define DD_LOADP_0_A21 0x1F
/* "0x7" # [-] FCSI DDC1.CMR setting for reference transmit power */
#define DD_CM_LOAD_0 0x6
#define DD_CM_LOAD_0_A21 0x8
/* "0x1F" # [-] FCSI BDC0.RTN setting for reference transmit power */
#define BD_LOADN_0 0x1F
#define BD_LOADN_0_A21 0x05
/* "0xF" # [-] FCSI BDC0.FT setting for reference transmit power */
#define BD_BIAS_EN_0 0xF
#define BD_BIAS_EN_0_A21 0x3
/* "0x1F" # [-] FCSI BDC1.RTP setting for reference transmit power */
#define BD_LOADP_0 0x1F
#define BD_LOADP_0_A21 0x3
/* "0x3" # [-] FCSI BDC1.CMR setting for reference transmit power */
#define BD_CM_LOAD_0 0x3
#define BD_CM_LOAD_0_A21 0x6
/* "0x1F" # [-] FCSI DDC0.RTN setting for reference -3 dB transmit power */
#define DD_LOADN_1 0x1F
#define DD_LOADN_1_A21 0x1F
/* "0x7" # [-] FCSI DDC0.FT setting for reference -3 dB transmit power */
#define DD_BIAS_EN_1 0x7
#define DD_BIAS_EN_1_A21 0xF
/* "0x1F" # [-] FCSI DDC1.RTP setting for reference -3 dB transmit power */
#define DD_LOADP_1 0x1F
#define DD_LOADP_1_A21 0x1F
/* "0x7" # [-] FCSI DDC1.CMR setting for reference -3 dB transmit power */
#define DD_CM_LOAD_1 0x6
#define DD_CM_LOAD_1_A21 0x8
/* "0x1F" # [-] FCSI BDC0.RTN setting for reference -3 dB transmit power */
#define BD_LOADN_1 0x1F
#define BD_LOADN_1_A21 0x05
/* "0xF" # [-] FCSI BDC0.FT setting for reference -3 dB transmit power */
#define BD_BIAS_EN_1 0xF
#define BD_BIAS_EN_1_A21 0x3
/* "0x1F" # [-] FCSI BDC1.RTP setting for reference -3 dB transmit power */
#define BD_LOADP_1 0x1F
#define BD_LOADP_1_A21 0x3
/* "0x3" # [-] FCSI BDC1.CMR setting for reference -3 dB transmit power */
#define BD_CM_LOAD_1 0x3
#define BD_CM_LOAD_1_A21 0x6
/* "0x1F" # [-] FCSI DDC0.RTN setting for reference -6 dB transmit power */
#define DD_LOADN_2 0x1F
#define DD_LOADN_2_A21 0x1F
/* "0x7" # [-] FCSI DDC0.FT setting for reference -6 dB transmit power */
#define DD_BIAS_EN_2 0x7
#define DD_BIAS_EN_2_A21 0xF
/* "0x1F" # [-] FCSI DDC1.RTP setting for reference -6 dB transmit power */
#define DD_LOADP_2 0x1F
#define DD_LOADP_2_A21 0x1F
/* "0x7" # [-] FCSI DDC1.CMR setting for reference -6 dB transmit power */
#define DD_CM_LOAD_2 0x6
#define DD_CM_LOAD_2_A21 0x8
/* "0x1F" # [-] FCSI BDC0.RTN setting for reference -6 dB transmit power */
#define BD_LOADN_2 0x1F
#define BD_LOADN_2_A21 0x05
/* "0xF" # [-] FCSI BDC0.FT setting for reference -6 dB transmit power */
#define BD_BIAS_EN_2 0xF
#define BD_BIAS_EN_2_A21 0x3
/* "0x1F" # [-] FCSI BDC1.RTP setting for reference -6 dB transmit power */
#define BD_LOADP_2 0x1F
#define BD_LOADP_2_A21 0x3
/* "0x3" # [-] FCSI BDC1.CMR setting for reference -6 dB transmit power */
#define BD_CM_LOAD_2 0x3
#define BD_CM_LOAD_2_A21 0x6
struct optic_reg_fcsi {
struct fcsi_reg_txbosa txbosa; /* 0 .. 7 */
struct fcsi_reg_txomu txomu; /* 8 .. 10 */
struct fcsi_reg_rxbosa rxbosa; /* 11 */
uint16_t reg_12;
struct fcsi_reg_rxomu rxomu; /* 13 */
struct fcsi_reg_mm mm; /* 14 */
struct fcsi_reg_vdac vdac; /* 15 */
struct fcsi_reg_bfd bfd; /* 16 .. 18 */
uint16_t reg_19;
struct fcsi_reg_cbias cbias; /* 20, 21 */
uint16_t reg_22;
uint16_t reg_23;
struct fcsi_reg_vdll vdll; /* 24 */
};
/*
#define txbosa &(fcsi->txbosa)
#define rxbosa &(fcsi->rxbosa)
#define txomu &(fcsi->rxomu)
#define rxomu &(fcsi->rxomu)
#define bfd &(fcsi->bfd)
#define mm &(fcsi->mm)
*/
/* These are the FCSI register default values, used by OPTIC_IO_FCSI_Init */
/* !!! changing this setting can cause hardware damage !!! */
/** reg #0:
fcsi_w(TXBOSA_Base + TXBOSA_DDC0 , 0x1B << TXBOSA_DDC0_RTN |
0x0 << TXBOSA_DDC0_BLCD |
0x8 << TXBOSA_DDC0_FT ); */
/*
#define OPTIC_FCSI_TXBOSA_DDC0_RESET 0x801B
*/
#define OPTIC_FCSI_TXBOSA_DDC0_RESET 0x8010
#define OPTIC_FCSI_TXBOSA_DDC0_RESET_BOSA 0x701F
#define OPTIC_FCSI_TXBOSA_DDC0_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_DDC0_RESET_A21 0xF0BF
#define OPTIC_FCSI_TXBOSA_DDC0_RESET_BOSA_A21 0xF0BF
#define OPTIC_FCSI_TXBOSA_DDC0_RESET_OMU_A21 0x0000
/** reg #1:
fcsi_w(TXBOSA_Base + TXBOSA_DDC1 , 0x1B << TXBOSA_DDC1_RTP |
0x7 << TXBOSA_DDC1_CMR |
0x0 << TXBOSA_DDC1_ENPD ); */
/*
#define OPTIC_FCSI_TXBOSA_DDC1_RESET_1 0x1C1B
*/
#define OPTIC_FCSI_TXBOSA_DDC1_RESET 0x4010
#define OPTIC_FCSI_TXBOSA_DDC1_RESET_BOSA 0x181F
#define OPTIC_FCSI_TXBOSA_DDC1_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_DDC1_RESET_A21 0x207F
#define OPTIC_FCSI_TXBOSA_DDC1_RESET_BOSA_A21 0x207F
#define OPTIC_FCSI_TXBOSA_DDC1_RESET_OMU_A21 0x0000
/** reg #2:
fcsi_w(TXBOSA_Base + TXBOSA_BDC0 , 0x10 << TXBOSA_BDC0_RTN |
0x0 << TXBOSA_BDC0_BLCD |
0x8 << TXBOSA_BDC0_FT ); */
/*
#define OPTIC_FCSI_TXBOSA_BDC0_RESET 0x8010
*/
#define OPTIC_FCSI_TXBOSA_BDC0_RESET 0x8008
#define OPTIC_FCSI_TXBOSA_BDC0_RESET_BOSA 0xF01F
#define OPTIC_FCSI_TXBOSA_BDC0_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_BDC0_RESET_A21 0x3005
#define OPTIC_FCSI_TXBOSA_BDC0_RESET_BOSA_A21 0x3005
#define OPTIC_FCSI_TXBOSA_BDC0_RESET_OMU_A21 0x0000
/** reg #3:
fcsi_w(TXBOSA_Base + TXBOSA_BDC1 , 0x10 << TXBOSA_BDC1_RTP |
0x0 << TXBOSA_BDC1_CMR |
0x0 << TXBOSA_BDC1_ENPD ); */
/*
#define OPTIC_FCSI_TXBOSA_BDC1_RESET_1 0x0010
*/
#define OPTIC_FCSI_TXBOSA_BDC1_RESET 0x0008
#define OPTIC_FCSI_TXBOSA_BDC1_RESET_BOSA 0x0C1F
#define OPTIC_FCSI_TXBOSA_BDC1_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_BDC1_RESET_A21 0x1803
#define OPTIC_FCSI_TXBOSA_BDC1_RESET_BOSA_A21 0x1803
#define OPTIC_FCSI_TXBOSA_BDC1_RESET_OMU_A21 0x0000
/** reg #4:
fcsi_w(TXBOSA_Base + TXBOSA_CTRL , 0x1 << TXBOSA_CTRL_FFR |
0x0 << TXBOSA_CTRL_SE |
0x0 << TXBOSA_CTRL_OP |
0x0 << TXBOSA_CTRL_CE |
0x0 << TXBOSA_CTRL_CED |
0x1 << TXBOSA_CTRL_PDB |
0x1 << TXBOSA_CTRL_PDD |
0x0 << TXBOSA_CTRL_PRE ); */
#define OPTIC_FCSI_TXBOSA_CTRL_RESET 0x0001
#define OPTIC_FCSI_TXBOSA_CTRL_RESET_BOSA 0x0081
#define OPTIC_FCSI_TXBOSA_CTRL_RESET_OMU 0x0060
#define OPTIC_FCSI_TXBOSA_CTRL_RESET_A21 0x0081
#define OPTIC_FCSI_TXBOSA_CTRL_RESET_BOSA_A21 0x0081
#define OPTIC_FCSI_TXBOSA_CTRL_RESET_OMU_A21 0x0060
/** reg #5:
fcsi_w(TXBOSA_Base + TXBOSA_CC , 0x0 << TXBOSA_CC_CINV |
0x1B << TXBOSA_CC_PRTN |
0x1B << TXBOSA_CC_PRTP |
0x6 << TXBOSA_CC_PCM ); */
#define OPTIC_FCSI_TXBOSA_CC_RESET 0x0000
#define OPTIC_FCSI_TXBOSA_CC_RESET_BOSA 0x3000
#define OPTIC_FCSI_TXBOSA_CC_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_CC_RESET_A21 0x4000
#define OPTIC_FCSI_TXBOSA_CC_RESET_BOSA_A21 0x4000
#define OPTIC_FCSI_TXBOSA_CC_RESET_OMU_A21 0x0000
/** reg #6:
fcsi_w(TXBOSA_Base + TXBOSA_PH , 0x0 << TXBOSA_PH_RD |
0x0 << TXBOSA_PH_RST |
0x10 << TXBOSA_PH_PRTNB|
0x10 << TXBOSA_PH_PRTPB|
0x8 << TXBOSA_PH_PBEN); */
#define OPTIC_FCSI_TXBOSA_PH_RESET 0x0000
#define OPTIC_FCSI_TXBOSA_PH_RESET_BOSA 0x1000
#define OPTIC_FCSI_TXBOSA_PH_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_PH_RESET_A21 0x2000
#define OPTIC_FCSI_TXBOSA_PH_RESET_BOSA_A21 0x2000
#define OPTIC_FCSI_TXBOSA_PH_RESET_OMU_A21 0x0000
/** reg #7:
fcsi_w(TXBOSA_Base + TXBOSA_PDS , 0x7 << TXBOSA_PDS_PBENDD |
0x6 << TXBOSA_PDS_PCMD |
0x0 << TXBOSA_PDS_PSPRE ); */
#define OPTIC_FCSI_TXBOSA_PDS_RESET 0x0000
#define OPTIC_FCSI_TXBOSA_PDS_RESET_BOSA 0x0233
#define OPTIC_FCSI_TXBOSA_PDS_RESET_OMU 0x0000
#define OPTIC_FCSI_TXBOSA_PDS_RESET_A21 0x0067
#define OPTIC_FCSI_TXBOSA_PDS_RESET_BOSA_A21 0x0067
#define OPTIC_FCSI_TXBOSA_PDS_RESET_OMU_A21 0x0000
/** reg #8:
fcsi_w(TXOMU_Base + TXOMU_TXEC , 0x3 << TXOMU_TXEC_BEN |
0x7 << TXOMU_TXEC_PCSE |
0x0 << TXOMU_TXEC_BYPST |
0x0 << TXOMU_TXEC_STE |
0xF << TXOMU_TXEC_SCSEL ); */
#define OPTIC_FCSI_TXOMU_TXEC_RESET 0xF707
#define OPTIC_FCSI_TXOMU_TXEC_RESET_BOSA 0x0000
#define OPTIC_FCSI_TXOMU_TXEC_RESET_OMU 0xF707
/** reg #9:
fcsi_w(TXOMU_Base + TXOMU_TXDC , 0x3 << TXOMU_TXDC_BEN |
0x7 << TXOMU_TXDC_PCSE |
0x0 << TXOMU_TXDC_BYPST |
0x0 << TXOMU_TXDC_STE |
0xF << TXOMU_TXDC_SCSEL ); */
#define OPTIC_FCSI_TXOMU_TXDC_RESET 0xF707
#define OPTIC_FCSI_TXOMU_TXDC_RESET_BOSA 0x0000
#define OPTIC_FCSI_TXOMU_TXDC_RESET_OMU 0xF707
/** reg #10:
fcsi_w(TXOMU_Base + TXOMU_CTRL , 0x0 << TXOMU_CTRL_CMEN |
0x0 << TXOMU_CTRL_CLKM |
0x0 << TXOMU_CTRL_DEM |
0x0 << TXOMU_CTRL_CINV |
0x0 << TXOMU_CTRL_SOVD |
0x0 << TXOMU_CTRL_SOEN |
0x1 << TXOMU_CTRL_SE |
0x0 << TXOMU_CTRL_TBED |
0x0 << TXOMU_CTRL_TBEE |
0x0 << TXOMU_CTRL_CINV8 ); */
#define OPTIC_FCSI_TXOMU_CTRL_RESET 0x0040
#define OPTIC_FCSI_TXOMU_CTRL_RESET_BOSA 0x0000
#define OPTIC_FCSI_TXOMU_CTRL_RESET_OMU 0x0040
/** reg #11:
fcsi_w(RXBOSA_Base + RXBOSA_CTRL , 0x0 << RXBOSA_CTRL_BLCM |
0x0 << RXBOSA_CTRL_BLCL |
0x0 << RXBOSA_CTRL_BLCH |
0x0 << RXBOSA_CTRL_ISOM |
0x0 << RXBOSA_CTRL_CDRR |
0x0 << RXBOSA_CTRL_CDRF |
0x0 << RXBOSA_CTRL_CDRD |
0x0 << RXBOSA_CTRL_CDRM |
0x0 << RXBOSA_CTRL_TDS |
0x0 << RXBOSA_CTRL_RST |
0x0 << RXBOSA_CTRL_CINV |
0x0 << RXBOSA_CTRL_DLCOM |
0x0 << RXBOSA_CTRL_C3OM ); */
/* \todo check for A21 */
#define OPTIC_FCSI_RXBOSA_CTRL_RESET 0x0000
#define OPTIC_FCSI_RXBOSA_CTRL_RESET_BOSA 0x0184
#define OPTIC_FCSI_RXBOSA_CTRL_RESET_OMU 0x0000
/** reg #13:
fcsi_w(RXOMU_Base + RXOMU_CTRL , 0x0 << RXOMU_CTRL_ISOM |
0x0 << RXOMU_CTRL_BLOC |
0x0 << RXOMU_CTRL_CDR |
0x0 << RXOMU_CTRL_CINV |
0x0 << RXOMU_CTRL_TDS ); */
#define OPTIC_FCSI_RXOMU_CTRL_RESET 0x0000
#define OPTIC_FCSI_RXOMU_CTRL_RESET_OMU 0x0000
#define OPTIC_FCSI_RXOMU_CTRL_RESET_BOSA 0x0000
#define OPTIC_FCSI_RXOMU_CTRL_RESET_BOSA_2 0x0002
/** reg #14:
fcsi_w(MM_Base + MM_CTRL , 0x0 << MM_CTRL_TINP |
0x0 << MM_CTRL_TINN |
0x1 << MM_CTRL_RVS |
0x1 << MM_CTRL_FBSEL |
0x1 << MM_CTRL_REFEN |
0x0 << MM_CTRL_OPBIAS |
0x0 << MM_CTRL_CINV ); */
#define OPTIC_FCSI_MM_CTRL_RESET 0x0024
#define OPTIC_FCSI_MM_CTRL_RESET_BOSA 0x0024
#define OPTIC_FCSI_MM_CTRL_RESET_OMU 0x0024
/** reg #15:
fcsi_w(VDAC_Base + VDAC_CTRL , 0x00 << VDAC_CTRL_VWD |
0x0 << VDAC_CTRL_LREN |
0x1 << VDAC_CTRL_OM ); */
#define OPTIC_FCSI_VDAC_CTRL_RESET 0x0400
#define OPTIC_FCSI_VDAC_CTRL_RESET_BOSA 0x0400
#define OPTIC_FCSI_VDAC_CTRL_RESET_OMU 0x0400
/** reg #16:
fcsi_w(BFD_Base + BFD_GVS , 0x0 << BFD_GVS_GAIN0 |
0x5 << BFD_GVS_GAIN1 |
0x6 << BFD_GVS_GAIN2 |
0xA << BFD_GVS_GAIN3 ); */
#define OPTIC_FCSI_BFD_GVS_RESET 0xEEA5
#define OPTIC_FCSI_BFD_GVS_RESET_BOSA 0xEEA5
#define OPTIC_FCSI_BFD_GVS_RESET_OMU 0x0000
/** reg #17:
fcsi_w(BFD_Base + BFD_CTRL0 , 0x4 << BFD_CTRL0_CMSEL |
0x0 << BFD_CTRL0_BLCD |
0x7 << BFD_CTRL0_RTSEL |
0x0 << BFD_CTRL0_CDRO |
0x0 << BFD_CTRL0_VCM0V6 |
0x0 << BFD_CTRL0_VCM0V5 |
0x0 << BFD_CTRL0_BLLD ); */
#define OPTIC_FCSI_BFD_CTRL0_RESET 0x0074
#define OPTIC_FCSI_BFD_CTRL0_RESET_BOSA 0x0074
#define OPTIC_FCSI_BFD_CTRL0_RESET_OMU 0x0000
/** reg #18:
fcsi_w(BFD_Base + BFD_CTRL1 , 0x0 << BFD_CTRL1_TDSEL |
0x0 << BFD_CTRL1_BLAP0 |
0x0 << BFD_CTRL1_BLAP1 |
0x0 << BFD_CTRL1_RST |
0x0 << BFD_CTRL1_CINV |
0x0 << BFD_CTRL1_RINV |
0x0 << BFD_CTRL1_LDO |
0x0 << BFD_CTRL1_IRED |
0x0 << BFD_CTRL1_PDLS ); */
#define OPTIC_FCSI_BFD_CTRL1_RESET 0x0200
#define OPTIC_FCSI_BFD_CTRL1_RESET_BOSA 0x0200
#define OPTIC_FCSI_BFD_CTRL1_RESET_OMU 0x0000
/** reg #19:
*/
#define OPTIC_FCSI_PI_CTRL_RESET 0x0000
#define OPTIC_FCSI_PI_CTRL_RESET_BOSA 0x00BC
#define OPTIC_FCSI_PI_CTRL_RESET_OMU 0x00F6
/** reg #20:
fcsi_w(CBIAS_Base + CBIAS_CTRL0 , 0x0 << CBIAS_CTRL0_IBFD |
0x0 << CBIAS_CTRL0_IVCM0V5 |
0x0 << CBIAS_CTRL0_IVCM0V6 |
0x0 << CBIAS_CTRL0_ITXBOSA |
0x0 << CBIAS_CTRL0_IDAC1550 |
0x0 << CBIAS_CTRL0_IMVCM ); */
#define OPTIC_FCSI_CBIAS_CTRL0_RESET 0x0000
#define OPTIC_FCSI_CBIAS_CTRL0_RESET_BOSA 0x0000
#define OPTIC_FCSI_CBIAS_CTRL0_RESET_OMU 0x0000
/** reg #21:
fcsi_w(CBIAS_Base + CBIAS_CTRL1 , 0x0 << CBIAS_CTRL1_BGPV |
0x0 << CBIAS_CTRL1_PD |
0x0 << CBIAS_CTRL1_BGPT |
0x0 << CBIAS_CTRL1_MCAL |
0x0 << CBIAS_CTRL1_UICT |
0x0 << CBIAS_CTRL1_UIRT ); */
#define OPTIC_FCSI_CBIAS_CTRL1_RESET 0x0000
#define OPTIC_FCSI_CBIAS_CTRL1_RESET_BOSA 0x0000
#define OPTIC_FCSI_CBIAS_CTRL1_RESET_OMU 0x0000
/** reg #24:
fcsi_w(VDLL_Base + VDLL_CTRL , 0x0 << VDLL_CTRL_VREF |
0x0 << VDLL_CTRL_ICP |
0x0 << VDLL_CTRL_IBIAS |
0x0 << VDLL_CTRL_MCLK ); */
#define OPTIC_FCSI_VDLL_CTRL_RESET 0x0000
#define OPTIC_FCSI_VDLL_CTRL_RESET_BOSA 0x0000
#define OPTIC_FCSI_VDLL_CTRL_RESET_OMU 0x0000
enum optic_errorcode optic_ll_fcsi_init ( const enum optic_manage_mode mode );
enum optic_errorcode optic_ll_fcsi_init_bosa_2nd ( void );
enum optic_errorcode optic_ll_fcsi_bfd_cfg ( const struct optic_config_fcsi
*fcsi );
enum optic_errorcode optic_ll_fcsi_write ( const vuint16_t *addr,
const uint32_t data );
enum optic_errorcode optic_ll_fcsi_read ( const vuint16_t *addr,
uint32_t *data );
enum optic_errorcode optic_ll_fcsi_fuses_set ( const uint8_t tbgp,
const uint8_t vbgp,
const uint8_t irefbpg );
enum optic_errorcode optic_ll_fcsi_powersave_set ( const enum optic_activation
powerdown );
enum optic_errorcode optic_ll_fcsi_predriver_set ( uint8_t dd_loadn,
uint8_t dd_bias_en,
uint8_t dd_loadp,
uint8_t dd_cm_load,
uint8_t bd_loadn,
uint8_t bd_bias_en,
uint8_t bd_loadp,
uint8_t bd_cm_load );
enum optic_errorcode optic_ll_fcsi_predriver_get ( uint8_t *dd_loadn,
uint8_t *dd_bias_en,
uint8_t *dd_loadp,
uint8_t *dd_cm_load,
uint8_t *bd_loadn,
uint8_t *bd_bias_en,
uint8_t *bd_loadp,
uint8_t *bd_cm_load );
enum optic_errorcode optic_ll_fcsi_predriver_switch (
const enum optic_activation mode );
enum optic_errorcode optic_ll_fcsi_predriver_switch_get (enum optic_activation *mode);
enum optic_errorcode optic_ll_fcsi_video_cfg_set ( const uint16_t video_word,
const bool video_range_low );
enum optic_errorcode optic_ll_fcsi_video_cfg_get ( uint16_t *video_word,
bool *video_range_low );
enum optic_errorcode optic_ll_fcsi_video_set ( const enum optic_activation
mode );
enum optic_errorcode optic_ll_fcsi_video_get ( enum optic_activation *mode );
enum optic_errorcode optic_ll_fcsi_bfd_get ( struct optic_bfd *bfd );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_FCSI == ACTIVE))
enum optic_errorcode optic_ll_fcsi_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, GPIO Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_GPIO_INTERNAL GPIO Module - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_gpio.h"
#if defined(LINUX)
#ifdef __KERNEL__
#include <linux/gpio.h>
#endif
#endif
#ifdef OPTIC_LIBRARY
#include <gpio.h>
#endif
#ifdef OPTIC_SIMULATION
#undef OPTIC_GPIO
#define OPTIC_GPIO INACTIVE
#endif
extern struct optic_irq_table * optic_irq_tbl;
static enum optic_errorcode optic_ll_gpio_check ( uint16_t port )
{
uint8_t pin= port % 100;
switch (port / 100) {
case 0:
if (pin > 14)
return OPTIC_STATUS_POOR;
break;
case 1:
if (pin > 13)
return OPTIC_STATUS_POOR;
break;
case 2:
if (pin > 24)
return OPTIC_STATUS_POOR;
break;
case 3:
if ((pin > 8) && ((pin < 23) || (pin > 25)))
return OPTIC_STATUS_POOR;
break;
case 4:
if ((pin > 6) && ((pin < 22) || (pin > 24)))
return OPTIC_STATUS_POOR;
break;
default:
return OPTIC_STATUS_POOR;
}
return OPTIC_STATUS_OK;
}
/**
Initialisate GPIO pins.
\return
- OPTIC_STATUS_OK - no errors,
- OPTIC_STATUS_ERR - error occurs
*/
enum optic_errorcode optic_ll_gpio_init ( const uint8_t signal_detect_port,
uint8_t *signal_detect_irq )
{
enum optic_errorcode ret;
OPTIC_DEBUG_ERR("gpio_to_irq: %d", signal_detect_port);
if (signal_detect_irq == NULL)
return OPTIC_STATUS_ERR;
ret = optic_ll_gpio_check ( signal_detect_port );
if (ret != OPTIC_STATUS_OK)
return ret;
/* configure dir register */
#if (OPTIC_GPIO == ACTIVE)
if (gpio_request (signal_detect_port,"OPTIC SignalDetectAlarm") < 0) {
OPTIC_DEBUG_ERR("gpio_request (%d) failed", signal_detect_port);
return OPTIC_STATUS_INIT_FAIL;
}
#ifndef OPTIC_LIBRARY
*signal_detect_irq = gpio_to_irq ( signal_detect_port );
if (*signal_detect_irq <= 0) {
OPTIC_DEBUG_ERR("gpio_to_irq (%d): %d",
signal_detect_port, *signal_detect_irq);
return OPTIC_STATUS_INIT_FAIL;
}
#endif
#endif
return ret;
}
enum optic_errorcode optic_ll_gpio_exit ( const uint8_t signal_detect_port )
{
#if (OPTIC_GPIO == ACTIVE)
gpio_free ( signal_detect_port );
#else
(void)signal_detect_port;
#endif
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_gpio_signaldetect_get ( const uint8_t
signal_detect_port,
bool *sd )
{
enum optic_errorcode ret;
if (sd == NULL)
return OPTIC_STATUS_ERR;
ret = optic_ll_gpio_check ( signal_detect_port );
if (ret != OPTIC_STATUS_OK)
return ret;
/* read GPIO port */
#if (OPTIC_GPIO == ACTIVE)
if (gpio_get_value ( signal_detect_port ))
*sd = true;
else
*sd = false;
#else
*sd = false;
#endif
return OPTIC_STATUS_OK;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_gpio.h
*/
#ifndef _drv_optic_ll_gpio_h
#define _drv_optic_ll_gpio_h
#include "drv_optic_api.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
#define OPTIC_P0_BASE (KSEG1 | 0x1D810000)
#define OPTIC_P0_END (KSEG1 | 0x1D810080)
#define OPTIC_P1_BASE (KSEG1 | 0x1E800100)
#define OPTIC_P1_END (KSEG1 | 0x1E800180)
#define OPTIC_P2_BASE (KSEG1 | 0x1D810100)
#define OPTIC_P2_END (KSEG1 | 0x1D810180)
#define OPTIC_P3_BASE (KSEG1 | 0x1E800200)
#define OPTIC_P3_END (KSEG1 | 0x1E800280)
#define OPTIC_P4_BASE (KSEG1 | 0x1E800300)
#define OPTIC_P4_END (KSEG1 | 0x1E800380)
#define EXINTCR1 0x1C
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_GPIO_INTERNAL GPIO Module - Internal
@{
*/
enum optic_errorcode optic_ll_gpio_init ( const uint8_t signal_detect_port,
uint8_t *signal_detect_irq );
enum optic_errorcode optic_ll_gpio_exit ( const uint8_t signal_detect_port );
enum optic_errorcode optic_ll_gpio_signaldetect_get ( const uint8_t
signal_detect_port,
bool *sd );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, GTC-PMA Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_GTC_PMA_INTERNAL GTC/PMA Interface Module - Internal
@{
*/
#include "drv_optic_ll_gtc.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_gtc_pma.h"
static enum optic_errorcode optic_ll_gtc_length_set ( const uint8_t length);
static enum optic_errorcode optic_ll_gtc_length_get ( uint8_t *length);
static enum optic_errorcode optic_ll_gtc_pattern_set ( const uint32_t
pattern[20] );
static enum optic_errorcode optic_ll_gtc_pattern_get ( uint32_t pattern[20] );
static enum optic_errorcode optic_ll_gtc_length_set ( const uint8_t length)
{
gtc_pma_w32_mask ( GTC_PMA_LTSC_LEN_MASK,
(((length > 78) ? 78 : length)
<< GTC_PMA_LTSC_LEN_OFFSET) &
GTC_PMA_LTSC_LEN_MASK, ltsc);
return OPTIC_STATUS_OK;
}
static enum optic_errorcode optic_ll_gtc_length_get ( uint8_t *length)
{
uint32_t reg;
if (length == NULL)
return OPTIC_STATUS_ERR;
reg = gtc_pma_r32 ( ltsc );
*length = (reg & GTC_PMA_LTSC_LEN_MASK) >> GTC_PMA_LTSC_LEN_OFFSET;
if (*length > 78)
*length = 78;
return OPTIC_STATUS_OK;
}
static enum optic_errorcode optic_ll_gtc_pattern_set ( const uint32_t
pattern[20] )
{
uint8_t i;
if (pattern == NULL)
return OPTIC_STATUS_ERR;
for (i=0; i<20; i++)
gtc_pma_w32(pattern[i], ltsdata[i]);
return OPTIC_STATUS_OK;
}
static enum optic_errorcode optic_ll_gtc_pattern_get ( uint32_t pattern[20] )
{
uint8_t i;
if (pattern == NULL)
return OPTIC_STATUS_ERR;
for (i=0; i<20; i++)
pattern[i] = gtc_pma_r32(ltsdata[i]);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_gtc_set ( const enum optic_activation mode )
{
gtc_pma_w32_mask ( GTC_PMA_LTSC_EN,
(mode == OPTIC_ENABLE)?
GTC_PMA_LTSC_EN : GTC_PMA_LTSC_EN_DIS,
ltsc);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_gtc_get ( enum optic_activation *mode )
{
uint32_t reg;
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg = gtc_pma_r32 ( ltsc );
if ((reg & GTC_PMA_LTSC_EN) == GTC_PMA_LTSC_EN)
*mode = OPTIC_ENABLE;
else
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_gtc_pattern_config_set ( const enum
optic_patternmode mode,
const uint32_t
pattern[20],
const uint8_t length )
{
enum optic_errorcode ret;
switch (mode) {
case OPTIC_PATTERNMODE_BERT:
gtc_pma_w32_mask ( GTC_PMA_LTSC_ENL, GTC_PMA_LTSC_ENL_EN,
ltsc);
break;
case OPTIC_PATTERNMODE_LTS:
gtc_pma_w32_mask ( GTC_PMA_LTSC_ENL, GTC_PMA_LTSC_ENL_DIS,
ltsc);
break;
default:
return OPTIC_STATUS_POOR;
}
ret = optic_ll_gtc_set ( OPTIC_DISABLE );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_gtc_length_set ( length );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_gtc_pattern_set ( pattern );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
enum optic_errorcode optic_ll_gtc_pattern_config_get ( enum
optic_patternmode *mode,
uint32_t pattern[20],
uint8_t *length )
{
enum optic_errorcode ret;
uint32_t reg;
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg = gtc_pma_r32 (ltsc);
if ((reg & GTC_PMA_LTSC_ENL) == GTC_PMA_LTSC_ENL_EN)
*mode = OPTIC_PATTERNMODE_BERT;
else
*mode = OPTIC_PATTERNMODE_LTS;
ret = optic_ll_gtc_length_get ( length );
if (ret != OPTIC_STATUS_OK)
return ret;
ret = optic_ll_gtc_pattern_get ( pattern );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_gtc.h
*/
#ifndef _drv_optic_ll_gtc_h
#define _drv_optic_ll_gtc_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_GTC_PMA_INTERNAL GTC/PMA Interface Module - Internal
@{
*/
enum optic_patternmode
{
OPTIC_PATTERNMODE_BERT,
OPTIC_PATTERNMODE_LTS,
};
enum optic_errorcode optic_ll_gtc_set ( const enum optic_activation mode );
enum optic_errorcode optic_ll_gtc_get ( enum optic_activation *mode );
enum optic_errorcode optic_ll_gtc_pattern_config_set ( const enum
optic_patternmode mode,
const uint32_t
pattern[20],
const uint8_t length );
enum optic_errorcode optic_ll_gtc_pattern_config_get ( enum optic_patternmode
*mode,
uint32_t pattern[20],
uint8_t *length );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, PMA INT Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_INT_INTERNAL Interrupt Module - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_int.h"
#include "drv_optic_ll_gpio.h"
#include "drv_optic_ll_mm.h"
#include "drv_optic_ll_rx.h"
#include "drv_optic_ll_pll.h"
#include "drv_optic_reg_pma_int200.h"
#include "drv_optic_reg_pma_inttx.h"
#include "drv_optic_reg_pma_intrx.h"
#include "drv_optic_reg_pma.h"
#if defined(LINUX) && !defined(OPTIC_SIMULATION)
DEFINE_SPINLOCK(irq_lock);
#endif
static uint32_t int_cnt[4];
enum optic_errorcode optic_ll_int_reset ( struct optic_interrupts *irq )
{
irq->signal_overload = false;
irq->signal_valid = false;
irq->signal_lost = false;
irq->rx_lock_lost = false;
irq->tx_overcurrent = false;
irq->tx_p0_interburst_alarm = false;
irq->tx_p0_intraburst_alarm = false;
/*
irq->tx_p1_interburst_alarm = false;
irq->tx_p1_intraburst_alarm = false;
*/
irq->tx_bias_limit = false;
irq->tx_mod_limit = false;
irq->temp_alarm_yellow = false;
irq->temp_alarm_red = false;
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_int_all_set ( const enum optic_activation mode )
{
static enum optic_activation mode_old = OPTIC_DISABLE;
#if defined(LINUX) && !defined(OPTIC_SIMULATION)
unsigned long flags;
#endif
if (mode == mode_old)
return OPTIC_STATUS_OK;
#if defined(LINUX) && !defined(OPTIC_SIMULATION)
spin_lock_irqsave(&irq_lock, flags);
#endif
mode_old = mode;
switch (mode) {
case OPTIC_ENABLE:
/* GPONSW-588, never enable HW interrupt for 200MHz */
pma_int200_w32 ( OPTIC_INT200_RESET , irnen);
pma_intrx_w32 ( OPTIC_INTRX_SET , irnen);
/* rogue interrupts are separately set */
pma_inttx_w32 (PMA_INTTX_IRNCR_MODL | PMA_INTTX_IRNCR_BIASL |
PMA_INTTX_IRNICR_OV, irnen);
break;
case OPTIC_DISABLE:
pma_int200_w32 ( OPTIC_INT200_RESET , irnen);
pma_intrx_w32 ( OPTIC_INTRX_RESET , irnen);
pma_inttx_w32 ( OPTIC_INTTX_RESET , irnen);
break;
default:
#if defined(LINUX) && !defined(OPTIC_SIMULATION)
spin_unlock_irqrestore(&irq_lock, flags);
#endif
return OPTIC_STATUS_POOR;
}
#if defined(LINUX) && !defined(OPTIC_SIMULATION)
spin_unlock_irqrestore(&irq_lock, flags);
#endif
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_int_omu_handle ( const enum optic_irq_type type,
const optic_isr callback_isr,
const uint8_t signal_detect_port,
struct optic_interrupts *irq )
{
enum optic_errorcode ret;
bool sd;
switch (type) {
case OPTIC_IRQ_TYPE_GPIO_SD:
ret = optic_ll_gpio_signaldetect_get ( signal_detect_port,
&sd );
if (ret != OPTIC_STATUS_OK)
return ret;
if (sd == true) {
irq->signal_valid = true;
irq->signal_lost = false;
optic_ll_rx_cdr_bpd ( OPTIC_ENABLE );
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_SD );
else
OPTIC_DEBUG_WRN("IRQ gpio: Signal Detect");
} else {
irq->signal_valid = false;
irq->signal_lost = true;
irq->rx_lock_lost = true;
optic_ll_rx_cdr_bpd ( OPTIC_DISABLE );
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_LOS );
else
OPTIC_DEBUG_WRN("IRQ gpio: Loss Of Signal");
}
break;
default:
return OPTIC_STATUS_POOR;
}
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_int_omu_get ( const bool signal_detect_avail,
struct optic_interrupts *irq,
bool *loss_of_signal,
bool *loss_of_lock )
{
enum optic_errorcode ret;
if ((loss_of_signal == NULL) || (loss_of_lock == NULL))
return OPTIC_STATUS_ERR;
if (signal_detect_avail == false) {
*loss_of_signal = true;
*loss_of_lock = true;
return OPTIC_STATUS_OK;
}
*loss_of_signal = irq->signal_lost;
/* get LOL status */
if (irq->signal_valid == true) {
ret = optic_ll_rx_lol_get ( &(irq->rx_lock_lost) );
if (ret != OPTIC_STATUS_OK)
return ret;
*loss_of_lock = irq->rx_lock_lost;
} else {
*loss_of_lock = true;
}
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_int_bosa_handle ( const enum optic_irq_type type,
const optic_isr callback_isr,
const uint16_t thresh_cw_los,
const uint16_t thresh_cw_ovl,
struct optic_interrupts *irq )
{
#if (OPTIC_BOSA_LOS_DISABLE_RX == ACTIVE)||(OPTIC_BOSA_IRQ_THRESHOLD_CHECK == ACTIVE)
enum optic_errorcode ret;
#endif
uint32_t reg, mask;
bool correctness;
switch (type) {
case OPTIC_IRQ_TYPE_INT200:
reg = pma_int200_r32 ( irncr );
if (reg & PMA_INT200_IRNCR_OVL) {
#if (OPTIC_BOSA_IRQ_THRESHOLD_CHECK == ACTIVE)
ret = optic_ll_mm_check_thresh ( OPTIC_IRQ_OVL,
thresh_cw_los,
thresh_cw_ovl,
&correctness );
if (ret != OPTIC_STATUS_OK)
correctness = false;
#else
correctness = true;
/* avoid compiler warnings */
(void)thresh_cw_los;
(void)thresh_cw_ovl;
#endif
pma_int200_w32_mask ( PMA_INT200_IRNCR_OVL, 0, irnen);
return OPTIC_STATUS_ERR;
if (correctness == false)
return OPTIC_STATUS_ERR;
irq->signal_overload = true;
irq->signal_valid = false;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_OVL );
else
OPTIC_DEBUG_WRN("IRQ INT200: OverLoad");
}
if (reg & PMA_INT200_IRNCR_SIGDET) {
#if (OPTIC_BOSA_IRQ_THRESHOLD_CHECK == ACTIVE)
ret = optic_ll_mm_check_thresh ( OPTIC_IRQ_SD,
thresh_cw_los,
thresh_cw_ovl,
&correctness );
if (ret != OPTIC_STATUS_OK)
correctness = false;
#else
correctness = true;
#endif
pma_int200_w32_mask ( PMA_INT200_IRNCR_SIGDET, 0,
irnen);
if (correctness == false)
return OPTIC_STATUS_ERR;
irq->signal_valid = true;
irq->signal_overload = false;
irq->signal_lost = false;
#if (OPTIC_BOSA_LOS_DISABLE_RX == ACTIVE)
ret = optic_ll_rx_afectrl_set ( OPTIC_ENABLE,
false );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_ll_rx_afectrl_set: %d",
ret);
return ret;
}
#endif
int_cnt[3]++;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_SD );
else
OPTIC_DEBUG_MSG("IRQ INT200: Signal Detect");
}
if (reg & PMA_INT200_IRNCR_LOS) {
#if (OPTIC_BOSA_IRQ_THRESHOLD_CHECK == ACTIVE)
ret = optic_ll_mm_check_thresh ( OPTIC_IRQ_LOS,
thresh_cw_los,
thresh_cw_ovl,
&correctness );
if (ret != OPTIC_STATUS_OK)
correctness = false;
#else
correctness = true;
#endif
pma_int200_w32_mask ( PMA_INT200_IRNCR_LOS, 0, irnen);
if (correctness == false)
return OPTIC_STATUS_ERR;
irq->signal_lost = true;
irq->signal_overload = false;
irq->signal_valid = false;
#if (OPTIC_BOSA_LOS_DISABLE_RX == ACTIVE)
ret = optic_ll_rx_afectrl_set ( OPTIC_DISABLE,
false );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_ll_rx_afectrl_set: %d",
ret);
return ret;
}
#endif
int_cnt[2]++;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_LOS );
else
OPTIC_DEBUG_MSG("IRQ INT200: Loss of Signal");
}
/* quit */
pma_int200_w32 ( reg, irncr );
break;
case OPTIC_IRQ_TYPE_INTRX:
reg = pma_intrx_r32 ( irncr );
if (reg & PMA_INTRX_IRNCR_LOL) {
pma_intrx_w32_mask ( PMA_INTRX_IRNCR_LOL, 0, irnen);
irq->rx_lock_lost = true;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_LOL );
else
OPTIC_DEBUG_WRN("IRQ INTRX: Loss Of Lock");
}
pma_intrx_w32 ( reg, irncr );
break;
case OPTIC_IRQ_TYPE_INTTX:
reg = pma_inttx_r32 ( irncr );
mask = 0;
if (reg & PMA_INTTX_IRNCR_OV) {
mask |= PMA_INTTX_IRNCR_OV;
irq->tx_overcurrent = true;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_OV );
else
OPTIC_DEBUG_WRN("IRQ INTTX: Overcurrent");
}
#if 0
/* disabled for further investigation */
if (reg & PMA_INTTX_IRNCR_BP1IBA) {
mask |= PMA_INTTX_IRNCR_BP1IBA;
irq->tx_p1_interburst_alarm = true;
if (callback_isr != NULL)
callback_isr (OPTIC_IRQ_BP1IBA);
else
OPTIC_DEBUG_WRN("IRQ INTTX: P1 Interburst Alarm");
}
if (reg & PMA_INTTX_IRNCR_BP1BA) {
mask |= PMA_INTTX_IRNCR_BP1BA;
irq->tx_p1_intraburst_alarm = true;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_BP1BA );
else
OPTIC_DEBUG_WRN("IRQ INTTX: P1 Intraburst Alarm");
}
#endif
if (reg & PMA_INTTX_IRNCR_BP0IBA) {
mask |= PMA_INTTX_IRNCR_BP0IBA;
irq->tx_p0_interburst_alarm = true;
int_cnt[1]++;
optic_ll_pll_rogue();
if (callback_isr != NULL)
callback_isr (OPTIC_IRQ_BP0IBA);
else
OPTIC_DEBUG_ERR("P0 Interburst Alarm -> "
"TX Disabled (Dualloop switched off) ");
}
if (reg & PMA_INTTX_IRNCR_BP0BA) {
mask |= PMA_INTTX_IRNCR_BP0BA;
irq->tx_p0_intraburst_alarm = true;
int_cnt[0]++;
optic_ll_pll_module_set (OPTIC_PLL_TX, false);
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_BP0BA );
else
OPTIC_DEBUG_ERR("OPTIC P0 Intraburst Alarm -> "
"TX Disabled");
}
if (reg & PMA_INTTX_IRNCR_BIASL) {
mask |= PMA_INTTX_IRNCR_BIASL;
irq->tx_bias_limit = true;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_BIASL );
else
OPTIC_DEBUG_WRN("IRQ INTTX: Bias Limit");
}
if (reg & PMA_INTTX_IRNCR_MODL) {
mask |= PMA_INTTX_IRNCR_MODL;
irq->tx_mod_limit = true;
if (callback_isr != NULL)
callback_isr ( OPTIC_IRQ_MODL );
else
OPTIC_DEBUG_WRN("IRQ INTTX: Modulation Limit");
}
pma_inttx_w32_mask (mask, 0, irnen);
pma_inttx_w32 ( reg, irncr );
break;
default:
return OPTIC_STATUS_POOR;
}
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_int_poll ( struct optic_interrupts *irq )
{
/*
uint32_t reg;
*/
/** poll int200 irqs */
/* int 200 interrupts enable each other - no polling necessary */
/*
reg = pma_int200_r32 ( irnicr );
*/
#if 1
if (irq->signal_overload == false) {
pma_int200_w32_mask ( 0, PMA_INT200_IRNCR_OVL, irnen);
}
if (irq->signal_valid == false) {
pma_int200_w32_mask ( 0, PMA_INT200_IRNCR_SIGDET, irnen);
}
if (irq->signal_lost == false) {
pma_int200_w32_mask ( 0, PMA_INT200_IRNCR_LOS, irnen);
}
#else
/* edge triggered */
if ((irq->signal_overload == true) &&
!(reg & PMA_INT200_IRNCR_OVL)) {
irq->signal_overload = false;
pma_int200_w32_mask ( 0, PMA_INT200_IRNCR_OVL, irnen);
}
if ((irq->signal_valid == true) &&
!(reg & PMA_INT200_IRNCR_SIGDET)) {
irq->signal_valid = false;
pma_int200_w32_mask ( 0, PMA_INT200_IRNCR_SIGDET, irnen);
}
if ((irq->signal_lost == true) &&
!(reg & PMA_INT200_IRNCR_LOS)) {
irq->signal_lost = false;
pma_int200_w32_mask ( 0, PMA_INT200_IRNCR_LOS, irnen);
}
#endif
/** poll rx irqs */
/*
reg = pma_intrx_r32 ( irnicr );
*/
if (irq->rx_lock_lost == false) {
pma_intrx_w32_mask ( 0, PMA_INTRX_IRNCR_LOL, irnen);
}
/** poll tx irqs */
/*
reg = pma_inttx_r32 ( irnicr );
*/
if (irq->tx_overcurrent == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_OV, irnen);
}
#if 0
if (irq->tx_p1_interburst_alarm == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_BP1IBA, irnen);
}
if (irq->tx_p1_intraburst_alarm == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_BP1BA, irnen);
}
if (irq->tx_p0_interburst_alarm == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_BP0IBA, irnen);
}
if (irq->tx_p0_intraburst_alarm == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_BP0BA, irnen);
}
#endif
if (irq->tx_bias_limit == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_BIASL, irnen);
}
if (irq->tx_mod_limit == false) {
pma_inttx_w32_mask ( 0, PMA_INTTX_IRNCR_MODL, irnen);
}
return OPTIC_STATUS_OK;
}
void optic_ll_int_counter_get (uint32_t **p_int_cnt)
{
*p_int_cnt = int_cnt;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_int.h
*/
#ifndef _drv_optic_ll_int_h
#define _drv_optic_ll_int_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
#include "drv_optic_interface.h"
#if defined(LINUX) && defined(__KERNEL__)
#include <linux/interrupt.h>
#ifdef CONFIG_SOC_FALCON
#include <falcon/falcon_irq.h>
#endif
#endif
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_IRQ_INTERNAL Interrupt Module - Internal
@{
*/
#define OPTIC_INT200_SET 0x00000007
#define OPTIC_INT200_RESET 0x00000000
#define OPTIC_INTTX_RESET 0x00000000
#define OPTIC_INTRX_SET 0x00000001
#define OPTIC_INTRX_RESET 0x00000000
enum optic_irq_type {
OPTIC_IRQ_TYPE_INT200,
OPTIC_IRQ_TYPE_INTRX,
OPTIC_IRQ_TYPE_INTTX,
OPTIC_IRQ_TYPE_GPIO_SD
};
#ifndef FALCON_IRQ_PMA_200M
# define FALCON_IRQ_PMA_200M 47
#endif
#ifndef FALCON_IRQ_PMA_TX
# define FALCON_IRQ_PMA_TX 48
#endif
#ifndef FALCON_IRQ_PMA_RX
# define FALCON_IRQ_PMA_RX 49
#endif
enum optic_errorcode optic_ll_int_reset ( struct optic_interrupts *irq );
enum optic_errorcode optic_ll_int_all_set ( const enum optic_activation mode );
enum optic_errorcode optic_ll_int_omu_handle ( const enum optic_irq_type type,
const optic_isr callback_isr,
const uint8_t signal_detect_port,
struct optic_interrupts *irq );
enum optic_errorcode optic_ll_int_omu_get ( const bool signal_detect_avail,
struct optic_interrupts *irq,
bool *loss_of_signal,
bool *loss_of_lock );
enum optic_errorcode optic_ll_int_bosa_handle ( const enum optic_irq_type type,
const optic_isr callback_isr,
const uint16_t thresh_cw_los,
const uint16_t thresh_cw_ovl,
struct optic_interrupts *irq );
enum optic_errorcode optic_ll_int_poll ( struct optic_interrupts *irq );
void optic_ll_int_counter_get (uint32_t **p_int_cnt);
void optic_enable_irq (uint32_t irq);
void optic_disable_irq (uint32_t irq);
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, PMA MM Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_MM_INTERNAL Measurement Module - Internal
@{
*/
/* activate SYSTEM_SIMULATION for using io_write and fcsi_w */
#include "drv_optic_ll_mm.h"
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_calc.h"
#include "drv_optic_ll_fcsi.h"
#include "drv_optic_reg_pma.h"
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_MMTIME == ACTIVE))
static uint32_t jiff[1000];
static uint8_t jiff_index = 0;
#endif
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_MMTIME == ACTIVE))
static void print_measure_jiffies ( int16_t measure_history[OPTIC_MEASURE_MAX]
[OPTIC_MM_INIT_AVERAGE_DEPTH] )
{
uint16_t type, j, t;
for (type=0; type<OPTIC_MEASURE_MAX; type++)
for (j=0; j<OPTIC_MM_INIT_AVERAGE_DEPTH; j++) {
if (j % 10 == 0) {
t = type*((OPTIC_MM_INIT_AVERAGE_DEPTH-1)/10+2);
OPTIC_DEBUG_ERR("measure(%d, %d): <%u>",
type, j/10, jiff[t + j/10 + 1]);
}
OPTIC_DEBUG_ERR("measure(%d): hist %d",
type, measure_history[type][j]);
}
return;
}
#endif
enum optic_errorcode optic_ll_mm_prepare ( const enum optic_measure_type type,
const uint8_t gain_selector,
const enum optic_rssi_1490_mode
rssi_1490_mode,
const enum optic_vref rssi_1550_vref,
const enum optic_vref rf_1550_vref,
const uint8_t start,
const uint8_t end )
{
uint32_t reg = OPTIC_MM_M_SET_RESET;
uint32_t fcsi;
uint8_t i;
switch (type) {
case OPTIC_MEASURE_GAIN_GS0:
case OPTIC_MEASURE_GAIN_GS1:
case OPTIC_MEASURE_GAIN_GS2:
case OPTIC_MEASURE_GAIN_GS3:
case OPTIC_MEASURE_GAIN_GS4:
case OPTIC_MEASURE_GAIN_GS5:
reg |= PMA_M_SET_ROP1490N |
PMA_M_SET_IREF;
if (gain_selector >= 5)
reg |= PMA_M_SET_IREFVAL; /* 20 uA */
if (is_falcon_chip_a1x())
break;
/* additional 300 uA via FCSI */
optic_ll_fcsi_read (FCSI_CBIAS_CTRL1, &fcsi );
if (gain_selector < 3) {
fcsi |= CBIAS_CTRL1_MCAL;
} else {
fcsi &= ~CBIAS_CTRL1_MCAL;
}
optic_ll_fcsi_write (FCSI_CBIAS_CTRL1, fcsi );
break;
case OPTIC_MEASURE_OFFSET_GS0:
case OPTIC_MEASURE_OFFSET_GS1:
case OPTIC_MEASURE_OFFSET_GS2:
case OPTIC_MEASURE_OFFSET_GS3:
case OPTIC_MEASURE_OFFSET_GS4:
case OPTIC_MEASURE_OFFSET_GS5:
reg |= PMA_M_SET_PN_SHORT;
break;
case OPTIC_MEASURE_VDD_HALF:
reg |= ((1<<PMA_M_SET_TS_OFFSET) &
PMA_M_SET_TS_MASK) | /* vdd */
((1<<PMA_M_SET_VREF_VAL_OFFSET) &
PMA_M_SET_VREF_VAL_MASK);
break;
case OPTIC_MEASURE_VBE1:
reg |= ((2<<PMA_M_SET_TS_OFFSET) &
PMA_M_SET_TS_MASK) | /* vbe1 */
((1<<PMA_M_SET_VREF_VAL_OFFSET) &
PMA_M_SET_VREF_VAL_MASK);
break;
case OPTIC_MEASURE_VBE2:
reg |= ((3<<PMA_M_SET_TS_OFFSET) &
PMA_M_SET_TS_MASK) | /* vbe2 */
((1<<PMA_M_SET_VREF_VAL_OFFSET) &
PMA_M_SET_VREF_VAL_MASK);
break;
case OPTIC_MEASURE_VOLTAGE_PN:
#if 1
reg |= PMA_M_SET_TSTRN |
PMA_M_SET_TSPN |
PMA_M_SET_VREF;
#else
reg |= PMA_M_SET_TSTRN1 |
PMA_M_SET_TSTRN |
PMA_M_SET_TSPN |
PMA_M_SET_IREF;
if (pn_iref == OPTIC_IREF_20UA)
reg |= PMA_M_SET_IREFVAL;
if (is_falcon_chip_a1x())
break;
/* additional 300 uA via FCSI */
optic_ll_fcsi_read (FCSI_CBIAS_CTRL1, &fcsi );
if (pn_iref == OPTIC_IREF_400UA)
fcsi |= CBIAS_CTRL1_MCAL;
else
fcsi &= ~CBIAS_CTRL1_MCAL;
optic_ll_fcsi_write (FCSI_CBIAS_CTRL1, fcsi );
#endif
break;
case OPTIC_MEASURE_POWER_RSSI_1490:
switch (rssi_1490_mode) {
case OPTIC_RSSI_1490_DIFFERENTIAL:
reg |= PMA_M_SET_DCDCAPD|
PMA_M_SET_ROP1490P;
break;
case OPTIC_RSSI_1490_SINGLE_ENDED:
reg |= PMA_M_SET_ROP1490N |
PMA_M_SET_ROP1490P;
break;
default:
return OPTIC_STATUS_POOR;
}
break;
case OPTIC_MEASURE_POWER_RF_1550:
reg |= ((rf_1550_vref << PMA_M_SET_VREF_VAL_OFFSET) &
PMA_M_SET_VREF_VAL_MASK) |
PMA_M_SET_RF1550;
break;
case OPTIC_MEASURE_POWER_RSSI_1550:
reg |= ((rssi_1550_vref << PMA_M_SET_VREF_VAL_OFFSET) &
PMA_M_SET_VREF_VAL_MASK) |
PMA_M_SET_ROP1550;
break;
default:
OPTIC_DEBUG_ERR("optic_ll_mm_prepare: invalid type %d", type);
return OPTIC_STATUS_POOR;
}
/* prepare M_SET */
reg |= (gain_selector << PMA_M_SET_GAIN_OFFSET) & PMA_M_SET_GAIN_MASK;
for (i=start; i<=end; i++) {
/* write M_SET */
pma_w32_table(reg, gpon_mm_slice_pdi_m_set, i);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP == ACTIVE))
OPTIC_DEBUG_ERR("optic_ll_mm_prepare: type %d, gain %d, ch %d: 0x%08X",
type, gain_selector, i, reg);
#endif
}
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_mm_measure ( const uint8_t *measure_type,
int16_t *read )
{
uint32_t reg;
/* uint32_t reg2; */
uint8_t i;
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_MMTIME == ACTIVE))
#if defined(LINUX) && !defined(OPTIC_SIMULATION)
if (p_ctrl->state.current_state < OPTIC_STATE_RUN)
jiff[jiff_index++] = jiffies;
#endif
#endif
for (i=0; i<OPTIC_MM_CHANNELS; i++) {
if (measure_type[i] == OPTIC_MEASURE_NONE)
continue;
reg = pma_r32_table(gpon_mm_slice_pdi_m_result, i);
/*
reg2 = pma_r32_table(gpon_mm_slice_pdi_m_set, i);
OPTIC_DEBUG_ERR("set: 0x%08x, result: %d", reg2, reg);
*/
read[i] = (int16_t) (reg & 0xFFFF);
}
return OPTIC_STATUS_OK;
}
/**
Initialize the Measurement Module (MM).
- Set ADC control to default values
GPON_MM_SLICE_PDI.ADC = 0x004C 9262
- Disable all measurement channels and open all hardware switches
GPON_MM_SLICE_PDI.M_SET_0...9 = 0x0000 0000
- Set the measurement time interval to 1 ms
(this is different from the hardware default value!)
GPON_MM_SLICE_PDI.M_TIME_CONFIG = 0x0000 7918
- Reset the ADC clock divider
GPON_MM_SLICE_PDI.MMADC_CLK = 0x0000 0001
GPON_MM_SLICE_PDI.MMADC_CLK = 0x0000 0000
- Initialize the LOS interrupt threshold
GPON_MM_SLICE_PDI.ALARM_CFG.LOS_CFG = 0x0000
- Initialize the overload interrupt threshold
GPON_MM_SLICE_PDI.ALARM_CFG.OVERLOAD_CFG = 0xFFFF
- Initialize MM filter paramaeters
GPON_MM_SLICE_PDI.MM_CFG.MM_CLKCFG = 0x0C
GPON_MM_SLICE_PDI.MM_CFG.MM_DECCFG = 0x0
- prepare M_SET for channel 1,2,3 (VDD/2, VBE1, VBE2)
- estimate gain selector for pn junction measurement (channel 4)
- prepare M_SET for channel 4
- Perform the measurement path calibration. optic_ll_mm_calibrate()
\return
- OPTIC_STATUS_OK - MM successfully initialized,
- OPTIC_STATUS_INIT_FAIL - MM not initialized
*/
enum optic_errorcode optic_ll_mm_init ( void )
{
uint8_t i;
uint32_t reg;
/* reset ADC */
reg = OPTIC_MM_ADC_RESET;
pma_w32(reg, gpon_mm_slice_pdi_adc);
/* disable all MM channels */
reg = OPTIC_MM_M_SET_RESET;
for (i=0; i<OPTIC_MM_CHANNELS; i++) {
pma_w32_table(reg, gpon_mm_slice_pdi_m_set, i);
}
/* set measurement time interval to 1 ms = 31000 (in 31 MHz cycles) */
reg = (OPTIC_M_TIME_CONFIG_MEAS_TIME_INIT <<
PMA_M_TIME_CONFIG_MEAS_TIME_OFFSET) &
PMA_M_TIME_CONFIG_MEAS_TIME_MASK;
pma_w32(reg, gpon_mm_slice_pdi_m_time_config);
/* reset ADC clock divider */
reg = PMA_MMADC_CLK_DIV_RESET;
pma_w32(reg, gpon_mm_slice_pdi_mmadc_clk);
reg = 0;
pma_w32(reg, gpon_mm_slice_pdi_mmadc_clk);
/* init mm filter */
reg = ((OPTIC_MM_CFG_MM_DECCFG_INIT << PMA_MM_CFG_MM_DECCFG_OFFSET) &
PMA_MM_CFG_MM_DECCFG_MASK) |
((OPTIC_MM_CFG_MM_CLKCFG_INIT << PMA_MM_CFG_MM_CLKCFG_OFFSET) &
PMA_MM_CFG_MM_CLKCFG_MASK);
pma_w32(reg, gpon_mm_slice_pdi_mm_cfg);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_mm_thresh_reg_set ( const uint16_t ovl_cw,
const uint16_t los_cw )
{
uint32_t reg;
reg = ((ovl_cw << PMA_ALARM_CFG_OVERLOAD_CFG_OFFSET) &
PMA_ALARM_CFG_OVERLOAD_CFG_MASK) |
((los_cw << PMA_ALARM_CFG_LOS_CFG_OFFSET) &
PMA_ALARM_CFG_LOS_CFG_MASK);
pma_w32 ( reg, gpon_mm_slice_pdi_alarm_cfg );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_mm_check_thresh ( const enum optic_irq irq,
const uint16_t thresh_cw_los,
const uint16_t thresh_cw_ovl,
bool *correctness )
{
uint16_t reg;
if (correctness == NULL)
return OPTIC_STATUS_ERR;
*correctness = false;
reg = abs ((int16_t) (pma_r32_table(gpon_mm_slice_pdi_m_result, 9)));
switch (irq) {
case OPTIC_IRQ_SD:
if (reg > thresh_cw_los)
*correctness = true;
break;
case OPTIC_IRQ_LOS:
if (reg < thresh_cw_los)
*correctness = true;
break;
case OPTIC_IRQ_OVL:
if (reg > thresh_cw_ovl)
*correctness = true;
break;
default:
*correctness = true;
break;
}
return OPTIC_STATUS_OK;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_mm.h
*/
#ifndef _drv_optic_ll_mm_h
#define _drv_optic_ll_mm_h
#ifndef SYSTEM_SIMULATION
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#else
#include "drv_optic_simu.h"
#endif
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_MM_INTERNAL Measurement Module - Internal
@{
*/
#define OPTIC_MM_ADC_RESET 0x004C9262
#define OPTIC_MM_M_SET_RESET 0x00000000
#define OPTIC_MM_CFG_MM_DECCFG_INIT 4
#define OPTIC_MM_CFG_MM_CLKCFG_INIT 0xF2
#define OPTIC_M_TIME_CONFIG_MEAS_TIME_INIT 62000
#define OPTIC_MM_CHANNELS 10
/* parallel mode */
/* "channel"-value > 10 means: channel = { 0 ... (value-10) } <- multiple
measurement via several channels */
#define OPTIC_CHANNEL_MEASURE_GAIN 12
#define OPTIC_CHANNEL_MEASURE_OFFSET 12
#define OPTIC_CHANNEL_MEASURE_VDD_HALF 3
#define OPTIC_CHANNEL_MEASURE_VBE1 4
#define OPTIC_CHANNEL_MEASURE_VBE2 5
#define OPTIC_CHANNEL_MEASURE_VOLTAGE_PN 6
#define OPTIC_CHANNEL_MEASURE_POWER_RSSI_1550 7
#define OPTIC_CHANNEL_MEASURE_POWER_RF_1550 8
#define OPTIC_CHANNEL_MEASURE_POWER_RSSI_1490 9
#define OPTIC_CHANNEL_MEASURE_UPDATE_CYCLE 10
#define OPTIC_CHANNEL_MEASURE_RSSI_UPDATE_CYCLE 4
enum optic_errorcode optic_ll_mm_init ( void );
enum optic_errorcode optic_ll_mm_prepare ( const enum optic_measure_type type,
const uint8_t gain_selector,
const enum optic_rssi_1490_mode
rssi_1490_mode,
const enum optic_vref rssi_1550_vref,
const enum optic_vref rf_1550_vref,
const uint8_t start,
const uint8_t end );
enum optic_errorcode optic_ll_mm_measure ( const uint8_t *measure_type,
int16_t *read );
enum optic_errorcode optic_ll_mm_thresh_reg_set ( const uint16_t ovl_cw,
const uint16_t los_cw );
enum optic_errorcode optic_ll_mm_check_thresh ( const enum optic_irq irq,
const uint16_t thresh_cw_los,
const uint16_t thresh_cw_ovl,
bool *correctness );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_mpd.h
*/
#ifndef _drv_optic_ll_mpd_h
#define _drv_optic_ll_mpd_h
#ifndef SYSTEM_SIMULATION
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#else
#include "drv_optic_simu.h"
#endif
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_MPD_INTERNAL MPD Interface - Internal
@{
*/
#define P0_DUAL_LOOP_RESET 0x0FE008C0
#define P1_DUAL_LOOP_RESET 0x0FE008C0
#define LOOP_REGULATION_BIAS_RESET 0x42002080
#define LOOP_REGULATION_MODULATION_RESET 0x42002080
enum optic_dac_type {
OPTIC_DAC_TIA_OFFSET,
OPTIC_DAC_P0_LEVEL,
OPTIC_DAC_P1_LEVEL,
OPTIC_DAC_MAX
};
enum optic_p_type {
OPTIC_P0,
OPTIC_P1
};
enum optic_errorcode optic_ll_mpd_init ( const struct optic_config_monitor
*monitor,
const enum optic_bosa_loop_mode
loop_mode );
enum optic_errorcode optic_ll_mpd_exit ( void );
enum optic_errorcode optic_ll_mpd_level_set ( const enum optic_search_type type,
const int16_t level );
#if 0
enum optic_errorcode optic_ll_mpd_level_get ( const enum optic_search_type type,
int16_t *level );
#endif
enum optic_errorcode optic_ll_mpd_disable_powersave(void);
enum optic_errorcode optic_ll_mpd_level_find ( const enum optic_loop_mode burstmode, const enum optic_search_type
type,
const bool read_p0,
int32_t gain,
int16_t *level,
int16_t *level_c);
enum optic_errorcode optic_ll_mpd_loop_set ( const struct optic_config_monitor
*monitor,
enum optic_loop_mode *loopmode,
const enum optic_loop_mode
loopmode_p0,
const enum optic_loop_mode
loopmode_p1 );
enum optic_errorcode optic_ll_mpd_cint_set ( const enum optic_current_type
type,
const uint8_t intcoeff,
const uint16_t saturation );
enum optic_errorcode optic_ll_mpd_dac_set ( enum optic_dac_type dac,
const int16_t coarse,
const int16_t fine );
enum optic_errorcode optic_ll_mpd_dac_get ( enum optic_dac_type dac,
int16_t *off_c,
int16_t *off_f );
enum optic_errorcode optic_ll_mpd_trace_get ( uint16_t *correlator_trace_p0,
uint16_t *correlator_trace_p1,
uint16_t *trace_pattern_p0,
uint16_t *trace_pattern_p1 );
enum optic_errorcode optic_ll_mpd_update_get ( const enum optic_current_type
type,
const uint8_t int_coeff,
bool *update );
enum optic_errorcode optic_ll_mpd_saturation_write ( const uint16_t bias_sat,
const uint16_t mod_sat );
enum optic_errorcode optic_ll_mpd_saturation_read ( uint16_t *bias_sat,
uint16_t *mod_sat );
enum optic_errorcode optic_ll_mpd_bias_write ( const uint16_t dbias );
enum optic_errorcode optic_ll_mpd_biaslowsat_write ( const uint16_t dbias );
enum optic_errorcode optic_ll_mpd_bias_read ( uint16_t *dbias );
#if 0
enum optic_errorcode optic_ll_mpd_gain_toggle (void);
#endif
enum optic_errorcode optic_ll_mpd_bias_check ( bool *update );
enum optic_errorcode optic_ll_mpd_mod_write ( const uint16_t dmod );
enum optic_errorcode optic_ll_mpd_mod_read ( uint16_t *dmod );
enum optic_errorcode optic_ll_mpd_mod_check ( bool *update );
enum optic_errorcode optic_ll_mpd_compstatus_get ( uint16_t *p0_cnt,
uint16_t *p1_cnt );
enum optic_errorcode optic_ll_mpd_powersave_set ( const enum optic_activation
powerdown );
enum optic_errorcode optic_ll_mpd_powersave_get ( enum optic_activation
*powerdown );
enum optic_errorcode optic_ll_mpd_gainctrl_set ( const uint8_t
tia_gain_selector,
const uint8_t
calibration_current );
void optic_ll_mpd_az_delay_set (uint8_t p0_az, uint8_t p1_az);
enum optic_errorcode optic_ll_mpd_az_delay_get (uint8_t *p0_az,
uint8_t *p1_az);
void optic_ll_mpd_rogue_int_set ( const enum optic_activation iba_mode,
const enum optic_activation ba_mode);
void optic_ll_mpd_ib_handle (uint32_t *ib_check_old, bool rw);
void optic_ll_mpd_p0cnt_get (uint32_t *p0_cnt);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_MPD == ACTIVE))
enum optic_errorcode optic_ll_mpd_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, OCTRLG Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_OCTRLG_INTERNAL OCTRLG Interface Module - Internal
@{
*/
#include "drv_optic_ll_gtc.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_octrlg.h"
#ifndef OPTIC_LIBRARY
/**
this function reads total transmitted bytes counter and recalculate
laser life time. Function has to be called at least each 27 seconds
*/
enum optic_errorcode optic_ll_octrlg_ageupdate ( uint8_t *seconds )
{
uint32_t reg, diff;
static uint32_t reg_old = 0;
static uint32_t last = 0;
if (seconds == NULL)
return OPTIC_STATUS_ERR;
#ifndef OPTIC_SIMULATION
reg = octrlg_r32 ( txtcnt );
#else
reg = 0;
#endif
if (reg > reg_old)
diff = reg - reg_old;
else
diff = 0xFFFFFFFF - reg_old + reg + 1;
/* not clear on read */
#if 1
reg_old = reg;
#endif
/* counter = 19440 in 125 us */
*seconds = diff / (0x9450C00);
last += (diff % (0x9450C00));
if (last > 0x9450C00) {
(*seconds) ++;
last -= 0x9450C00;
}
return OPTIC_STATUS_OK;
}
#endif
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_octrlg.h
*/
#ifndef _drv_optic_ll_octrlg_h
#define _drv_optic_ll_octrlg_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_OCTRLG_INTERNAL OCTRLG Interface Module - Internal
@{
*/
enum optic_errorcode optic_ll_octrlg_ageupdate ( uint8_t *seconds );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, PMA PLL Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_PLL_INTERNAL PLL Module - Internal
@{
*/
#include "drv_optic_ll_pll.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_pma.h"
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_PLL == ACTIVE))
static enum optic_errorcode optic_ll_pll_dump ( void );
static enum optic_errorcode optic_ll_pll_dump_status ( void );
#endif
/**
Calibrate PLL and wait for locking.
\return
- OPTIC_STATUS_PLL_LOCKED - PLL locked,
- OPTIC_STATUS_PLL_NOTLOCKED - PLL not locked
- OPTIC_STATUS_PLL_LOCKTIMEOUT - timeout while PLL calibration
1. Activate the PLL
tmp = (
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_BIAS(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_CP(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_DIV(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_DIV2(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_DIV8(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_DIV5(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_FIX_PH_CORE_F(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_FD_IN_BUFFER(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_LDO_VCO(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_LF(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_PWD_VREFS(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_REF_CLK_O_MTR_EN(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_REFCLK_O_EN(1) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_REFCLK_SEL(1) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_TEST_EXT_FD_IN_EN(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_VCO_VCTRL_WHEN_CT(0) |
ELEM_GPON_PLL_SLICE_PDI_A_CTRL3_MMD(46));
io_write(ADR_GPON_PLL_SLICE_PDI_A_CTRL3, tmp);
2. Wait 5 us
3. Release the PLL reset
tmp = (
ELEM_GPON_PLL_SLICE_PDI_CTRL2_CONST_SDM(0x83) |
ELEM_GPON_PLL_SLICE_PDI_CTRL2_EN_CONST_SDM_REG(0) |
ELEM_GPON_PLL_SLICE_PDI_CTRL2_EN_CONST_SDM(1) |
ELEM_GPON_PLL_SLICE_PDI_CTRL2_PLL_ENSDM(1) |
ELEM_GPON_PLL_SLICE_PDI_CTRL2_PLL_ENWAVEGEN(0) |
ELEM_GPON_PLL_SLICE_PDI_CTRL2_PLLDIGTEST(0) |
ELEM_GPON_PLL_SLICE_PDI_CTRL2_PLL_RESETN(1));
io_write(ADR_GPON_PLL_SLICE_PDI_CTRL2, tmp);
4. Wait for PLL lock, check GPON_PLL_SLICE_PDI.STATUS.LOCK 0 --> 1
*/
enum optic_errorcode optic_ll_pll_calibrate ( void )
{
enum optic_errorcode ret;
uint32_t reg;
uint32_t cnt = 100;
/* try PLL start like in phyton scrip
* is however only slightly different to "original"
* implementation by Henrik
* Commented because stuck on boot seen in rarely occasions
*/
#if 0
/*write reset values to HW*/
pma_w32 ( 0x00000AB6, gpon_pll_slice_pdi_pmd_resetcontrol );
pma_w32 ( 0x00008e39, gpon_pll_slice_pdi_ctrl1 );
pma_w32 ( 0x00000283, gpon_pll_slice_pdi_ctrl2 );
pma_w32 ( 0x00000041, gpon_pll_slice_pdi_ctrl3 );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_ctrl4 );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_ctrl5 );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_ctrl6 );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_ctrl7 );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_a_ctrl1 );
pma_w32 ( 0x00018000, gpon_pll_slice_pdi_a_ctrl2 );
pma_w32 ( 0x00B86001, gpon_pll_slice_pdi_a_ctrl3 );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_status );
pma_w32 ( 0x00000000, gpon_pll_slice_pdi_pma_top_ctrl );
/* OPTIC_DEBUG_ERR("PLL reset"); */
/* PD PLL*/
reg = ((0x2E << PMA_A_CTRL3_MMD_OFFSET) & PMA_A_CTRL3_MMD_MASK) |
((1 << PMA_A_CTRL3_VCO_VCTRL_WHEN_CT_OFFSET) & PMA_A_CTRL3_VCO_VCTRL_WHEN_CT_MASK) |
PMA_A_CTRL3_REFCLK_SEL |
PMA_A_CTRL3_REFCLK_O_EN |
PMA_A_CTRL3_PWD;
pma_w32 ( reg, gpon_pll_slice_pdi_a_ctrl3 );
/* supply adjust */
reg = ((0x5 << PMA_A_CTRL2_LDO_VREF_SEL_OFFSET) & PMA_A_CTRL2_LDO_VREF_SEL_MASK) |
((0x3 << PMA_A_CTRL2_CURR_SEL_PI_OFFSET) & PMA_A_CTRL2_CURR_SEL_PI_MASK) |
((0x3 << PMA_A_CTRL2_CURR_SEL_DIV2_OFFSET) & PMA_A_CTRL2_CURR_SEL_DIV2_MASK);
pma_w32 ( reg, gpon_pll_slice_pdi_a_ctrl2 );
reg = PMA_CTRL2_PLL_ENSDM |
PMA_CTRL2_EN_CONST_SDM_EN |
((0x83 << PMA_CTRL2_CONST_SDM_OFFSET) & PMA_CTRL2_CONST_SDM_MASK);
pma_w32 ( reg, gpon_pll_slice_pdi_ctrl2 );
optic_udelay(100);
/* release PLL powerdown */
reg = ((0x2E << PMA_A_CTRL3_MMD_OFFSET) & PMA_A_CTRL3_MMD_MASK) |
((1 << PMA_A_CTRL3_VCO_VCTRL_WHEN_CT_OFFSET) & PMA_A_CTRL3_VCO_VCTRL_WHEN_CT_MASK) |
PMA_A_CTRL3_REFCLK_SEL |
PMA_A_CTRL3_REFCLK_O_EN;
pma_w32 ( reg, gpon_pll_slice_pdi_a_ctrl3 );
optic_udelay(100);
/* release digital PLL reset */
reg = PMA_CTRL2_PLL_RESETN |
PMA_CTRL2_EN_CONST_SDM_EN |
PMA_CTRL2_PLL_ENSDM |
((0x83 << PMA_CTRL2_CONST_SDM_OFFSET) & PMA_CTRL2_CONST_SDM_MASK);
pma_w32 ( reg, gpon_pll_slice_pdi_ctrl2 );
reg = ((0x0D << PMA_CTRL3_EXT_SELVCO_OFFSET) &
PMA_CTRL3_EXT_SELVCO_MASK) |
((4 << PMA_CTRL3_EXT_MMD_DIV_RATIO_OFFSET) &
PMA_CTRL3_EXT_MMD_DIV_RATIO_MASK) |
PMA_CTRL3_EN_BIN_CAL_EN;
pma_w32 ( reg, gpon_pll_slice_pdi_ctrl3 );
optic_udelay(100);
/* OPTIC_DEBUG_ERR("PLL wait lock"); */
#endif
#if 1
/* manually tune the vco */
optic_ll_pll_vco_set ();
/* reset to digital PLL */
reg = PMA_CTRL2_PLL_ENSDM |
PMA_CTRL2_EN_CONST_SDM_EN |
((0x83 << PMA_CTRL2_CONST_SDM_OFFSET) & PMA_CTRL2_CONST_SDM_MASK);
pma_w32 ( reg, gpon_pll_slice_pdi_ctrl2 );
/* deactivate analog power down, activate PLL */
reg = ((46 << PMA_A_CTRL3_MMD_OFFSET) & PMA_A_CTRL3_MMD_MASK) |
((1 << PMA_A_CTRL3_VCO_VCTRL_WHEN_CT_OFFSET) &
PMA_A_CTRL3_VCO_VCTRL_WHEN_CT_MASK) |
PMA_A_CTRL3_REFCLK_SEL |
PMA_A_CTRL3_REFCLK_O_EN |
PMA_A_CTRL3_PWD;
pma_w32 ( reg, gpon_pll_slice_pdi_a_ctrl3 );
ret = optic_ll_pll_start ( OPTIC_NOMODE );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("optic_ll_pll_calibrate: %d",
ret);
}
pma_w32_mask ( PMA_A_CTRL3_PWD, 0, gpon_pll_slice_pdi_a_ctrl3 );
/* release reset to digital PLL */
reg = PMA_CTRL2_PLL_RESETN |
PMA_CTRL2_PLL_ENSDM |
PMA_CTRL2_EN_CONST_SDM_EN |
((0x83 << PMA_CTRL2_CONST_SDM_OFFSET) & PMA_CTRL2_CONST_SDM_MASK);
pma_w32 ( reg, gpon_pll_slice_pdi_ctrl2 );
/* release reset to digital PLL */
reg = ((0x3 << PMA_A_CTRL2_LDO_VREF_SEL_OFFSET) &
PMA_A_CTRL2_LDO_VREF_SEL_MASK) |
((0x3 << PMA_A_CTRL2_CURR_SEL_PI_OFFSET) &
PMA_A_CTRL2_CURR_SEL_PI_MASK) |
((0x5 << PMA_A_CTRL2_CURR_SEL_DIV2_OFFSET) &
PMA_A_CTRL2_CURR_SEL_DIV2_MASK);
pma_w32 ( reg, gpon_pll_slice_pdi_a_ctrl2 );
/* wait to release reset to digital PLL */
optic_udelay(100);
#endif
/* wait until PLL locked */
while ((cnt) && (((pma_r32(gpon_pll_slice_pdi_status) &
PMA_STATUS_STARTUP_RDY_MASK) >>
PMA_STATUS_STARTUP_RDY_OFFSET) != 1)) {
cnt--;
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_PLL == ACTIVE))
optic_ll_pll_dump_status ();
#endif
optic_udelay(10);
}
optic_udelay(100);
/* try PLL start like in phyton scrip
* is however only slightly different to "original"
* implementation by Henrik
* Commented because stuck on boot seen in rarely occasions
*/
#if 0
/* no PD, but still reset */
pma_w32 ( 0x0, gpon_pll_slice_pdi_pmd_resetcontrol );
#endif
/* PLL calibration finished */
if (cnt) {
return optic_ll_pll_check ( );
} else
return OPTIC_STATUS_PLL_LOCKTIMEOUT;
}
enum optic_errorcode optic_ll_pll_vco_set ( void )
{
uint32_t reg;
reg = ((0x0D << PMA_CTRL3_EXT_SELVCO_OFFSET) &
PMA_CTRL3_EXT_SELVCO_MASK) |
((4 << PMA_CTRL3_EXT_MMD_DIV_RATIO_OFFSET) &
PMA_CTRL3_EXT_MMD_DIV_RATIO_MASK) |
PMA_CTRL3_EN_BIN_CAL_EN;
/* don't use external SEL VCO
if (mode == OPTIC_ENABLE)
reg |= PMA_CTRL3_EN_EXT_SELVCO_EN;
*/
pma_w32 ( reg, gpon_pll_slice_pdi_ctrl3 );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_PLL == ACTIVE))
OPTIC_DEBUG_WRN("PLL CTRL3: 0x%08X", reg);
#endif
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_pll_check ( void )
{
if ((pma_r32(gpon_pll_slice_pdi_status) & PMA_STATUS_LOCK)
== PMA_STATUS_LOCK)
return OPTIC_STATUS_PLL_LOCKED;
else
return OPTIC_STATUS_PLL_NOTLOCKED;
}
/**
set omu/bosa mode, reset power down
A) OMU:
1. Select the OMU operation mode
tmp = (
ELEM_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL_EXT_LASER_EN(0) |
ELEM_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL_TX_CLK_SEL(1) |
ELEM_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL_RX_CLK_SEL(1) );
io_write(ADR_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL, tmp);
2. Disable reset for TX(omu), RX(omu), MM, DLL
Disable power down for RXOMU, TXOMU, MM, DLL
tmp = (
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_TX_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_TX_PD(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_TXOMU_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_RX_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_RX_PD(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_RXOMU_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_BFD_RSTN(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_BFD_PD(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_MM_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_MM_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_DLL_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_DLL_PD(0) );
io_write(ADR_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL, tmp);
B) BOSA:
1. Select the OMU operation mode
tmp = (
ELEM_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL_EXT_LASER_EN(0) |
ELEM_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL_TX_CLK_SEL(0) |
ELEM_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL_RX_CLK_SEL(0) );
io_write(ADR_GPON_PLL_SLICE_PDI_PMA_TOP_CTRL, tmp);
2. Disable reset for TX(omu), RX(omu), BFD, MM, DLL
Disable power down for RX, TX, BFD, MM, DLL
tmp = (
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_TX_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_TX_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_TXOMU_PD(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_RX_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_RX_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_RXOMU_PD(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_BFD_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_BFD_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_MM_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_MM_PD(0) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_DLL_RSTN(1) |
ELEM_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL_DLL_PD(0) );
io_write(ADR_GPON_PLL_SLICE_PDI_PMD_RESETCONTROL, tmp);
*/
enum optic_errorcode optic_ll_pll_start ( const enum optic_manage_mode mode )
{
uint32_t reg_top_ctrl = 0, reg_resetcontrol;
/* keep voice pll as defined by voice driver if any */
reg_resetcontrol = pma_r32 (gpon_pll_slice_pdi_pmd_resetcontrol) &
(PMA_PMD_RESETCONTROL_DLL_PD | PMA_PMD_RESETCONTROL_DLL_RSTN);
switch (mode) {
case OPTIC_NOMODE:
/* OMU mode for TX + RX clock */
reg_top_ctrl = (PMA_PMA_TOP_CTRL_TX_CLK_SEL |
PMA_PMA_TOP_CTRL_RX_CLK_SEL);
/* all power down + reset */
reg_resetcontrol |= (PMA_PMD_RESETCONTROL_MM_PD |
PMA_PMD_RESETCONTROL_BFD_PD |
PMA_PMD_RESETCONTROL_TXOMU_PD |
PMA_PMD_RESETCONTROL_TX_PD |
PMA_PMD_RESETCONTROL_RXOMU_PD |
PMA_PMD_RESETCONTROL_RX_PD);
break;
case OPTIC_OMU:
/* OMU mode for TX + RX clock */
reg_top_ctrl = (PMA_PMA_TOP_CTRL_TX_CLK_SEL |
PMA_PMA_TOP_CTRL_RX_CLK_SEL|
PMA_PMA_TOP_CTRL_EXT_LASER_EN);
/* disable power down + no reset RX/TX OMU, DLL, MM */
reg_resetcontrol |= (PMA_PMD_RESETCONTROL_MM_RSTN |
PMA_PMD_RESETCONTROL_BFD_PD |
PMA_PMD_RESETCONTROL_TX_PD |
PMA_PMD_RESETCONTROL_TX_RSTN |
PMA_PMD_RESETCONTROL_RX_PD |
PMA_PMD_RESETCONTROL_RX_RSTN);
break;
case OPTIC_BOSA:
/* no OMU mode for TX + RX clock */
reg_top_ctrl = 0;
/* disable power down + no reset RX/TX, DLL, MM, BFD */
reg_resetcontrol |= (PMA_PMD_RESETCONTROL_MM_RSTN |
PMA_PMD_RESETCONTROL_BFD_RSTN |
PMA_PMD_RESETCONTROL_TXOMU_PD |
PMA_PMD_RESETCONTROL_TX_RSTN |
PMA_PMD_RESETCONTROL_RXOMU_PD |
PMA_PMD_RESETCONTROL_RX_RSTN);
break;
case OPTIC_BOSA_2:
/* OMU mode for RX clock */
reg_top_ctrl = (PMA_PMA_TOP_CTRL_RX_CLK_SEL|
PMA_PMA_TOP_CTRL_EXT_LASER_EN);
/* disable power down + no reset RX OMU/TX, DLL, MM, BFD */
reg_resetcontrol |= (PMA_PMD_RESETCONTROL_MM_RSTN |
PMA_PMD_RESETCONTROL_BFD_RSTN |
PMA_PMD_RESETCONTROL_TXOMU_PD |
PMA_PMD_RESETCONTROL_TX_RSTN |
PMA_PMD_RESETCONTROL_RX_PD |
PMA_PMD_RESETCONTROL_RX_RSTN);
break;
default:
return OPTIC_STATUS_POOR;
}
pma_w32 ( reg_top_ctrl, gpon_pll_slice_pdi_pma_top_ctrl );
pma_w32 ( reg_resetcontrol, gpon_pll_slice_pdi_pmd_resetcontrol );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_PLL == ACTIVE))
optic_ll_pll_dump ();
#endif
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_pll_laser_set ( const bool single_ended )
{
pma_w32_mask ( PMA_PMA_TOP_CTRL_EXT_LASER_EN, (single_ended == true)?
PMA_PMA_TOP_CTRL_EXT_LASER_EN : 0,
gpon_pll_slice_pdi_pma_top_ctrl );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_PLL == ACTIVE))
OPTIC_DEBUG_WRN("PLL TOP_CTRL: 0x%08X",
pma_r32 ( gpon_pll_slice_pdi_pma_top_ctrl ));
#endif
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_pll_rogue (void)
{
pma_w32_mask ( PMA_PMD_RESETCONTROL_TX_RSTN |
PMA_PMD_RESETCONTROL_TX_PD |
PMA_PMD_RESETCONTROL_BFD_RSTN |
PMA_PMD_RESETCONTROL_BFD_PD,
0,
gpon_pll_slice_pdi_pmd_resetcontrol );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_pll_module_set ( const enum optic_pll_module
module,
const enum optic_activation
mode )
{
switch (module) {
case OPTIC_PLL_TX:
pma_w32_mask ( PMA_PMD_RESETCONTROL_TX_RSTN,
(mode == OPTIC_ENABLE)?
PMA_PMD_RESETCONTROL_TX_RSTN : 0,
gpon_pll_slice_pdi_pmd_resetcontrol );
break;
case OPTIC_PLL_RX:
pma_w32_mask ( PMA_PMD_RESETCONTROL_RX_RSTN,
(mode == OPTIC_ENABLE)?
PMA_PMD_RESETCONTROL_RX_RSTN : 0,
gpon_pll_slice_pdi_pmd_resetcontrol );
break;
default:
return OPTIC_STATUS_POOR;
}
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_pll_module_get ( const enum optic_pll_module
module,
enum optic_activation *mode )
{
uint32_t reg = pma_r32(gpon_pll_slice_pdi_pmd_resetcontrol);
if (mode == NULL)
return OPTIC_STATUS_ERR;
switch (module) {
case OPTIC_PLL_TX:
*mode = (reg & PMA_PMD_RESETCONTROL_TX_RSTN) ?
OPTIC_ENABLE : OPTIC_DISABLE;
break;
case OPTIC_PLL_RX:
*mode = (reg & PMA_PMD_RESETCONTROL_RX_RSTN) ?
OPTIC_ENABLE : OPTIC_DISABLE;
break;
default:
return OPTIC_STATUS_POOR;
}
return OPTIC_STATUS_OK;
}
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_PLL == ACTIVE))
static enum optic_errorcode optic_ll_pll_dump ( void )
{
uint32_t reg;
reg = pma_r32 ( gpon_pll_slice_pdi_pmd_resetcontrol );
OPTIC_DEBUG_WRN("PLL RESETCONTROL: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl1 );
OPTIC_DEBUG_WRN("PLL CTRL1: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl2 );
OPTIC_DEBUG_WRN("PLL CTRL2: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl3 );
OPTIC_DEBUG_WRN("PLL CTRL3: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl4 );
OPTIC_DEBUG_WRN("PLL CTRL4: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl5 );
OPTIC_DEBUG_WRN("PLL CTRL5: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl6 );
OPTIC_DEBUG_WRN("PLL CTRL6: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_ctrl7 );
OPTIC_DEBUG_WRN("PLL CTRL7: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_a_ctrl1 );
OPTIC_DEBUG_WRN("PLL A_CTRL1: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_a_ctrl2 );
OPTIC_DEBUG_WRN("PLL A_CTRL2: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_a_ctrl3 );
OPTIC_DEBUG_WRN("PLL A_CTRL3: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_status );
OPTIC_DEBUG_WRN("PLL STATUS: 0x%08X", reg);
reg = pma_r32 ( gpon_pll_slice_pdi_pma_top_ctrl );
OPTIC_DEBUG_WRN("PLL TOP_CTRL: 0x%08X", reg);
return OPTIC_STATUS_OK;
}
static enum optic_errorcode optic_ll_pll_dump_status ( void )
{
uint32_t reg;
reg = pma_r32 ( gpon_pll_slice_pdi_status );
OPTIC_DEBUG_WRN("PLL STATUS: 0x%08X", reg);
return OPTIC_STATUS_OK;
}
#endif
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_pll.h
*/
#ifndef _drv_optic_ll_pll_h
#define _drv_optic_ll_pll_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_PLL_INTERNAL PLL Module - Internal
@{
*/
enum optic_pll_module
{
OPTIC_PLL_RX,
OPTIC_PLL_TX,
};
enum optic_errorcode optic_ll_pll_calibrate ( void );
enum optic_errorcode optic_ll_pll_vco_set ( void );
enum optic_errorcode optic_ll_pll_check ( void );
enum optic_errorcode optic_ll_pll_start ( const enum optic_manage_mode mode );
enum optic_errorcode optic_ll_pll_laser_set ( const bool single_ended );
enum optic_errorcode optic_ll_pll_module_set ( const enum optic_pll_module
module,
const enum optic_activation mode );
enum optic_errorcode optic_ll_pll_module_get ( const enum optic_pll_module
module,
enum optic_activation *mode );
enum optic_errorcode optic_ll_pll_rogue (void);
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_rx.h
*/
#ifndef _drv_optic_ll_rx_h
#define _drv_optic_ll_rx_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
#include "drv_optic_common.h"
#include "drv_optic_interface.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_RX_INTERNAL Receiver Module - Internal
@{
*/
#define OPTIC_RX_READ_CYCLES_LOL 8
#define OPTIC_RX_DSM_CTRL_OFFS 0xF1197C
#define OPTIC_RX_ASYN_CNT 20 /* check GTC status in 20*50ms = 1000ms raster */
enum optic_rx_type {
OPTIC_RX_DATA_LOW,
OPTIC_RX_DATA_HIGH,
OPTIC_RX_EDGE_FALL,
OPTIC_RX_EDGE_RISE,
OPTIC_RX_MONITOR,
OPTIC_RX_XTALK,
OPTIC_RX_DFECTRL_OFF
};
enum optic_errorcode optic_ll_rx_cdr_init ( const bool bosa,
const bool dead_zone_elimination );
enum optic_errorcode optic_ll_rx_cdr_bpd ( const enum optic_activation mode );
enum optic_errorcode optic_ll_rx_lolalarm_thresh_set ( const uint8_t limit_low,
const uint8_t
limit_high );
enum optic_errorcode optic_ll_rx_lolalarm_thresh_get ( uint8_t *limit_low,
uint8_t *limit_high );
enum optic_errorcode optic_ll_rx_flipinvert_set ( const enum optic_rx_type type,
const bool flip,
const bool invert );
enum optic_errorcode optic_ll_rx_flipinvert_get ( const enum optic_rx_type type,
bool *flip,
bool *invert );
enum optic_errorcode optic_ll_rx_afectrl_config ( const uint16_t rterm,
const uint8_t emp );
enum optic_errorcode optic_ll_rx_afectrl_set ( const enum optic_activation
mode,
const bool calibration );
enum optic_errorcode optic_ll_rx_dac_set ( const enum optic_rx_type type,
const bool positive,
const uint8_t level_coarse,
const uint8_t level_fine );
enum optic_errorcode optic_ll_rx_dac_get ( const enum optic_rx_type type,
bool *positive,
uint8_t *level_coarse,
uint8_t *level_fine );
enum optic_errorcode optic_ll_rx_dac_sel ( const enum optic_rx_type type );
enum optic_errorcode optic_ll_rx_lol_get ( bool *lol );
enum optic_errorcode optic_ll_rx_offset_cancel ( const enum optic_rx_type type,
int32_t *rx_offset );
enum optic_errorcode optic_ll_rx_dsm_reset (uint8_t lol_set, uint8_t lol_clear);
enum optic_errorcode optic_ll_rx_dsm_switch (const enum optic_activation mode);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_RX == ACTIVE))
enum optic_errorcode optic_ll_rx_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_calc.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_fcsi.h"
#include "drv_optic_reg_base.h"
#include "drv_optic_reg_sys_gpon.h"
#include "drv_optic_reg_status.h"
#include "drv_optic_reg_dcdc.h"
#include "drv_optic_reg_sys1.h"
#include "drv_optic_reg_pma.h"
#include "drv_optic_reg_gtc_pma.h"
#include "drv_optic_reg_pma_int200.h"
#include "drv_optic_reg_pma_intrx.h"
#include "drv_optic_reg_pma_inttx.h"
#include "drv_optic_reg_fcsic.h"
#ifdef OPTIC_SIMULATION
#include "drv_optic_ll_simulator.h"
struct optic_reg_sys_gpon g_sys_gpon;
struct optic_reg_sys_gpon *sys_gpon = &g_sys_gpon;
/*
struct optic_reg_octrlg g_octrlg;
struct optic_reg_octrlg *octrlg = &g_octrlg;
*/
struct optic_reg_status g_status;
struct optic_reg_status *status = &g_status;
struct optic_reg_gtc_pma g_gtc_pma;
struct optic_reg_gtc_pma *gtc_pma = &g_gtc_pma;
struct optic_reg_pma g_pma;
struct optic_reg_pma *pma = &g_pma;
struct optic_reg_fcsic g_fcsic;
struct optic_reg_fcsic *fcsic = &g_fcsic;
struct optic_reg_fcsi g_fcsi;
struct optic_reg_fcsi *fcsi = &g_fcsi;
struct optic_reg_dcdc g_dcdc_apd;
struct optic_reg_dcdc *dcdc_apd = &g_dcdc_apd;
struct optic_reg_dcdc g_dcdc_core;
struct optic_reg_dcdc *dcdc_core = &g_dcdc_core;
struct optic_reg_dcdc g_dcdc_ddr;
struct optic_reg_dcdc *dcdc_ddr = &g_dcdc_ddr;
struct optic_reg_sys1 g_sys1;
struct optic_reg_sys1 *sys1 = &g_sys1;
struct optic_reg_pma_int200 g_pma_int200;
struct optic_reg_pma_int200 *pma_int200 = &g_pma_int200;
struct optic_reg_pma_intrx g_pma_intrx;
struct optic_reg_pma_intrx *pma_intrx = &g_pma_intrx;
struct optic_reg_pma_inttx g_pma_inttx;
struct optic_reg_pma_inttx *pma_inttx = &g_pma_inttx;
int optic_ll_fcsic_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)fcsic + (reg & ~OPTIC_FCSIC_BASE);
*val = *(vuint32_t *) (addr);
/* simulate ready bits */
if (addr == (ulong_t)&fcsic->stat)
*val |= FCSIC_STAT_XR_FRDY |
FCSIC_STAT_XE_FEMP |
FCSIC_STAT_RR_FRDY;
return 0;
}
int optic_ll_fcsic_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)fcsic + (reg & ~OPTIC_FCSIC_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_pma_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)pma + (reg & ~OPTIC_PMA_BASE);
*val = *(vuint32_t *) (addr);
/* simulate pll lock */
if (addr == (ulong_t)&pma->gpon_pll_slice_pdi_status)
*val |= (1 << PMA_STATUS_STARTUP_RDY_OFFSET) |
PMA_STATUS_LOCK;
return 0;
}
int optic_ll_pma_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)pma + (reg & ~OPTIC_PMA_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_sysgpon_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)sys_gpon + (reg & ~OPTIC_SYS_GPON_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_sysgpon_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)sys_gpon + (reg & ~OPTIC_SYS_GPON_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
/*
int optic_ll_octrlg_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)octrlg + (reg & ~OPTIC_OCTRLG_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_octrlg_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)octrlg + (reg & ~OPTIC_OCTRLG_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
*/
int optic_ll_status_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)status + (reg & ~OPTIC_STATUS_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_status_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)status + (reg & ~OPTIC_STATUS_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_gtc_pma_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)gtc_pma + (reg & ~OPTIC_GTC_PMA_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_gtc_pma_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)gtc_pma + (reg & ~OPTIC_GTC_PMA_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_fcsi_simread ( ulong_t reg, uint32_t *val )
{
uint16_t temp;
ulong_t addr = (ulong_t)fcsi + (reg & ~OPTIC_FCSI_BASE)*2;
temp = *(vuint16_t *) (addr);
*val = temp;
return 0;
}
int optic_ll_fcsi_simwrite ( ulong_t reg, uint32_t val )
{
uint16_t temp = (uint16_t) val;
ulong_t addr = (ulong_t)fcsi + (reg & ~OPTIC_FCSI_BASE)*2;
*(vuint16_t *) (addr) = temp;
return 0;
}
int optic_ll_dcdc_apd_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)dcdc_apd + (reg & ~OPTIC_DCDC_APD_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_dcdc_apd_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)dcdc_apd + (reg & ~OPTIC_DCDC_APD_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_dcdc_core_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)dcdc_core + (reg & ~OPTIC_DCDC_CORE_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_dcdc_core_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)dcdc_core + (reg & ~OPTIC_DCDC_CORE_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_dcdc_ddr_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)dcdc_ddr + (reg & ~OPTIC_DCDC_DDR_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_dcdc_ddr_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)dcdc_ddr + (reg & ~OPTIC_DCDC_DDR_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
int optic_ll_sys1_simread ( ulong_t reg, uint32_t *val )
{
ulong_t addr = (ulong_t)sys1 + (reg & ~OPTIC_SYS1_BASE);
*val = *(vuint32_t *) (addr);
return 0;
}
int optic_ll_sys1_simwrite ( ulong_t reg, uint32_t val )
{
ulong_t addr = (ulong_t)sys1 + (reg & ~OPTIC_SYS1_BASE);
*(vuint32_t *) (addr) = val;
return 0;
}
void optic_register_correct ( uint8_t form, void **reg )
{
/* memory address in case of reg_ macro access */
if ((form == 16) &&
(optic_in_range ( *reg, (ulong_t)fcsi, (ulong_t)fcsi +
(OPTIC_FCSI_END - OPTIC_FCSI_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)fcsi +
OPTIC_FCSI_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)fcsic, (ulong_t)fcsic +
(OPTIC_FCSIC_END - OPTIC_FCSIC_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)fcsic +
OPTIC_FCSIC_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)pma, (ulong_t)pma +
(OPTIC_PMA_END - OPTIC_PMA_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)pma + OPTIC_PMA_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)sys_gpon, (ulong_t)sys_gpon +
(OPTIC_SYS_GPON_END - OPTIC_SYS_GPON_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)sys_gpon +
OPTIC_SYS_GPON_BASE);
} else
/*
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)octrlg, (ulong_t)octrlg +
(OPTIC_OCTRLG_END - OPTIC_OCTRLG_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)octrlg +
OPTIC_OCTRLG_BASE);
} else
*/
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)status, (ulong_t)status +
(OPTIC_STATUS_END - OPTIC_STATUS_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)status +
OPTIC_STATUS_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)gtc_pma, (ulong_t)gtc_pma +
(OPTIC_GTC_PMA_END - OPTIC_GTC_PMA_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)gtc_pma +
OPTIC_GTC_PMA_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)dcdc_apd, (ulong_t)dcdc_apd +
(OPTIC_DCDC_APD_END - OPTIC_DCDC_APD_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)dcdc_apd +
OPTIC_DCDC_APD_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)dcdc_core, (ulong_t)dcdc_core +
(OPTIC_DCDC_CORE_END - OPTIC_DCDC_CORE_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)dcdc_core +
OPTIC_DCDC_CORE_BASE);
} else
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)dcdc_ddr, (ulong_t)dcdc_ddr +
(OPTIC_DCDC_DDR_END - OPTIC_DCDC_DDR_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)dcdc_ddr +
OPTIC_DCDC_DDR_BASE);
}
if ((form == 32) &&
(optic_in_range ( *reg, (ulong_t)sys1, (ulong_t)sys1 +
(OPTIC_SYS1_END - OPTIC_SYS1_BASE) ) )) {
*reg = (void*) ((ulong_t)*reg - (ulong_t)sys1 +
OPTIC_SYS1_BASE);
}
}
uint32_t optic_register_read ( uint8_t form, void *reg)
{
uint32_t value = 0;
/* memory address in case of reg_ macro access */
optic_register_correct (form, &reg);
if ((form == 16) &&
(optic_in_range ( reg, OPTIC_FCSI_BASE, OPTIC_FCSI_END ))) {
optic_ll_fcsi_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range(reg, OPTIC_FCSIC_BASE, OPTIC_FCSIC_END ))) {
optic_ll_fcsic_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_PMA_BASE, OPTIC_PMA_END ))) {
optic_ll_pma_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_SYS_GPON_BASE, OPTIC_SYS_GPON_END ))) {
optic_ll_sysgpon_simread((ulong_t)reg, &value);
} else
/*
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_OCTRLG_BASE, OPTIC_OCTRLG_END ))) {
optic_ll_octrlg_simread((ulong_t)reg, &value);
} else
*/
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_STATUS_BASE, OPTIC_STATUS_END ))) {
optic_ll_status_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_GTC_PMA_BASE, OPTIC_GTC_PMA_END ))) {
optic_ll_gtc_pma_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_DCDC_APD_BASE, OPTIC_DCDC_APD_END ))) {
optic_ll_dcdc_apd_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_DCDC_CORE_BASE,
OPTIC_DCDC_CORE_END ))) {
optic_ll_dcdc_core_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_DCDC_DDR_BASE, OPTIC_DCDC_DDR_END ))) {
optic_ll_dcdc_ddr_simread((ulong_t)reg, &value);
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_SYS1_BASE, OPTIC_SYS1_END ))) {
optic_ll_sys1_simread((ulong_t)reg, &value);
} else
OPTIC_DEBUG_ERR ("reg 0x%x read access not supported", reg);
return value;
}
enum optic_errorcode optic_register_write ( uint8_t form,
void *reg,
uint32_t value )
{
enum optic_errorcode ret = OPTIC_STATUS_ERR;
/* memory address in case of reg_ macro access */
optic_register_correct (form, &reg);
if ((form == 16) &&
(optic_in_range ( reg, OPTIC_FCSI_BASE, OPTIC_FCSI_END ))) {
if (optic_ll_fcsi_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_FCSIC_BASE, OPTIC_FCSIC_END ))) {
if (optic_ll_fcsic_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_PMA_BASE, OPTIC_PMA_END ))) {
if (optic_ll_pma_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_SYS_GPON_BASE, OPTIC_SYS_GPON_END ))) {
if (optic_ll_sysgpon_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
/*
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_OCTRLG_BASE, OPTIC_OCTRLG_END ))) {
if (optic_ll_octrlg_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
*/
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_STATUS_BASE, OPTIC_STATUS_END ))) {
if (optic_ll_status_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_GTC_PMA_BASE, OPTIC_GTC_PMA_END ))) {
if (optic_ll_gtc_pma_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_DCDC_APD_BASE, OPTIC_DCDC_APD_END ))) {
if (optic_ll_dcdc_apd_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_DCDC_CORE_BASE,
OPTIC_DCDC_CORE_END ))) {
if (optic_ll_dcdc_core_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_DCDC_DDR_BASE, OPTIC_DCDC_DDR_END ))) {
if (optic_ll_dcdc_ddr_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
if ((form == 32) &&
(optic_in_range ( reg, OPTIC_SYS1_BASE, OPTIC_SYS1_END ))) {
if (optic_ll_sys1_simwrite((ulong_t)reg, value) == 0)
ret = OPTIC_STATUS_OK;
} else
OPTIC_DEBUG_ERR ("reg 0x%x write access not supported", reg);
return ret;
}
void optic_irq_set ( enum optic_manage_mode mode,
enum optic_activation act )
{
(void) mode;
(void) act;
return;
}
void optic_irq_omu_init ( const uint8_t signal_detect_irq )
{
(void) signal_detect_irq;
return;
}
#endif /* OPTIC_SIMULATION */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_ll_simulator_h
#define _drv_optic_ll_simulator_h
/** \defgroup OPTIC_SIMULATOR_INTERNAL Register Simulator Module
@{
*/
extern int optic_ll_pma_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_pma_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_sys_gpon_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_sys_gpon_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_status_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_status_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_gtc_pma_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_gtc_pma_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_fcsi_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_fcsi_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_dcdc_apd_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_dcdc_apd_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_dcdc_core_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_dcdc_core_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_dcdc_ddr_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_dcdc_ddr_simwrite (ulong_t reg, uint32_t val);
extern int optic_ll_dcdc_sys1_simread (ulong_t reg, uint32_t *val);
extern int optic_ll_dcdc_sys1_simwrite (ulong_t reg, uint32_t val);
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, STATUS Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_STATUS_INTERNAL STATUS Module - Internal
@{
*/
#include "drv_optic_ll_status.h"
#include "drv_optic_common.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_status.h"
/**
Read Fusing information from STATUS.ANALOG.
Check how GOI fuse parameters shall be handled
(for each parameter, store in HW registers and/or use as SW parameters)
If no valid fuse values are stored in the device, default values shall be used.
If all fuse values are equal to 0000 of FFFF, unfused state is assumed.
OPTIC_DEFAULT_FUSE_VCALMM20 = 32
OPTIC_DEFAULT_FUSE_VCALMM100 = 32
OPTIC_DEFAULT_FUSE_VCALMM400 = 32
OPTIC_DEFAULT_FUSE_RCALMM = 128
OPTIC_DEFAULT_FUSE_DCDC_APD_OFFSET = 32
OPTIC_DEFAULT_FUSE_DCDC_APD_GAIN = 32
\return
- OPTIC_STATUS_OK - no errors,
- OPTIC_STATUS_ERR - error occurs
*/
enum optic_errorcode optic_ll_status_fuses_get ( struct optic_fuses *fuses )
{
uint32_t reg;
uint8_t temp;
int8_t itemp;
reg = status_r32(fuse0);
if (reg != 0) {
fuses->vcal_mm20 = (reg & STATUS_FUSE0_VCALMM20_MASK)
>> STATUS_FUSE0_VCALMM20_OFFSET;
fuses->vcal_mm100 = (reg & STATUS_FUSE0_VCALMM100_MASK)
>> STATUS_FUSE0_VCALMM100_OFFSET;
fuses->vcal_mm400 = (reg & STATUS_FUSE0_VCALMM400_MASK)
>> STATUS_FUSE0_VCALMM400_OFFSET;
fuses->rcal_mm = (reg & STATUS_FUSE0_RCALMM_MASK)
>> STATUS_FUSE0_RCALMM_OFFSET;
} else {
fuses->vcal_mm20 = OPTIC_DEFAULT_FUSE_VCALMM20;
fuses->vcal_mm100 = OPTIC_DEFAULT_FUSE_VCALMM100;
fuses->vcal_mm400 = OPTIC_DEFAULT_FUSE_VCALMM400;
fuses->rcal_mm = OPTIC_DEFAULT_FUSE_RCALMM;
}
reg = status_r32(analog);
if (reg != 0) {
/* differ between old and new fuse format: A0 = 1
means new format */
fuses->format = ((reg & STATUS_ANALOG_FS_MASK) >>
STATUS_ANALOG_FS_OFFSET);
if (fuses->format == 1) {
fuses->temp_mm = (reg & STATUS_ANALOG_NEW_TEMPMM_MASK)
>> STATUS_ANALOG_NEW_TEMPMM_OFFSET;
fuses->tbgp = (reg & STATUS_ANALOG_NEW_TBGP_MASK)
>> STATUS_ANALOG_NEW_TBGP_OFFSET;
fuses->vbgp = (reg & STATUS_ANALOG_VBGP_MASK)
>> STATUS_ANALOG_VBGP_OFFSET;
fuses->irefbgp = (reg & STATUS_ANALOG_IREFBGP_MASK)
>> STATUS_ANALOG_IREFBGP_OFFSET;
fuses->gain_dac_drive = (reg &
STATUS_ANALOG_NEW_GAINDRIVEDAC_MASK) >>
STATUS_ANALOG_NEW_GAINDRIVEDAC_OFFSET;
fuses->gain_dac_bias = (reg &
STATUS_ANALOG_NEW_GAINBIASDAC_MASK) >>
STATUS_ANALOG_NEW_GAINBIASDAC_OFFSET;
} else {
fuses->temp_mm = (reg & STATUS_ANALOG_TEMPMM_MASK)
>> STATUS_ANALOG_TEMPMM_OFFSET;
fuses->tbgp = (reg & STATUS_ANALOG_TBGP_MASK)
>> STATUS_ANALOG_TBGP_OFFSET;
fuses->vbgp = (reg & STATUS_ANALOG_VBGP_MASK)
>> STATUS_ANALOG_VBGP_OFFSET;
fuses->irefbgp = (reg & STATUS_ANALOG_IREFBGP_MASK)
>> STATUS_ANALOG_IREFBGP_OFFSET;
fuses->gain_dac_drive = (reg &
STATUS_ANALOG_GAINDRIVEDAC_MASK) >>
STATUS_ANALOG_GAINDRIVEDAC_OFFSET;
fuses->gain_dac_bias = (reg &
STATUS_ANALOG_GAINBIASDAC_MASK) >>
STATUS_ANALOG_GAINBIASDAC_OFFSET;
}
} else {
fuses->temp_mm = OPTIC_DEFAULT_FUSE_TEMPMM;
fuses->tbgp = OPTIC_DEFAULT_FUSE_TBGP;
fuses->vbgp = OPTIC_DEFAULT_FUSE_VBGP;
fuses->irefbgp = OPTIC_DEFAULT_FUSE_IREFBGP;
if(is_falcon_chip_a2x()) {
fuses->gain_dac_drive = OPTIC_DEFAULT_FUSE_GAINDRIVEDAC_A22;
fuses->gain_dac_bias = OPTIC_DEFAULT_FUSE_GAINBIASDAC_A22;
}
else {
fuses->gain_dac_drive = OPTIC_DEFAULT_FUSE_GAINDRIVEDAC;
fuses->gain_dac_bias = OPTIC_DEFAULT_FUSE_GAINBIASDAC;
}
}
reg = status_r32(fuse1);
if (reg != 0) {
if (fuses->format == 1) {
fuses->offset_dcdc_ddr =
OPTIC_DEFAULT_FUSE_DCDC_DDR_OFFSET;
fuses->gain_dcdc_ddr =
OPTIC_DEFAULT_FUSE_DCDC_DDR_GAIN;
temp = (reg & STATUS_FUSE1_OFFSET1V0DCDC_MASK) >>
STATUS_FUSE1_OFFSET1V0DCDC_OFFSET;
/* 2-complement */
temp = (temp << 3);
itemp = (int8_t) temp;
fuses->offset_dcdc_core = itemp / 8;
/*
fuses->gain_dcdc_core = (reg &
STATUS_FUSE1_GAIN1V0DCDC_MASK) >>
STATUS_FUSE1_GAIN1V0DCDC_OFFSET;
*/
fuses->gain_dcdc_core =
OPTIC_DEFAULT_FUSE_DCDC_1V0_GAIN;
temp = (reg & STATUS_FUSE1_OFFSETAPDDCDC_NEW_MASK) >>
STATUS_FUSE1_OFFSETAPDDCDC_OFFSET;
/* 2-complement */
temp = (temp << 3);
itemp = (int8_t) temp;
fuses->offset_dcdc_apd = itemp / 8;
} else {
fuses->offset_dcdc_ddr = (reg &
STATUS_FUSE1_OFFSETDDRDCDC_MASK) >>
STATUS_FUSE1_OFFSETDDRDCDC_OFFSET;
fuses->gain_dcdc_ddr = (reg &
STATUS_FUSE1_GAINDDRDCDC_MASK) >>
STATUS_FUSE1_GAINDDRDCDC_OFFSET;
fuses->offset_dcdc_core =
OPTIC_DEFAULT_FUSE_DCDC_1V0_OFFSET;
fuses->gain_dcdc_core =
OPTIC_DEFAULT_FUSE_DCDC_1V0_GAIN;
fuses->offset_dcdc_apd = (reg &
STATUS_FUSE1_OFFSETAPDDCDC_MASK) >>
STATUS_FUSE1_OFFSETAPDDCDC_OFFSET;
}
fuses->gain_dcdc_apd = (reg &
STATUS_FUSE1_GAINAPDDCDC_MASK) >>
STATUS_FUSE1_GAINAPDDCDC_OFFSET;
} else {
fuses->offset_dcdc_ddr = OPTIC_DEFAULT_FUSE_DCDC_DDR_OFFSET;
fuses->gain_dcdc_ddr = OPTIC_DEFAULT_FUSE_DCDC_DDR_GAIN;
fuses->offset_dcdc_core = OPTIC_DEFAULT_FUSE_DCDC_1V0_OFFSET;
fuses->gain_dcdc_core = OPTIC_DEFAULT_FUSE_DCDC_1V0_GAIN;
fuses->offset_dcdc_apd = OPTIC_DEFAULT_FUSE_DCDC_APD_OFFSET;
fuses->gain_dcdc_apd = OPTIC_DEFAULT_FUSE_DCDC_APD_GAIN;
}
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_status_chip_get ( enum optic_chip *chip )
{
uint32_t reg;
uint16_t ver;
enum optic_errorcode ret = OPTIC_STATUS_OK;
if (chip == NULL)
return OPTIC_STATUS_ERR;
reg = status_r32(config);
ver = 0xA00 + ((((reg & STATUS_CONFIG_SUBVERS_MASK) >>
STATUS_CONFIG_SUBVERS_OFFSET) >> 2) << 8);
ver |= ((((reg & STATUS_CONFIG_SUBVERS_MASK) >>
STATUS_CONFIG_SUBVERS_OFFSET) & 3) + 1);
reg = status_r32(chipid);
ver |= (((reg & STATUS_CHIPID_VERSION_MASK) >>
STATUS_CHIPID_VERSION_OFFSET) << 4);
switch (ver) {
#ifdef CONFIG_WITH_FALCON_A1X
case 0xA11:
*chip = OPTIC_CHIP_A11;
break;
case 0xA12:
*chip = OPTIC_CHIP_A12;
break;
#endif
#ifdef CONFIG_WITH_FALCON_A2X
case 0xA21:
case 0xA22:
case 0xA23:
*chip = OPTIC_CHIP_A21;
break;
#endif
default:
*chip = OPTIC_CHIP_UNKNOWN;
ret = OPTIC_STATUS_ERR;
break;
}
return ret;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_status.h
*/
#ifndef _drv_optic_ll_status_h
#define _drv_optic_ll_status_h
#ifndef SYSTEM_SIMULATION
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#else
#include "drv_optic_simu.h"
#endif
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_STATUS_INTERNAL STATUS Module - Internal
@{
*/
#define OPTIC_DEFAULT_FUSE_VCALMM20 32
#define OPTIC_DEFAULT_FUSE_VCALMM100 32
#define OPTIC_DEFAULT_FUSE_VCALMM400 32
#define OPTIC_DEFAULT_FUSE_RCALMM 128
#define OPTIC_DEFAULT_FUSE_TEMPMM 0
#define OPTIC_DEFAULT_FUSE_TBGP 4
#define OPTIC_DEFAULT_FUSE_VBGP 4
#define OPTIC_DEFAULT_FUSE_IREFBGP 8
#define OPTIC_DEFAULT_FUSE_GAINDRIVEDAC 8
#define OPTIC_DEFAULT_FUSE_GAINBIASDAC 8
#define OPTIC_DEFAULT_FUSE_GAINDRIVEDAC_A22 16
#define OPTIC_DEFAULT_FUSE_GAINBIASDAC_A22 16
#define OPTIC_DEFAULT_FUSE_DCDC_DDR_OFFSET 0
#define OPTIC_DEFAULT_FUSE_DCDC_DDR_GAIN 32
#define OPTIC_DEFAULT_FUSE_DCDC_1V0_OFFSET 0
#define OPTIC_DEFAULT_FUSE_DCDC_1V0_GAIN 32
#define OPTIC_DEFAULT_FUSE_DCDC_APD_OFFSET 0
#define OPTIC_DEFAULT_FUSE_DCDC_APD_GAIN 32
enum optic_errorcode optic_ll_status_fuses_get ( struct optic_fuses *fuses );
enum optic_errorcode optic_ll_status_chip_get ( enum optic_chip *chip );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, SYS1 Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_SYS1_INTERNAL SYS1 Module - Internal
@{
*/
#include "drv_optic_ll_sys1.h"
#include "drv_optic_common.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_sys1.h"
enum optic_errorcode optic_ll_sys1_ldo_set ( const enum optic_activation mode )
{
/* init ldo configuration: 1,5 V */
if (mode == OPTIC_ENABLE) {
sys1_w32_mask ( INFRAC_LIN1V5C_MASK,
((0x03 << INFRAC_LIN1V5C_OFFSET) &
INFRAC_LIN1V5C_MASK),
infrac );
}
sys1_w32_mask ( INFRAC_LIN1V5EN, (mode == OPTIC_ENABLE)?
INFRAC_LIN1V5EN_EN : INFRAC_LIN1V5EN_DIS,
infrac );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_sys1_ldo_get ( enum optic_activation *mode )
{
uint32_t reg;
if (mode == NULL)
return OPTIC_STATUS_ERR;
reg = sys1_r32 ( infrac );
if ((reg & INFRAC_LIN1V5EN) == INFRAC_LIN1V5EN_EN)
*mode = OPTIC_ENABLE;
else
*mode = OPTIC_DISABLE;
return OPTIC_STATUS_OK;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_sys1.h
*/
#ifndef _drv_optic_ll_sys1_h
#define _drv_optic_ll_sys1_h
#include "drv_optic_api.h"
#include "drv_optic_common.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_SYS1_INTERNAL SYS1 Module - Internal
@{
*/
enum optic_errorcode optic_ll_sys1_ldo_set ( const enum optic_activation mode );
enum optic_errorcode optic_ll_sys1_ldo_get ( enum optic_activation *mode );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, SYS_GPON Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_SYS_GPON_INTERNAL SYS_GPON Module - Internal
@{
*/
#include "drv_optic_ll_sys_gpon.h"
#include "drv_optic_common.h"
#include "drv_optic_register.h"
#include "drv_optic_reg_sys_gpon.h"
#if defined(LINUX) && defined(__KERNEL__)
#include <falcon/sysctrl.h>
#endif
/**
Activate Clocks.
\return
- OPTIC_STATUS_OK - no errors,
- OPTIC_STATUS_ERR - error occurs
*/
enum optic_errorcode optic_ll_sys_gpon_clockenable ( void )
{
uint32_t reg = 0;
reg = SYS_GPON_CLKEN_PMATX_SET | SYS_GPON_CLKEN_TOD_SET |
SYS_GPON_CLKEN_GPEIF_SET | SYS_GPON_CLKEN_GTCRXPDI_SET |
SYS_GPON_CLKEN_GTCRX_SET | SYS_GPON_CLKEN_GTCTXPDI_SET |
SYS_GPON_CLKEN_GTCTX_SET;
sys_gpon_w32(reg, clken);
reg = SYS_GPON_ACT_PMATX_SET | SYS_GPON_ACT_TOD_SET |
SYS_GPON_ACT_GPEIF_SET | SYS_GPON_ACT_GTCRXPDI_SET |
SYS_GPON_ACT_GTCRX_SET | SYS_GPON_ACT_GTCTXPDI_SET |
SYS_GPON_ACT_GTCTX_SET;
sys_gpon_w32(reg, act);
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP == ACTIVE))
optic_ll_sys_gpon_dump ();
#endif
/* GPE clocks needed */
#if defined(LINUX) && defined(__KERNEL__)
sys_gpe_hw_activate (0);
#endif
return OPTIC_STATUS_OK;
}
/**
Deactivate Clocks.
\return
- OPTIC_STATUS_OK - no errors,
- OPTIC_STATUS_ERR - error occurs
*/
enum optic_errorcode optic_ll_sys_gpon_clockdisable ( void )
{
uint32_t reg = 0;
reg = SYS_GPON_ACT_PMATX_SET;
sys_gpon_w32(reg, rbt);
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_sys_gpon_dump ( void )
{
uint32_t reg;
reg = sys_gpon_r32(clks);
OPTIC_DEBUG_WRN("SYS GPON CLKS: 0x%08X", reg);
reg = sys_gpon_r32(acts);
OPTIC_DEBUG_WRN("SYS GPON ACTS: 0x%08X", reg);
return OPTIC_STATUS_OK;
}
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_sys_gpon.h
*/
#ifndef _drv_optic_ll_sys_gpon_h
#define _drv_optic_ll_sys_gpon_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_SYS_GPON_INTERNAL SYS_GPON Module - Internal
@{
*/
enum optic_errorcode optic_ll_sys_gpon_clockenable ( void );
enum optic_errorcode optic_ll_sys_gpon_clockdisable ( void );
enum optic_errorcode optic_ll_sys_gpon_dump ( void );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2010
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, PMA TX Module - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_TX_INTERNAL Transmit Module - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_register.h"
#include "drv_optic_ll_rx.h"
#include "drv_optic_ll_tx.h"
#include "drv_optic_reg_pma.h"
/**
Initialize data/bias path in transmit direction.
\param mode Optical interface operation mode
\param bias_invert enable or disable inverting of data on bias
\param mod_invert enable or disable inverting of data on modulation
\return
- OPTIC_STATUS_OK - success,
*/
enum optic_errorcode optic_ll_tx_path_init (const enum optic_manage_mode mode,
const bool bias_invert, const bool mod_invert)
{
uint32_t reg;
/* bias path: flip, invert=bias_polarity (1=invert),
no burst, power from GTC */
reg = pma_r32 (gpon_tx_slice_pdi_biaspath);
reg &= ~(PMA_BIASPATH_BIAS_INV |
PMA_BIASPATH_POWER_UP_OVR |
PMA_BIASPATH_BURST_VALID_PRG_EN |
PMA_BIASPATH_BIAS_PRG_EN |
PMA_BIASPATH_BIAS_PRG_DATA_MASK);
reg |= PMA_BIASPATH_BIAS_FLIP;
if (bias_invert == true)
reg |= PMA_BIASPATH_BIAS_INV;
pma_w32 (reg, gpon_tx_slice_pdi_biaspath);
/* data path: flip, invert=mod_polarity (1=invert),
no burst, power from GTC */
reg = pma_r32 (gpon_tx_slice_pdi_datapath);
reg &= ~(PMA_DATAPATH_DATA_INV |
PMA_DATAPATH_BURST_VALID_PRG_EN |
PMA_DATAPATH_POWER_UP_OVR |
PMA_DATAPATH_DATA_PRG_EN |
PMA_DATAPATH_DATA_PRG_DATA_MASK);
reg |= PMA_DATAPATH_DATA_FLIP;
/* do not invert for BOSA */
if ((mod_invert == true && mode == OPTIC_OMU) ||
(mod_invert == false && mode == OPTIC_BOSA))
reg |= PMA_DATAPATH_DATA_INV;
pma_w32 ( reg, gpon_tx_slice_pdi_datapath);
/* bias path sending to BERT enabled/disabled */
pma_w32_mask (PMA_BIASPATH_BERT, 0, gpon_tx_slice_pdi_biaspath);
return OPTIC_STATUS_OK;
}
/**
Configure data/bias path in transmit direction.
\param type BIAS or MODULATION (data) path
\param burst enable or disable burst valid mode
\param power_up enable or disable power up
\param flip enable or disable flipping of LSB and MSB
\param invert enable or disable inverting of data
*/
void optic_ll_tx_path_activate (const enum optic_current_type type,
const bool invert)
{
uint32_t reg;
switch (type) {
case OPTIC_BIAS:
/* set bias path ctrl */
reg = pma_r32 (gpon_tx_slice_pdi_biaspath);
if (invert == true)
reg |= PMA_BIASPATH_BIAS_INV;
else
reg &= ~PMA_BIASPATH_BIAS_INV;
reg |= PMA_BIASPATH_BURST_VALID_PRG_EN |
PMA_BIASPATH_POWER_UP_OVR;
pma_w32 ( reg, gpon_tx_slice_pdi_biaspath);
break;
case OPTIC_MOD:
/* set data path ctrl */
reg = pma_r32 (gpon_tx_slice_pdi_datapath);
if (invert == true)
reg |= PMA_DATAPATH_DATA_INV;
else
reg &= ~PMA_DATAPATH_DATA_INV;
reg |= PMA_DATAPATH_BURST_VALID_PRG_EN |
PMA_DATAPATH_POWER_UP_OVR;
pma_w32 ( reg, gpon_tx_slice_pdi_datapath);
break;
}
}
/**
Configure bias path data.
\param activate - set to true to activate otherwise false
\param data - data to send
*/
void optic_ll_tx_biaspath_data_set (const uint8_t data)
{
uint32_t reg;
/* set bias path ctrl */
reg = pma_r32 (gpon_tx_slice_pdi_biaspath);
reg &= ~(PMA_BIASPATH_BIAS_PRG_EN |
PMA_BIASPATH_BIAS_PRG_DATA_MASK);
reg |= ((data << PMA_BIASPATH_BIAS_PRG_DATA_OFFSET) &
PMA_BIASPATH_BIAS_PRG_DATA_MASK) |
PMA_BIASPATH_BIAS_PRG_EN;
pma_w32 (reg, gpon_tx_slice_pdi_biaspath);
}
/**
Configure data bert sending.
\param bert_data data path sending to BERT enabled/disabled
\return
- OPTIC_STATUS_OK - success,
*/
enum optic_errorcode optic_ll_tx_path_bert_set (const enum optic_activation
bert_data)
{
pma_w32_mask ( PMA_DATAPATH_BERT, (bert_data == OPTIC_ENABLE) ?
PMA_DATAPATH_BERT : 0, gpon_tx_slice_pdi_datapath );
return OPTIC_STATUS_OK;
}
/**
Configure TX Fifo.
\param dalay_enable TX fifo start configuration (in bits)
\param delay_disable TX fifo stop configuration (in bits)
\param size_fifo TX fifo size configuration (in bits)
Configure Tx start/stop offset values for Tx FIFO, from goi config file
Values given in number of bit, programming in number of nibbles.
tmp = (
ELEM_GPON_TX_SLICE_PDI_LASER_ENABLE_ENABLE_DELAY(delay_tx_enable/4)|
ELEM_GPON_TX_SLICE_PDI_LASER_ENABLE_DISABLE_DELAY(delay_tx_disable/4)|
ELEM_GPON_TX_SLICE_PDI_LASER_ENABLE_BUFFER_SIZE(nTxEnableFifoSize/4));
io_write(ADR_GPON_TX_SLICE_PDI_LASER_ENABLE, tmp);
\return
- OPTIC_STATUS_OK - success,
*/
enum optic_errorcode optic_ll_tx_fifo_set ( const int16_t delay_enable,
const uint16_t delay_disable,
const uint16_t size_fifo )
{
uint32_t reg;
uint8_t delay_enable_nibble = ((abs(delay_enable) + 2) >> 2);
uint8_t delay_disable_nibble = ((delay_disable + 2) >> 2);
uint16_t size_fifo_nibble = ((size_fifo + 2) >> 2);
if(is_falcon_chip_a2x()) {
reg = ((size_fifo_nibble << PMA_LASER_ENABLE_BUFFER_SIZE_OFFSET) &
PMA_LASER_ENABLE_BUFFER_SIZE_MASK_A21) |
((delay_disable_nibble << PMA_LASER_ENABLE_DISABLE_DELAY_OFFSET) &
PMA_LASER_ENABLE_DISABLE_DELAY_MASK) |
((delay_enable_nibble << PMA_LASER_ENABLE_ENABLE_DELAY_OFFSET) &
PMA_LASER_ENABLE_ENABLE_DELAY_MASK);
if(delay_enable < 0)
reg |= (1 << PMA_LASER_ENABLE_NEG_ENABLE_DELAY_OFFSET_A21);
} else {
reg = ((size_fifo_nibble << PMA_LASER_ENABLE_BUFFER_SIZE_OFFSET) &
PMA_LASER_ENABLE_BUFFER_SIZE_MASK) |
((delay_disable_nibble << PMA_LASER_ENABLE_DISABLE_DELAY_OFFSET) &
PMA_LASER_ENABLE_DISABLE_DELAY_MASK) |
((delay_enable_nibble << PMA_LASER_ENABLE_ENABLE_DELAY_OFFSET) &
PMA_LASER_ENABLE_ENABLE_DELAY_MASK);
}
pma_w32 ( reg, gpon_tx_slice_pdi_laser_enable );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_tx_fifo_get ( int16_t *delay_enable,
uint16_t *delay_disable,
uint16_t *size_fifo )
{
uint32_t reg;
int16_t delay_enable_nibble;
uint8_t delay_disable_nibble;
uint16_t size_fifo_nibble;
reg = pma_r32 ( gpon_tx_slice_pdi_laser_enable );
if(is_falcon_chip_a2x())
size_fifo_nibble = (reg & PMA_LASER_ENABLE_BUFFER_SIZE_MASK_A21) >>
PMA_LASER_ENABLE_BUFFER_SIZE_OFFSET;
else
size_fifo_nibble = (reg & PMA_LASER_ENABLE_BUFFER_SIZE_MASK) >>
PMA_LASER_ENABLE_BUFFER_SIZE_OFFSET;
delay_disable_nibble = (reg & PMA_LASER_ENABLE_DISABLE_DELAY_MASK) >>
PMA_LASER_ENABLE_DISABLE_DELAY_OFFSET;
delay_enable_nibble = (reg & PMA_LASER_ENABLE_ENABLE_DELAY_MASK) >>
PMA_LASER_ENABLE_ENABLE_DELAY_OFFSET;
if(is_falcon_chip_a2x()) {
if ((reg & PMA_LASER_ENABLE_NEG_ENABLE_DELAY_MASK_A21)
>> PMA_LASER_ENABLE_NEG_ENABLE_DELAY_OFFSET_A21 )
delay_enable_nibble = -delay_enable_nibble;
}
if (delay_enable)
*delay_enable = delay_enable_nibble * 4;
if (delay_disable)
*delay_disable = delay_disable_nibble * 4;
if (size_fifo)
*size_fifo = size_fifo_nibble * 4;
return OPTIC_STATUS_OK;
}
void optic_ll_tx_pi_set ( const uint32_t pi_ctrl )
{
bool enable;
pma_w32 ( pi_ctrl, gpon_tx_slice_pdi_pi_ctrl );
enable = ((pi_ctrl & PMA_PI_CTRL_PI_EN) == PMA_PI_CTRL_PI_EN) ?
true : false;
pma_w32_mask ( PMA_MODULATOR_1_MOD_EN,
(enable)? PMA_MODULATOR_1_MOD_EN : 0,
gpon_tx_slice_pdi_modulator_1);
}
void optic_ll_tx_delay_set ( const uint8_t data_delay,
const uint8_t intrinsic_delay )
{
uint32_t reg;
/* configure data delay */
reg = ((data_delay << PMA_DATA_DELAY_DATA_DELAY_OFFSET) &
PMA_DATA_DELAY_DATA_DELAY_MASK) |
((intrinsic_delay << PMA_DATA_DELAY_INTRINSIC_DELAY_OFFSET) &
PMA_DATA_DELAY_INTRINSIC_DELAY_MASK);
pma_w32 ( reg, gpon_tx_slice_pdi_data_delay );
}
void optic_ll_tx_powersave_set ( const enum optic_activation
powersave )
{
if (powersave == OPTIC_ENABLE)
pma_w32_mask ( 0, PMA_DATA_DELAY_EN_PMD_TX_PD,
gpon_tx_slice_pdi_data_delay );
else
pma_w32_mask ( PMA_DATA_DELAY_EN_PMD_TX_PD, 0,
gpon_tx_slice_pdi_data_delay );
}
#ifdef CONFIG_WITH_FALCON_A2X
enum optic_errorcode optic_ll_tx_pd_latchoverride_set (
const enum optic_activation override )
{
if (override == OPTIC_ENABLE)
pma_w32_mask ( 0, PMA_DATA_DELAY_EN_PMD_TX_PD_LATCHOR_MASK_A21,
gpon_tx_slice_pdi_data_delay );
else
pma_w32_mask ( PMA_DATA_DELAY_EN_PMD_TX_PD_LATCHOR_MASK_A21, 0,
gpon_tx_slice_pdi_data_delay );
return OPTIC_STATUS_OK;
}
#endif
enum optic_errorcode optic_ll_tx_laserdelay_set ( const uint8_t bitdelay )
{
uint32_t reg = bitdelay;
if (bitdelay > 0x7)
return OPTIC_STATUS_POOR;
pma_w32 ( reg, gpon_tx_slice_pdi_laser_bitdelay );
return OPTIC_STATUS_OK;
}
enum optic_errorcode optic_ll_tx_laserdelay_get ( uint8_t *bitdelay )
{
if (bitdelay)
*bitdelay = (uint8_t) pma_r32(gpon_tx_slice_pdi_laser_bitdelay);
return OPTIC_STATUS_OK;
}
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_TX == ACTIVE))
enum optic_errorcode optic_ll_tx_dump ( void )
{
OPTIC_DEBUG_WRN("TX DATAPATH: 0x%08X",
pma_r32(gpon_tx_slice_pdi_datapath));
OPTIC_DEBUG_WRN("TX BIASPATH: 0x%08X",
pma_r32(gpon_tx_slice_pdi_biaspath));
OPTIC_DEBUG_WRN("TX DATA_DELAY: 0x%08X",
pma_r32(gpon_tx_slice_pdi_data_delay));
OPTIC_DEBUG_WRN("TX LASER_ENABLE: 0x%08X",
pma_r32(gpon_tx_slice_pdi_laser_enable));
OPTIC_DEBUG_WRN("TX LASER_BITDELAY: 0x%08X",
pma_r32(gpon_tx_slice_pdi_laser_bitdelay));
OPTIC_DEBUG_WRN("TX PI_CTRL: 0x%08X",
pma_r32(gpon_tx_slice_pdi_pi_ctrl));
OPTIC_DEBUG_WRN("TX MODULATOR_1: 0x%08X",
pma_r32(gpon_tx_slice_pdi_modulator_1));
OPTIC_DEBUG_WRN("TX MODULATOR_2: 0x%08X",
pma_r32(gpon_tx_slice_pdi_modulator_2));
return OPTIC_STATUS_OK;
}
#endif
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_ll_tx.h
*/
#ifndef _drv_optic_ll_tx_h
#define _drv_optic_ll_tx_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_TX_INTERNAL Transmit Module - Internal
@{
*/
enum optic_errorcode optic_ll_tx_path_init (const enum optic_manage_mode mode,
const bool bias_invert, const bool polarity_invert);
void optic_ll_tx_path_activate (const enum optic_current_type
type, const bool invert);
void optic_ll_tx_biaspath_data_set (const uint8_t data);
enum optic_errorcode optic_ll_tx_path_bert_set (const enum optic_activation
bert_data );
enum optic_errorcode optic_ll_tx_fifo_set ( const int16_t delay_enable,
const uint16_t delay_disable,
const uint16_t size_fifo );
enum optic_errorcode optic_ll_tx_fifo_get ( int16_t *delay_enable,
uint16_t *delay_disable,
uint16_t *size_fifo );
void optic_ll_tx_pi_set (const uint32_t pi_ctrl);
void optic_ll_tx_delay_set (const uint8_t data_delay,
const uint8_t intrinsic_delay );
void optic_ll_tx_powersave_set (const enum optic_activation powerdown);
#ifdef CONFIG_WITH_FALCON_A2X
enum optic_errorcode optic_ll_tx_pd_latchoverride_set (
const enum optic_activation override );
#endif
enum optic_errorcode optic_ll_tx_laserdelay_set ( const uint8_t bitdelay );
enum optic_errorcode optic_ll_tx_laserdelay_get ( uint8_t *bitdelay );
#if ((OPTIC_DEBUG == ACTIVE) && (OPTIC_DEBUG_PRINTOUT_DUMP_TX == ACTIVE))
enum optic_errorcode optic_ll_tx_dump ( void );
#endif
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_mm.h
*/
#ifndef _drv_optic_mm_h
#define _drv_optic_mm_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_MM_INTERNAL MM Module - Internal
@{
*/
enum optic_errorcode optic_mm_init ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mm_control ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mm_calibrate ( struct optic_control *p_ctrl,
uint8_t gain_selector );
enum optic_errorcode optic_mm_temp_int_get ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mm_temp_ext_get ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mm_power_get ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mm_thresh_calc ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mm_thresh_set ( struct optic_control *p_ctrl );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/**
\file drv_optic_mpd.h
*/
#ifndef _drv_optic_mpd_h
#define _drv_optic_mpd_h
#include "drv_optic_std_defs.h"
#include "drv_optic_error.h"
EXTERN_C_BEGIN
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \addtogroup OPTIC_MPD_INTERNAL MPD Module - Internal
@{
*/
enum optic_errorcode optic_mpd_init ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mpd_level_search ( struct optic_control *p_ctrl,
const enum optic_search_type
type,
int16_t *level ,int16_t *level_c );
enum optic_errorcode optic_mpd_offset_cancel ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mpd_ratio_measure ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mpd_calibrate_level ( struct optic_control *p_ctrl,
const bool offset_cancel,
const bool calibrate[2],
int16_t dac_coarse[2],
int16_t dac_fine[2] );
enum optic_errorcode optic_mpd_dac_level_search ( struct optic_control *p_ctrl,
const bool offset_calibration,
const uint8_t type_coarse,
const uint8_t type_fine,
int16_t *dac_coarse,
int16_t *dac_fine );
enum optic_errorcode optic_mpd_codeword_calc ( struct optic_control *p_ctrl,
const bool calibrate[2],
const bool offset_cancellation,
const int16_t dac_coarse[2],
const int16_t dac_fine[2] );
enum optic_errorcode optic_mpd_codeword_set ( struct optic_control *p_ctrl,
bool p0 );
enum optic_errorcode optic_mpd_biasmod_average ( struct optic_control *p_ctrl,
const enum optic_current_type
type );
enum optic_errorcode optic_mpd_regulation_get ( struct optic_control *p_ctrl,
const enum optic_current_type type,
bool *update,
uint16_t *average,
bool *reset_bias_low);
enum optic_errorcode optic_mpd_stable_get ( struct optic_control *p_ctrl,
const enum optic_current_type type,
const uint16_t average,
bool *reset);
enum optic_errorcode optic_mpd_biasmod_update ( struct optic_control *p_ctrl,
const enum optic_current_type
type );
enum optic_errorcode optic_mpd_p0_correct ( struct optic_control *p_ctrl);
enum optic_errorcode optic_mpd_biasmod_learn ( struct optic_control *p_ctrl,
const enum optic_current_type
type,
bool *learn );
void optic_mpd_biasmod_max_set ( uint8_t *bias_max, uint8_t *mod_max );
enum optic_errorcode optic_mpd_saturation_set ( struct optic_control *p_ctrl,
const uint16_t bias_sat,
const uint16_t mod_sat );
enum optic_errorcode optic_mpd_bias_set ( struct optic_control *p_ctrl,
const uint16_t ibias );
enum optic_errorcode optic_mpd_biaslowsat_set ( struct optic_control *p_ctrl,
const uint16_t ibias );
enum optic_errorcode optic_mpd_bias_get ( struct optic_control *p_ctrl,
const bool init,
uint16_t *bias );
enum optic_errorcode optic_mpd_mod_set ( struct optic_control *p_ctrl,
const uint16_t imod );
enum optic_errorcode optic_mpd_mod_get ( struct optic_control *p_ctrl,
const bool init,
uint16_t *mod );
enum optic_errorcode optic_mpd_cint_set ( struct optic_control *p_ctrl,
const enum optic_current_type type,
const uint8_t intcoeff );
enum optic_errorcode optic_mpd_loopmode ( struct optic_control *p_ctrl );
enum optic_errorcode optic_mpd_gainctrl_set ( struct optic_control *p_ctrl,
const enum optic_gainbank
gainbank,
const enum optic_cal_current
cal_current );
enum optic_errorcode optic_mpd_tia_offset_set ( struct optic_control *p_ctrl,
const enum optic_gainbank
gainbank );
/*! @} */
/*! @} */
EXTERN_C_END
#endif

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
/** \file
Device Driver, OMU Interface - Implementation
*/
/** \addtogroup MAPI_REFERENCE_GOI_INTERNAL Optical Interface API Reference - Internal
@{
*/
/** \defgroup OPTIC_OMU_INTERNAL OMU Interface - Internal
@{
*/
#include "drv_optic_api.h"
#include "drv_optic_common.h"
#include "drv_optic_omu_interface.h"
#include "drv_optic_rx.h"
#include "drv_optic_tx.h"
#include "drv_optic_ll_bert.h"
#include "drv_optic_ll_pll.h"
#include "drv_optic_ll_tx.h"
#include "drv_optic_ll_rx.h"
#include "drv_optic_ll_mpd.h"
#include "drv_optic_ll_gpio.h"
#include "drv_optic_ll_int.h"
#include "drv_optic_ll_dcdc_apd.h"
/**
The omu_cfg_set function is used to provide configurations for the
receive path of the optical module (OMU).
*/
enum optic_errorcode omu_cfg_set ( struct optic_device *p_dev,
const struct optic_omu_config *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
if (param == NULL)
return OPTIC_STATUS_ERR;
p_ctrl->config.omu.signal_detect_avail = param->signal_detect_avail;
p_ctrl->config.omu.signal_detect_port = param->signal_detect_port;
if (param->threshold_lol_set > 100)
return OPTIC_STATUS_POOR;
if (param->threshold_lol_clear > 100)
return OPTIC_STATUS_POOR;
p_ctrl->config.omu.threshold_lol_set = param->threshold_lol_set;
p_ctrl->config.omu.threshold_lol_clear = param->threshold_lol_clear;
p_ctrl->config.omu.laser_enable_single_ended =
param->laser_enable_single_ended;
/* ready to read tables & read configs */
p_ctrl->state.config_read[OPTIC_CONFIGTYPE_OMU] = true;
optic_state_set ( p_ctrl, OPTIC_STATE_CONFIG );
return OPTIC_STATUS_OK;
}
/**
The omu_cfg_get function is used to read back the basic configuration
of the OMU receive path within the GOI module.
*/
enum optic_errorcode omu_cfg_get ( struct optic_device *p_dev,
struct optic_omu_config *param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset(param, 0x00, sizeof(struct optic_omu_config));
param->signal_detect_avail = p_ctrl->config.omu.signal_detect_avail;
param->signal_detect_port = p_ctrl->config.omu.signal_detect_port;
param->threshold_lol_set = p_ctrl->config.omu.threshold_lol_set;
param->threshold_lol_clear = p_ctrl->config.omu.threshold_lol_clear;
param->laser_enable_single_ended =
p_ctrl->config.omu.laser_enable_single_ended;
return OPTIC_STATUS_OK;
}
/**
The omu_rx_enable function switches the receiver on.
*/
enum optic_errorcode omu_rx_enable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_pll_module_set ( OPTIC_PLL_RX, true );
}
/**
The omu_rx_disable function switches the receiver off.
*/
enum optic_errorcode omu_rx_disable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_pll_module_set ( OPTIC_PLL_RX, false );
}
/**
The omu_tx_enable function switches the receiver on.
*/
enum optic_errorcode omu_tx_enable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_pll_module_set ( OPTIC_PLL_TX, true );
}
/**
The omu_tx_disable function switches the receiver off.
*/
enum optic_errorcode omu_tx_disable ( struct optic_device *p_dev )
{
(void) p_dev;
return optic_ll_pll_module_set ( OPTIC_PLL_TX, false );
}
/**
The omu_tx_status_get function provides status information
that is available for the OMU transmitter.
*/
enum optic_errorcode omu_tx_status_get ( struct optic_device *p_dev,
struct optic_omu_tx_status_get
*param )
{
enum optic_errorcode ret;
enum optic_activation mode;
(void) p_dev;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset(param, 0x00, sizeof(struct optic_omu_tx_status_get));
/* read omu tx state */
ret = optic_ll_pll_module_get ( OPTIC_PLL_TX, &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->tx_enable = (mode == OPTIC_ENABLE) ? true : false;
return ret;
}
/**
The omu_rx_status_get function provides status information
that is available for the OMU receiver.
*/
enum optic_errorcode omu_rx_status_get ( struct optic_device *p_dev,
struct optic_omu_rx_status_get
*param )
{
struct optic_control *p_ctrl = p_dev->p_ctrl;
struct optic_config_omu *omu = &(p_ctrl->config.omu);
struct optic_interrupts *irq = &(p_ctrl->state.interrupts);
enum optic_errorcode ret;
enum optic_activation mode;
if (param == NULL)
return OPTIC_STATUS_ERR;
memset(param, 0x00, sizeof(struct optic_omu_rx_status_get));
/* read omu rx state */
ret = optic_ll_pll_module_get ( OPTIC_PLL_RX, &mode );
if (ret != OPTIC_STATUS_OK)
return ret;
param->rx_enable = (mode == OPTIC_ENABLE) ? true : false;
ret = optic_ll_int_omu_get ( omu->signal_detect_avail, irq,
&(param->loss_of_signal),
&(param->loss_of_lock) );
if (ret != OPTIC_STATUS_OK)
return ret;
return ret;
}
/* ----------------------------- NON IOCTL ---------------------------------- */
/**
The omu_init function is used to initialize the optical module (OMU).
- Make sure that FCSI registers are initialized,
to the same values as used for BOSA (part of GOI_init).
- The measurement unit is not needed. But we enable the module
to be able to use it for temperature measurements.
MM calibration is outside the scope of the OMU init function
(part of GOI_init).
1. configure TX FIFO
2. init CDR (RX)
3. set LOL thresholds (configure LOL alarm)
4. set LSB-MSB flip for RX data (low) path ctrl, TX data and bias path ctrl
5. enable receive data signals to GTC
6. set & enable receive DAC offset correction
7. init gpio: signal detect
*/
enum optic_errorcode omu_init ( struct optic_control *p_ctrl )
{
enum optic_errorcode ret;
struct optic_config_omu *omu = &(p_ctrl->config.omu);
bool ignore_error;
bool single_ended;
ignore_error = (p_ctrl->config.run_mode &
(1<<OPTIC_RUNMODE_ERROR_IGNORE)) ? true : false;
single_ended = p_ctrl->config.omu.laser_enable_single_ended;
ret = optic_ll_pll_laser_set ( single_ended );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("omu_init/optic_ll_pll_laser_set: %d",
ret);
if (! ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
/* disable APD DCDC */
ret = optic_ll_dcdc_apd_exit ();
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("omu_init/optic_ll_dcdc_apd_exit: %d", ret);
if (! ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_tx_init (OPTIC_OMU,
p_ctrl->config.bosa.pi_control,
p_ctrl->config.delay_tx_enable,
p_ctrl->config.delay_tx_disable,
p_ctrl->config.size_tx_fifo,
p_ctrl->config.bias_polarity_regular,
p_ctrl->config.mod_polarity_regular);
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("omu_init/optic_ll_tx_init: %d",
ret);
if (! ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
ret = optic_rx_init ( OPTIC_OMU, false,
omu->threshold_lol_clear,
omu->threshold_lol_set,
p_ctrl->config.rx_polarity_regular,
&(p_ctrl->calibrate.rx_offset) );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("omu_init/optic_ll_rx_init: %d",
ret);
if (! ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
if (p_ctrl->config.omu.signal_detect_avail == true) {
ret = optic_ll_gpio_init ( omu->signal_detect_port,
&(omu->signal_detect_irq) );
if (ret != OPTIC_STATUS_OK) {
OPTIC_DEBUG_ERR("omu_init/optic_ll_gpio_init: %d",
ret);
p_ctrl->config.omu.signal_detect_avail = false;
if (! ignore_error)
return OPTIC_STATUS_INIT_FAIL;
}
}
optic_irq_omu_init ( p_ctrl->config.omu.signal_detect_irq );
return OPTIC_STATUS_OK;
}
/* ------------------------------------------------------------------------- */
const struct optic_entry omu_function_table[OPTIC_OMU_MAX] =
{
/* 0 */ TE1in (FIO_OMU_CFG_SET, sizeof(struct optic_omu_config),
omu_cfg_set),
/* 1 */ TE1out (FIO_OMU_CFG_GET, sizeof(struct optic_omu_config),
omu_cfg_get),
/* 2 */ TE0 (FIO_OMU_RX_ENABLE, omu_rx_enable),
/* 3 */ TE0 (FIO_OMU_RX_DISABLE, omu_rx_disable),
/* 4 */ TE0 (FIO_OMU_TX_ENABLE, omu_tx_enable),
/* 5 */ TE0 (FIO_OMU_TX_DISABLE, omu_tx_disable),
/* 6 */ TE1out (FIO_OMU_RX_STATUS_GET, sizeof(struct optic_omu_rx_status_get),
omu_rx_status_get),
/* 7 */ TE1out (FIO_OMU_TX_STATUS_GET, sizeof(struct optic_omu_tx_status_get),
omu_tx_status_get)
};
/*! @} */
/*! @} */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_base_h
#define _drv_optic_reg_base_h
/** \addtogroup OPTIC_BASE
@{
*/
#ifndef KSEG1
#define KSEG1 0xA0000000
#endif
/** address range for gtc
0x1DC05000--0x1DC052D4 */
#define OPTIC_GTC_BASE (KSEG1 | 0x1DC00000)
#define OPTIC_GTC_END (KSEG1 | 0x1DC002D4)
#define OPTIC_GTC_SIZE 0x000002D5
/** address range for octrlg
0x1D420000--0x1D42FFFF */
#define OPTIC_OCTRLG_BASE (KSEG1 | 0x1D420000)
#define OPTIC_OCTRLG_END (KSEG1 | 0x1D42FFFF)
#define OPTIC_OCTRLG_SIZE 0x00010000
/** address range for pma
0x1DD00000--0x1DD003FF */
#define OPTIC_PMA_BASE (KSEG1 | 0x1DD00000)
#define OPTIC_PMA_END (KSEG1 | 0x1DD003FF)
#define OPTIC_PMA_SIZE 0x00000400
/** address range for fcsic
0x1DD00600--0x1DD0061F */
#define OPTIC_FCSIC_BASE (KSEG1 | 0x1DD00600)
#define OPTIC_FCSIC_END (KSEG1 | 0x1DD0061F)
#define OPTIC_FCSIC_SIZE 0x00000020
/** address range for pma_int200
0x1DD00700--0x1DD0070F */
#define OPTIC_PMA_INT200_BASE (KSEG1 | 0x1DD00700)
#define OPTIC_PMA_INT200_END (KSEG1 | 0x1DD0070F)
#define OPTIC_PMA_INT200_SIZE 0x00000010
/** address range for pma_inttx
0x1DD00720--0x1DD0072F */
#define OPTIC_PMA_INTTX_BASE (KSEG1 | 0x1DD00720)
#define OPTIC_PMA_INTTX_END (KSEG1 | 0x1DD0072F)
#define OPTIC_PMA_INTTX_SIZE 0x00000010
/** address range for pma_intrx
0x1DD00740--0x1DD0074F */
#define OPTIC_PMA_INTRX_BASE (KSEG1 | 0x1DD00740)
#define OPTIC_PMA_INTRX_END (KSEG1 | 0x1DD0074F)
#define OPTIC_PMA_INTRX_SIZE 0x00000010
/** address range for gtc_pma
0x1DEFFF00--0x1DEFFFFF */
#define OPTIC_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00)
#define OPTIC_GTC_PMA_END (KSEG1 | 0x1DEFFFFF)
#define OPTIC_GTC_PMA_SIZE 0x00000100
/** address range for sys_gpon
0x1DF00000--0x1DF000FF */
#define OPTIC_SYS_GPON_BASE (KSEG1 | 0x1DF00000)
#define OPTIC_SYS_GPON_END (KSEG1 | 0x1DF000FF)
#define OPTIC_SYS_GPON_SIZE 0x00000100
/** address range for status
0x1E802000--0x1E80207F */
#define OPTIC_STATUS_BASE (KSEG1 | 0x1E802000)
#define OPTIC_STATUS_END (KSEG1 | 0x1E80207F)
#define OPTIC_STATUS_SIZE 0x00000080
/** address range for dcdc_core
0x1E803000--0x1E8033FF */
#define OPTIC_DCDC_CORE_BASE (KSEG1 | 0x1E803000)
#define OPTIC_DCDC_CORE_END (KSEG1 | 0x1E8033FF)
#define OPTIC_DCDC_CORE_SIZE 0x00000400
/** address range for dcdc_ddr
0x1E804000--0x1E8043FF */
#define OPTIC_DCDC_DDR_BASE (KSEG1 | 0x1E804000)
#define OPTIC_DCDC_DDR_END (KSEG1 | 0x1E8043FF)
#define OPTIC_DCDC_DDR_SIZE 0x00000400
/** address range for dcdc_apd
0x1E805000--0x1E8053FF */
#define OPTIC_DCDC_APD_BASE (KSEG1 | 0x1E805000)
#define OPTIC_DCDC_APD_END (KSEG1 | 0x1E8053FF)
#define OPTIC_DCDC_APD_SIZE 0x00000400
/** address range for sys1
0x1EF00000--0x1EF000FF */
#define OPTIC_SYS1_BASE (KSEG1 | 0x1EF00000)
#define OPTIC_SYS1_END (KSEG1 | 0x1EF000FF)
#define OPTIC_SYS1_SIZE 0x00000100
/*! @} */ /* OPTIC_BASE */
#endif /* _drv_optic_reg_base_h */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_dcdc_h
#define _drv_optic_reg_dcdc_h
/** \addtogroup DCDC_REGISTER
@{
*/
/* access macros */
#define dcdc_core_r8(reg) (reg_r32(&dcdc_core->reg) & 0xFF)
#define dcdc_core_w8(val, reg) reg_w32((val) & 0xFF, &dcdc_core->reg)
#define dcdc_core_w8_mask(clear, set, reg) reg_w32_mask((clear) & 0xFF, (set) & 0xFF, &dcdc_core->reg)
#define dcdc_core_r8_table(reg, idx) (reg_r32_table(dcdc_core->reg, idx) & 0xFF)
#define dcdc_core_w8_table(val, reg, idx) reg_w32_table((val) & 0xFF, dcdc_core->reg, idx)
#define dcdc_core_w8_table_mask(clear, set, reg, idx) reg_w32_table_mask((clear) & 0xFF, (set) & 0xFF, dcdc_core->reg, idx)
#define dcdc_core_adr_table(reg, idx) adr_table(dcdc_core->reg, idx)
#define dcdc_ddr_r8(reg) (reg_r32(&dcdc_ddr->reg) & 0xFF)
#define dcdc_ddr_w8(val, reg) reg_w32((val) & 0xFF, &dcdc_ddr->reg)
#define dcdc_ddr_w8_mask(clear, set, reg) reg_w32_mask((clear) & 0xFF, (set) & 0xFF, &dcdc_ddr->reg)
#define dcdc_ddr_r8_table(reg, idx) (reg_r32_table(dcdc_ddr->reg, idx) & 0xFF)
#define dcdc_ddr_w8_table(val, reg, idx) reg_w32_table((val) & 0xFF, dcdc_ddr->reg, idx)
#define dcdc_ddr_w8_table_mask(clear, set, reg, idx) reg_w32_table_mask((clear) & 0xFF, (set) & 0xFF, dcdc_ddr->reg, idx)
#define dcdc_ddr_adr_table(reg, idx) adr_table(dcdc_ddr->reg, idx)
#define dcdc_apd_r8(reg) (reg_r32(&dcdc_apd->reg) & 0xFF)
#define dcdc_apd_w8(val, reg) reg_w32((val) & 0xFF, &dcdc_apd->reg)
#define dcdc_apd_w8_mask(clear, set, reg) reg_w32_mask((clear) & 0xFF, (set) & 0xFF, &dcdc_apd->reg)
#define dcdc_apd_r8_table(reg, idx) (reg_r32_table(dcdc_apd->reg, idx) & 0xFF)
#define dcdc_apd_w8_table(val, reg, idx) reg_w32_table((val) & 0xFF, dcdc_apd->reg, idx)
#define dcdc_apd_w8_table_mask(clear, set, reg, idx) reg_w32_table_mask((clear) & 0xFF, (set) & 0xFF, dcdc_apd->reg, idx)
#define dcdc_apd_adr_table(reg, idx) adr_table(dcdc_apd->reg, idx)
/** DCDC register structure */
struct optic_reg_dcdc
{
/** DCDC_PDI: DCDC Submodule Register File */
/** Hi Byte of coefficient b0
Not Specified */
unsigned int pdi_pid_hi_b0; /* 0x00000000 */
/** Lo Byte of coefficient b0
Not Specified */
unsigned int pdi_pid_lo_b0; /* 0x00000004 */
/** Hi Byte of coefficient b1
Not Specified */
unsigned int pdi_pid_hi_b1; /* 0x00000008 */
/** Lo Byte of coefficient b1
Not Specified */
unsigned int pdi_pid_lo_b1; /* 0x0000000C */
/** Hi Byte of coefficient b2
Not Specified */
unsigned int pdi_pid_hi_b2; /* 0x00000010 */
/** Lo Byte of coefficient b2
Not Specified */
unsigned int pdi_pid_lo_b2; /* 0x00000014 */
/** Set up clocks
Not Specified */
unsigned int pdi_clk_set0; /* 0x00000018 */
/** Set up clocks
Not Specified */
unsigned int pdi_clk_set1; /* 0x0000001C */
/** PWM Settings 0
Not Specified */
unsigned int pdi_pwm0; /* 0x00000020 */
/** PWM Settings 1
Not Specified */
unsigned int pdi_pwm1; /* 0x00000024 */
/** Set up BIAS and voltage regulator
Not Specified */
unsigned int pdi_bias_vreg; /* 0x00000028 */
/** Sets digital reference of DCDC converter
Not Specified */
unsigned int pdi_dig_ref; /* 0x0000002C */
/** General settings
Not Specified */
unsigned int pdi_general; /* 0x00000030 */
/** ADC conf0
Not Specified */
unsigned int pdi_adc0; /* 0x00000034 */
/** ADC conf1
Not Specified */
unsigned int pdi_adc1; /* 0x00000038 */
/** ADC conf2
Not Specified */
unsigned int pdi_adc2; /* 0x0000003C */
/** Analog Test Configuration for Autostart Mode
Not Specified */
unsigned int pdi_conf_test_ana; /* 0x00000040 */
/** Digital Test Configuration for Autostart Mode
Not Specified */
unsigned int pdi_conf_test_dig; /* 0x00000044 */
/** Analog Test Configuration for Non-Autostart Mode
Not Specified */
unsigned int pdi_conf_test_ana_noauto; /* 0x00000048 */
/** Digital Test Configuration for Non-Autostart Mode
Not Specified */
unsigned int pdi_conf_test_dig_noauto; /* 0x0000004C */
/** DCDC_STATUS
Not Specified */
unsigned int pdi_dcdc_status; /* 0x00000050 */
/** PID_STATUS
Not Specified */
unsigned int pdi_pid_status; /* 0x00000054 */
/** DUTY_CYCLE
Not Specified */
unsigned int pdi_duty_cycle; /* 0x00000058 */
/** NON_OV_DELAY
Not Specified */
unsigned int pdi_non_ov_delay; /* 0x0000005C */
/** ANALOG_GAIN
Not Specified */
unsigned int pdi_analog_gain; /* 0x00000060 */
/** DUTY_CYCLE_MAX_SAT
Not Specified */
unsigned int pdi_duty_cycle_max_sat; /* 0x00000064 */
/** DUTY_CYCLE_MIN_SAT
Not Specified */
unsigned int pdi_duty_cycle_min_sat; /* 0x00000068 */
/** DUTY_CYCLE_MAX
Not Specified */
unsigned int pdi_duty_cycle_max; /* 0x0000006C */
/** DUTY_CYCLE_MIN
Not Specified */
unsigned int pdi_duty_cycle_min; /* 0x00000070 */
/** ERROR_MAX
Not Specified */
unsigned int pdi_error_max; /* 0x00000074 */
/** ERROR_READ
Not Specified */
unsigned int pdi_error_read; /* 0x00000078 */
/** DELAY_DEGLITCH
Not Specified */
unsigned int pdi_delay_deglitch; /* 0x0000007C */
/** LATCH_CONTROL
Not Specified */
unsigned int pdi_latch_control; /* 0x00000080 */
/** LATCH_CONTROL_NOAUTO
Not Specified */
unsigned int pdi_latch_control_noauto; /* 0x00000084 */
/** CAP_CLK_CNT
Not Specified */
unsigned int pdi_cap_clk_cnt; /* 0x00000088 */
/** MDLL_DIVIDER
Not Specified */
unsigned int pdi_mdll_divider; /* 0x0000008C */
/** Reserved */
unsigned int pdi_res_0[220]; /* 0x00000090 */
/** OSC_PDI: OSC Submodule Register File */
/** OSC Configuration Register
Not Specified */
unsigned int osc_pdi_osc_conf; /* 0x00000400 */
/** OSC_STATUS
Not Specified */
unsigned int osc_pdi_osc_status; /* 0x00000404 */
/** Reserved */
unsigned int osc_pdi_res_1; /* 0x00000408 */
};
/* Fields of "Hi Byte of coefficient b0" */
/** Hi Byte of coefficient b0
Not Specified */
#define DCDC_PID_HI_B0_B_MASK 0xFF
/** field offset */
#define DCDC_PID_HI_B0_B_OFFSET 0
/** Kp = 1/Ks */
#define DCDC_PID_HI_B0_B_KP_1 0x02
/** Kp = 3/Ks */
#define DCDC_PID_HI_B0_B_KP_3 0x08
/** Kp = 5/Ks */
#define DCDC_PID_HI_B0_B_KP_5 0x0E
/** Kp = 7.5/Ks */
#define DCDC_PID_HI_B0_B_KP_7P5 0x15
/** Kp = 10/Ks */
#define DCDC_PID_HI_B0_B_KP_10 0x1C
/** Kp = 12.5/Ks */
#define DCDC_PID_HI_B0_B_KP_12P5 0x23
/** Kp = 15/Ks */
#define DCDC_PID_HI_B0_B_KP_15 0x2A
/** Kp = 17.5/Ks */
#define DCDC_PID_HI_B0_B_KP_17P5 0x31
/* Fields of "Lo Byte of coefficient b0" */
/** Lo Byte of coefficient b0
Not Specified */
#define DCDC_PID_LO_B0_B_MASK 0xFF
/** field offset */
#define DCDC_PID_LO_B0_B_OFFSET 0
/** Kp = 5/Ks */
#define DCDC_PID_LO_B0_B_KP_5 0x20
/** Kp = 7.5/Ks */
#define DCDC_PID_LO_B0_B_KP_7P5 0x31
/** Kp = 10/Ks */
#define DCDC_PID_LO_B0_B_KP_10 0x41
/** Kp = 12.5/Ks */
#define DCDC_PID_LO_B0_B_KP_12P5 0x51
/** Kp = 15/Ks */
#define DCDC_PID_LO_B0_B_KP_15 0x61
/** Kp = 17.5/Ks */
#define DCDC_PID_LO_B0_B_KP_17P5 0x72
/** Kp = 3/Ks */
#define DCDC_PID_LO_B0_B_KP_3 0x7A
/** Kp = 1/Ks */
#define DCDC_PID_LO_B0_B_KP_1 0xD3
/* Fields of "Hi Byte of coefficient b1" */
/** Hi Byte of coefficient b1
Not Specified */
#define DCDC_PID_HI_B1_B_MASK 0xFF
/** field offset */
#define DCDC_PID_HI_B1_B_OFFSET 0
/** Kp = 17.5/Ks */
#define DCDC_PID_HI_B1_B_KP_17P5 0x9B
/** Kp = 15/Ks */
#define DCDC_PID_HI_B1_B_KP_15 0xAA
/** Kp = 12.5/Ks */
#define DCDC_PID_HI_B1_B_KP_12P5 0xB8
/** Kp = 10/Ks */
#define DCDC_PID_HI_B1_B_KP_10 0xC6
/** Kp = 7.5/Ks */
#define DCDC_PID_HI_B1_B_KP_7P5 0xD5
/** Kp = 5/Ks */
#define DCDC_PID_HI_B1_B_KP_5 0xE3
/** Kp = 3/Ks */
#define DCDC_PID_HI_B1_B_KP_3 0xEE
/** Kp = 1/Ks */
#define DCDC_PID_HI_B1_B_KP_1 0xFA
/* Fields of "Lo Byte of coefficient b1" */
/** Lo Byte of coefficient b1
Not Specified */
#define DCDC_PID_LO_B1_B_MASK 0xFF
/** field offset */
#define DCDC_PID_LO_B1_B_OFFSET 0
/** Kp = 7.5/Ks */
#define DCDC_PID_LO_B1_B_KP_7P5 0x22
/** Kp = 15/Ks */
#define DCDC_PID_LO_B1_B_KP_15 0x45
/** Kp = 1/Ks */
#define DCDC_PID_LO_B1_B_KP_1 0x49
/** Kp = 5/Ks */
#define DCDC_PID_LO_B1_B_KP_5 0x6C
/** Kp = 12.5/Ks */
#define DCDC_PID_LO_B1_B_KP_12P5 0x8E
/** Kp = 10/Ks */
#define DCDC_PID_LO_B1_B_KP_10 0xD8
/** Kp = 3/Ks */
#define DCDC_PID_LO_B1_B_KP_3 0xDB
/** Kp = 17.5/Ks */
#define DCDC_PID_LO_B1_B_KP_17P5 0xFB
/* Fields of "Hi Byte of coefficient b2" */
/** Hi Byte of coefficient b2
Not Specified */
#define DCDC_PID_HI_B2_B_MASK 0xFF
/** field offset */
#define DCDC_PID_HI_B2_B_OFFSET 0
/** Kp = 1/Ks */
#define DCDC_PID_HI_B2_B_KP_1 0x02
/** Kp = 3/Ks */
#define DCDC_PID_HI_B2_B_KP_3 0x08
/** Kp = 5/Ks */
#define DCDC_PID_HI_B2_B_KP_5 0x0E
/** Kp = 7.5/Ks */
#define DCDC_PID_HI_B2_B_KP_7P5 0x15
/** Kp = 10/Ks */
#define DCDC_PID_HI_B2_B_KP_10 0x1C
/** Kp = 12.5/Ks */
#define DCDC_PID_HI_B2_B_KP_12P5 0x24
/** Kp = 15/Ks */
#define DCDC_PID_HI_B2_B_KP_15 0x2B
/** Kp = 17.5/Ks */
#define DCDC_PID_HI_B2_B_KP_17P5 0x32
/* Fields of "Lo Byte of coefficient b2" */
/** Lo Byte of coefficient b2
Not Specified */
#define DCDC_PID_LO_B2_B_MASK 0xFF
/** field offset */
#define DCDC_PID_LO_B2_B_OFFSET 0
/** Kp = 12.5/Ks */
#define DCDC_PID_LO_B2_B_KP_12P5 0x38
/** Kp = 15/Ks */
#define DCDC_PID_LO_B2_B_KP_15 0x76
/** Kp = 5/Ks */
#define DCDC_PID_LO_B2_B_KP_5 0x7D
/** Kp = 3/Ks */
#define DCDC_PID_LO_B2_B_KP_3 0xB1
/** Kp = 17.5/Ks */
#define DCDC_PID_LO_B2_B_KP_17P5 0xB4
/** Kp = 7.5/Ks */
#define DCDC_PID_LO_B2_B_KP_7P5 0xBB
/** Kp = 1/Ks */
#define DCDC_PID_LO_B2_B_KP_1 0xE6
/** Kp = 10/Ks */
#define DCDC_PID_LO_B2_B_KP_10 0xF9
/* Fields of "Set up clocks" */
/** MDLL multiplication factor
Integer by which input frequency is multiplied */
#define DCDC_CLK_SET0_MDLL_MUL_MASK 0x3F
/** field offset */
#define DCDC_CLK_SET0_MDLL_MUL_OFFSET 0
/** Sets PWM frequency to 720 MHz in VDSL-mode/to 500 MHz in non-VDSL-mode */
#define DCDC_CLK_SET0_MDLL_MUL_PWM500 0x12
/** Sets PWM frequency to 1440 MHz in VDSL-mode/to 1000 MHZ in non-VDSL-mode */
#define DCDC_CLK_SET0_MDLL_MUL_PWM1000 0x26
/** Set divider between MDLL and PWM
0 => MDLL output goes straight to PWM */
#define DCDC_CLK_SET0_CLK_SEL_PWM 0x40
/** Bypass MDLL
Input clock (36MHz in VDSL-mode, 25MHz in non-VDSL-mode) goes straight to PWM, bypassing the MDLL */
#define DCDC_CLK_SET0_MDLL_BYP 0x80
/* Fields of "Set up clocks" */
/** MDLL bias resistance
0,1,2,3,7 Higher number for higher frequency */
#define DCDC_CLK_SET1_MDLL_RES_MASK 0x07
/** field offset */
#define DCDC_CLK_SET1_MDLL_RES_OFFSET 0
/** Increase current step size in MDLL
Setting this bit will double the step size */
#define DCDC_CLK_SET1_MDLL_IX2 0x08
/** Double the frequency of ADC clocks
When the PWM clock is halved to 250MHz, this can be used to ensure that the ADC is still clocked with 250MHz iteration frequency. This also means that the PID controller gets double the clock frequency */
#define DCDC_CLK_SET1_ADC_CLK_MODE 0x10
/** reserved
Not Specified */
#define DCDC_CLK_SET1_RESERVED_MASK 0xE0
/** field offset */
#define DCDC_CLK_SET1_RESERVED_OFFSET 5
/* Fields of "PWM Settings 0" */
/** Counter pre-load
Sets factor between switching frequncy and PWM input clock. In order to work in VDSL-mode with 720MHz cpload has to be */
#define DCDC_PWM0_CPLOAD_MASK 0xFF
/** field offset */
#define DCDC_PWM0_CPLOAD_OFFSET 0
/* Fields of "PWM Settings 1" */
/** Static Duty Cycle Value
Sets duty cycle in case of PFM mode, or if force_static_dc is set. Also using the soft_preset_pid signal, the PID controller is set to this value, meaning that the integrator doesn't need to be charged up. dc = dc_static/cpload => thus nominal 80/256 = 30%, which is roughly what is needed for 3.3 V operation */
#define DCDC_PWM1_DC_STATIC_MASK 0xFF
/** field offset */
#define DCDC_PWM1_DC_STATIC_OFFSET 0
/* Fields of "Set up BIAS and voltage regulator" */
/** Trimming of the reference voltage */
#define DCDC_BIAS_VREG_VREF_MASK 0x07
/** field offset */
#define DCDC_BIAS_VREG_VREF_OFFSET 0
/** nominal value */
#define DCDC_BIAS_VREG_VREF_NOMINAL 0x00
/** -1.25% */
#define DCDC_BIAS_VREG_VREF_M125 0x01
/** -2.50% */
#define DCDC_BIAS_VREG_VREF_M250 0x02
/** -3.75% */
#define DCDC_BIAS_VREG_VREF_M375 0x03
/** +1.25% */
#define DCDC_BIAS_VREG_VREF_P125 0x04
/** +2.50% */
#define DCDC_BIAS_VREG_VREF_P250 0x05
/** +3.75% */
#define DCDC_BIAS_VREG_VREF_P375 0x06
/** +5.00% */
#define DCDC_BIAS_VREG_VREF_P500 0x07
/** Set voltage of internal regulator
Trimming of the internal voltage regulator */
#define DCDC_BIAS_VREG_VREG_SEL_MASK 0x18
/** field offset */
#define DCDC_BIAS_VREG_VREG_SEL_OFFSET 3
/** 0.93V */
#define DCDC_BIAS_VREG_VREG_SEL_M120 0x00
/** 1.0V */
#define DCDC_BIAS_VREG_VREG_SEL_M50 0x08
/** nominal value 1.05V */
#define DCDC_BIAS_VREG_VREG_SEL_NOMINAL 0x10
/** 1.175 */
#define DCDC_BIAS_VREG_VREG_SEL_P70 0x18
/** Reduce bias current for voltage regulator
Useful if load is low to gain more stability */
#define DCDC_BIAS_VREG_I_RED 0x20
/** Increase current load for internal regulator
Increase stability and performance by drawing 1mA of current through a resistor */
#define DCDC_BIAS_VREG_I_LOADINC 0x40
/** reserved
Not Specified */
#define DCDC_BIAS_VREG_RESERVED 0x80
/* Fields of "Sets digital reference of DCDC converter" */
/** Sets digital reference of DCDC converter
Sets up Most Significant Bits of target voltage */
#define DCDC_DIG_REF_V_MASK 0xFF
/** field offset */
#define DCDC_DIG_REF_V_OFFSET 0
/** minus 100mV = 0.90 */
#define DCDC_DIG_REF_V_M100 0x72
/** minus 50mV = 0.95 */
#define DCDC_DIG_REF_V_M50 0x78
/** nominal value 1.0V */
#define DCDC_DIG_REF_V_NOMINAL 0x7F
/** plus 50mV = 1.05 */
#define DCDC_DIG_REF_V_P50 0x86
/** plus 100mV = 1.10 */
#define DCDC_DIG_REF_V_P100 0x8C
/* Fields of "General settings" */
/** Causes fixed duty cycle
Value is taken from dc_static */
#define DCDC_GENERAL_FORCE_STATIC_DC 0x01
/** Switch on PFM mode
Similar to force_static_dc, except that additionally the Output Stage is enabled and disabled depending on the output of the PFM comparator, which compares the core voltage to 1.0V and 1.05V */
#define DCDC_GENERAL_PFM_MODE 0x02
/** enable output stage
Providing that the powerup signal has been received and pfm_mode isn't active, this signal enables the output stage, or makes it high ohmic */
#define DCDC_GENERAL_OS_EN 0x04
/** reserved
Not Specified */
#define DCDC_GENERAL_RESERVED0 0x08
/** invert PWM output signal
Invert the output of the PWM for external power devices */
#define DCDC_GENERAL_OUT_INV 0x10
/** reserved
Not Specified */
#define DCDC_GENERAL_RESERVED1_MASK 0x60
/** field offset */
#define DCDC_GENERAL_RESERVED1_OFFSET 5
/** set half LSB of digital reference
This is used to ensure that the control loop never reaches the dead region where it thinks the error is exactly 0 and makes no change to its output. Set at 1, the smallest error value can be + or - 0.5 LSB */
#define DCDC_GENERAL_SET_LSB_DIGREF 0x80
/* Fields of "ADC conf0" */
/** set comparator-to-arith clock delay
set comparator-to-arith clock delay 0:1:3 */
#define DCDC_ADC0_SET_COMP2ARITH_MASK 0x07
/** field offset */
#define DCDC_ADC0_SET_COMP2ARITH_OFFSET 0
/** set comparator-to-array clock delay
set comparator-to-array clock delay 0:1:7 */
#define DCDC_ADC0_SET_COMP2ARRAY_MASK 0x38
/** field offset */
#define DCDC_ADC0_SET_COMP2ARRAY_OFFSET 3
/** choose rom bank */
#define DCDC_ADC0_SET_ROM_SEL_MASK 0xC0
/** field offset */
#define DCDC_ADC0_SET_ROM_SEL_OFFSET 6
/* Fields of "ADC conf1" */
/** set reset arithunit
0: start from last sample */
#define DCDC_ADC1_SET_RESETARITH 0x01
/** enable comparator offset calibration
1: enable comparator offset calibration */
#define DCDC_ADC1_SET_OFFSET_CAL_EN 0x02
/** set comparator bias current
set comparator bias current to 12.5uA x 2:1:6 */
#define DCDC_ADC1_SET_COMP_CURR_MASK 0x1C
/** field offset */
#define DCDC_ADC1_SET_COMP_CURR_OFFSET 2
/** set scrambling state
set scrambling state 0:1:3 */
#define DCDC_ADC1_SET_SCR_STATE_MASK 0x60
/** field offset */
#define DCDC_ADC1_SET_SCR_STATE_OFFSET 5
/** reserved */
#define DCDC_ADC1_RESERVED 0x80
/* Fields of "ADC conf2" */
/** highest rom address while iterating
highest rom address while iterating 0:1:11 */
#define DCDC_ADC2_SET_ROM_START_MASK 0x0F
/** field offset */
#define DCDC_ADC2_SET_ROM_START_OFFSET 0
/** number of cycles per conversion minus one
number of cycles per conversion minus one 0:1:11 */
#define DCDC_ADC2_SET_START_MASK 0xF0
/** field offset */
#define DCDC_ADC2_SET_START_OFFSET 4
/* Fields of "Analog Test Configuration for Autostart Mode" */
/** Reset ADC
Not Specified */
#define DCDC_CONF_TEST_ANA_SOFT_RES_ADC_N 0x01
/** Reset MDLL
Not Specified */
#define DCDC_CONF_TEST_ANA_SOFT_RES_MDLL_N 0x02
/** Reset DPWM
The PWM generator is disabled. */
#define DCDC_CONF_TEST_ANA_SOFT_RES_DPWM_N 0x04
/** Power Down ADC
Not Specified */
#define DCDC_CONF_TEST_ANA_PD_ADC 0x08
/** reserved
Not Specified */
#define DCDC_CONF_TEST_ANA_RESERVED0 0x10
/** Power Down of PFM comparator
Not Specified */
#define DCDC_CONF_TEST_ANA_PD_PFMCOMP 0x20
/** Bypass Digital PWM generator
This passes the startup clk (25MHz/32) to the output of the DPWM block, allowing the DPWM to be put in reset. This feature is particularly interesting in PFM mode. */
#define DCDC_CONF_TEST_ANA_DPWM_BYP 0x40
/** Oscillator max suppression
This switches on the max suppression filter in the oscillator. */
#define DCDC_CONF_TEST_ANA_OSC_MAX_SUPPR 0x80
/* Fields of "Digital Test Configuration for Autostart Mode" */
/** Reset PID Controller
Not Specified */
#define DCDC_CONF_TEST_DIG_SOFT_RES_PID_N 0x01
/** Reset Rampup Generator
Causes the digital reference to start at zero and ramp to the value in its register */
#define DCDC_CONF_TEST_DIG_SOFT_RES_RAMPUP_N 0x02
/** Bypass PID control
Bypass PID control - Data from ADC accumulator are passed straight to DPWM */
#define DCDC_CONF_TEST_DIG_TEST_ADC2DUTY 0x04
/** Bypass of ADC accumulator
Bypass ADC accumulator - Data from ADC are passed straight to output of accumulator */
#define DCDC_CONF_TEST_DIG_TEST_ACCUM_BYP 0x08
/** Freeze PID controller
This is used to reset the sequencer which controls the pid filter. Should be set while changing any of the coefficients */
#define DCDC_CONF_TEST_DIG_FREEZE_PID 0x10
/** Soft preset of PID controller
This is used to preset the PID integrator, and output with the value of the static_dc register, and other registers to zero. Can be used to bring the system back under control */
#define DCDC_CONF_TEST_DIG_SOFT_PRESET_PID 0x20
/** reserved
Not Specified */
#define DCDC_CONF_TEST_DIG_RESERVED_MASK 0xC0
/** field offset */
#define DCDC_CONF_TEST_DIG_RESERVED_OFFSET 6
/* Fields of "Analog Test Configuration for Non-Autostart Mode" */
/** Reset ADC
Not Specified */
#define DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_ADC_N 0x01
/** Reset MDLL
Not Specified */
#define DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_MDLL_N 0x02
/** Reset DPWM
Not Specified */
#define DCDC_CONF_TEST_ANA_NOAUTO_SOFT_RES_DPWM_N 0x04
/** Power Down ADC
Not Specified */
#define DCDC_CONF_TEST_ANA_NOAUTO_PD_ADC 0x08
/** reserved
Not Specified */
#define DCDC_CONF_TEST_ANA_NOAUTO_RESERVED0 0x10
/** Power Down of PFM comparator
Not Specified */
#define DCDC_CONF_TEST_ANA_NOAUTO_PD_PFMCOMP 0x20
/** Bypass Digital PWM generator
This passes the startup clk (25MHz/32) to the output of the DPWM block, allowing the DPWM to be put in reset. This feature is particularly interesting in PFM mode. */
#define DCDC_CONF_TEST_ANA_NOAUTO_DPWM_BYP 0x40
/** Oscillator max suppression
This switches on the max suppression filter in the oscillator. */
#define DCDC_CONF_TEST_ANA_NOAUTO_OSC_MAX_SUPPR 0x80
/* Fields of "Digital Test Configuration for Non-Autostart Mode" */
/** Reset PID Controller
Not Specified */
#define DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_PID_N 0x01
/** Reset Rampup Generator
Causes the digital reference to start at zero and ramp to the value in its register */
#define DCDC_CONF_TEST_DIG_NOAUTO_SOFT_RES_RAMPUP_N 0x02
/** Bypass PID control
Bypass PID control - Data from ADC accumulator are passed straight to DPWM */
#define DCDC_CONF_TEST_DIG_NOAUTO_TEST_ADC2DUTY 0x04
/** Bypass of ADC accumulator
Bypass ADC accumulator - Data from ADC are passed straight to output of accumulator */
#define DCDC_CONF_TEST_DIG_NOAUTO_TEST_ACCUM_BYP 0x08
/** Freeze PID controller
This is used to reset the sequencer which controls the pid filter. Should be set while changing any of the coefficients */
#define DCDC_CONF_TEST_DIG_NOAUTO_FREEZE_PID 0x10
/** Soft preset of PID controller
This is used to preset the PID integrator, and output with the value of the static_dc register, and other registers to zero. Can be used to bring the system back under control */
#define DCDC_CONF_TEST_DIG_NOAUTO_SOFT_PRESET_PID 0x20
/** reserved
Not Specified */
#define DCDC_CONF_TEST_DIG_NOAUTO_RESERVED_MASK 0xC0
/** field offset */
#define DCDC_CONF_TEST_DIG_NOAUTO_RESERVED_OFFSET 6
/* Fields of "DCDC_STATUS" */
/** powerup dcdc signal detected just after reset */
#define DCDC_DCDC_STATUS_POWERUP_DCDC 0x01
/** Output current higher than 1A for more than 8 cycles */
#define DCDC_DCDC_STATUS_IMAX_REACHED 0x02
/** mdll locked signal */
#define DCDC_DCDC_STATUS_MDLL_LOCKED 0x04
/** inverted version of mdll locked signal - used to detect whether the MDLL wwas continually in locked. If set, then it was at least temporarily out of lock */
#define DCDC_DCDC_STATUS_MDLL_LOCKED_N 0x08
/* Fields of "PID_STATUS" */
/** duty cycle positive saturation (240/255) */
#define DCDC_PID_STATUS_DUTY_SAT_HI 0x01
/** duty cycle negative saturation (7/255) */
#define DCDC_PID_STATUS_DUTY_SAT_LO 0x02
/** error positive saturation (2^8-1) */
#define DCDC_PID_STATUS_ERR_SAT_HI 0x04
/** error negative saturation (-2^8) */
#define DCDC_PID_STATUS_ERR_SAT_LO 0x08
/** multiplier positive saturation (2^20-1) */
#define DCDC_PID_STATUS_MUL_SAT_HI 0x10
/** multiplier negative saturation (-2^20) */
#define DCDC_PID_STATUS_MUL_SAT_LO 0x20
/** PID controller has detected an error of > +/- 120mV for 7 cycles in a row! DANGER! */
#define DCDC_PID_STATUS_REG_FAIL 0x40
/** reserved */
#define DCDC_PID_STATUS_RESERVED 0x80
/* Fields of "DUTY_CYCLE" */
/** Contains the data going from PID to DPWM */
#define DCDC_DUTY_CYCLE_DC_WISH_MASK 0xFF
/** field offset */
#define DCDC_DUTY_CYCLE_DC_WISH_OFFSET 0
/* Fields of "NON_OV_DELAY" */
/** non-overlap-time for PMOS turn off
time between PMOS turn-off and NMOS turn-on */
#define DCDC_NON_OV_DELAY_DEL_N_MASK 0x0F
/** field offset */
#define DCDC_NON_OV_DELAY_DEL_N_OFFSET 0
/** non-overlap-time for PMOS turn on
time between NMOS turn-off and PMOS turn-on */
#define DCDC_NON_OV_DELAY_DEL_P_MASK 0xF0
/** field offset */
#define DCDC_NON_OV_DELAY_DEL_P_OFFSET 4
/* Fields of "ANALOG_GAIN" */
/** attenuation after subtraction of the analog reference. Used for DCDC that senses 1.8V or 2.5V, in case of DDR1 or DDR2 supply, together with the changed reference voltage (see vref_ana bit): */
#define DCDC_ANALOG_GAIN_ATTENUATE_ANA 0x01
/** gain in front ADC (after subtraction of the analog reference) */
#define DCDC_ANALOG_GAIN_GAIN_ANA_MASK 0x06
/** field offset */
#define DCDC_ANALOG_GAIN_GAIN_ANA_OFFSET 1
/** reference voltage for single to diff SC input buffer: */
#define DCDC_ANALOG_GAIN_VREF_ANA 0x08
/** reserved */
#define DCDC_ANALOG_GAIN_RESERVED_MASK 0xF0
/** field offset */
#define DCDC_ANALOG_GAIN_RESERVED_OFFSET 4
/* Fields of "DUTY_CYCLE_MAX_SAT" */
/** Contains the upper saturation value for the duty cycle */
#define DCDC_DUTY_CYCLE_MAX_SAT_DUTY_MAX_SAT_MASK 0xFF
/** field offset */
#define DCDC_DUTY_CYCLE_MAX_SAT_DUTY_MAX_SAT_OFFSET 0
/* Fields of "DUTY_CYCLE_MIN_SAT" */
/** Contains the lower saturation value for the duty cycle */
#define DCDC_DUTY_CYCLE_MIN_SAT_DUTY_MIN_SAT_MASK 0xFF
/** field offset */
#define DCDC_DUTY_CYCLE_MIN_SAT_DUTY_MIN_SAT_OFFSET 0
/* Fields of "DUTY_CYCLE_MAX" */
/** Contains the comparison value for the duty cycle. If the duty cycle is higher than this value => alarm that a overcurrent/short condition is happening */
#define DCDC_DUTY_CYCLE_MAX_DUTY_MAX_MASK 0xFF
/** field offset */
#define DCDC_DUTY_CYCLE_MAX_DUTY_MAX_OFFSET 0
/* Fields of "DUTY_CYCLE_MIN" */
/** Contains the comparison value for the duty cycle. If the duty cycle is lower than this value => alarm that a pmos short etc. condition is happening */
#define DCDC_DUTY_CYCLE_MIN_DUTY_MIN_MASK 0xFF
/** field offset */
#define DCDC_DUTY_CYCLE_MIN_DUTY_MIN_OFFSET 0
/* Fields of "ERROR_MAX" */
/** Contains the comparison value for the error. */
#define DCDC_ERROR_MAX_ERROR_MAX_MASK 0xFF
/** field offset */
#define DCDC_ERROR_MAX_ERROR_MAX_OFFSET 0
/* Fields of "ERROR_READ" */
/** Contains the actual error that is fed to the PID */
#define DCDC_ERROR_READ_ERROR_MASK 0xFF
/** field offset */
#define DCDC_ERROR_READ_ERROR_OFFSET 0
/* Fields of "DELAY_DEGLITCH" */
/** Deglitching counter for alarm. The alarm must be consistent active for the alarm_deglitch number of DCDC cycles, before the output is activated: */
#define DCDC_DELAY_DEGLITCH_ALARM_DEGLITCH_MASK 0x0F
/** field offset */
#define DCDC_DELAY_DEGLITCH_ALARM_DEGLITCH_OFFSET 0
/** Speed setting for soft start ramp: */
#define DCDC_DELAY_DEGLITCH_RAMP_DELAY_MASK 0x70
/** field offset */
#define DCDC_DELAY_DEGLITCH_RAMP_DELAY_OFFSET 4
/** reserved */
#define DCDC_DELAY_DEGLITCH_RESERVED 0x80
/* Fields of "LATCH_CONTROL" */
/** Select the latch for synchronising the SC input buffer data with the ADC result. */
#define DCDC_LATCH_CONTROL_CAP_CLK_MODE 0x01
/** reserved */
#define DCDC_LATCH_CONTROL_RESERVED1_MASK 0x06
/** field offset */
#define DCDC_LATCH_CONTROL_RESERVED1_OFFSET 1
/** Force p-transistor to static value. */
#define DCDC_LATCH_CONTROL_PFORCE_EN 0x08
/** Static value for p-transistor when forced. */
#define DCDC_LATCH_CONTROL_PFORCE_AT 0x10
/** Force n-transistor to static value. */
#define DCDC_LATCH_CONTROL_NFORCE_EN 0x20
/** Static value for n-transistor when forced. */
#define DCDC_LATCH_CONTROL_NFORCE_AT 0x40
/** reserved */
#define DCDC_LATCH_CONTROL_RESERVED2 0x80
/* Fields of "LATCH_CONTROL_NOAUTO" */
/** Select the latch for synchronising the SC input buffer data with the ADC result. */
#define DCDC_LATCH_CONTROL_NOAUTO_CAP_CLK_MODE 0x01
/** reserved */
#define DCDC_LATCH_CONTROL_NOAUTO_RESERVED1_MASK 0x06
/** field offset */
#define DCDC_LATCH_CONTROL_NOAUTO_RESERVED1_OFFSET 1
/** Force p-transistor to static value. */
#define DCDC_LATCH_CONTROL_NOAUTO_PFORCE_EN 0x08
/** Static value for p-transistor when forced. */
#define DCDC_LATCH_CONTROL_NOAUTO_PFORCE_AT 0x10
/** Force n-transistor to static value. */
#define DCDC_LATCH_CONTROL_NOAUTO_NFORCE_EN 0x20
/** Static value for n-transistor when forced. */
#define DCDC_LATCH_CONTROL_NOAUTO_NFORCE_AT 0x40
/** reserved */
#define DCDC_LATCH_CONTROL_NOAUTO_RESERVED2 0x80
/* Fields of "CAP_CLK_CNT" */
/** Contains the value for the capture clock counter. The ouput frequency is calculated by the formula fcap_clk = fsample_clk/counter value. */
#define DCDC_CAP_CLK_CNT_COUNTER_MASK 0xFF
/** field offset */
#define DCDC_CAP_CLK_CNT_COUNTER_OFFSET 0
/* Fields of "MDLL_DIVIDER" */
/** Select the post divider for MDLL clock. */
#define DCDC_MDLL_DIVIDER_DIVIDER_MASK 0x03
/** field offset */
#define DCDC_MDLL_DIVIDER_DIVIDER_OFFSET 0
/** Reserved bits for analog part of the DCDC converter. */
#define DCDC_MDLL_DIVIDER_ANA_RES_MASK 0x0C
/** field offset */
#define DCDC_MDLL_DIVIDER_ANA_RES_OFFSET 2
/* Fields of "OSC Configuration Register" */
/** Disable amplitude regulation
Leads to increase of amplitude at XTAL1, */
#define DCDC_OSC_CONF_REG_DIS 0x01
/** Increase regulation capacitance
Leads to increase of amplitude at XTAL1, */
#define DCDC_OSC_CONF_CAP_UP 0x02
/** Bypass shaper */
#define DCDC_OSC_CONF_SH_BYP_REG 0x04
/** Overwrite frequency detection
Instead of automatically detecting incoming frequency, this can be overwritten using this bit. The value is taken from OWR_FDET_VAL */
#define DCDC_OSC_CONF_OWR_FDET 0x08
/** Value of frequency detection in overwrite mode
0 => Frequency at XTAL1 goes through */
#define DCDC_OSC_CONF_OWR_FDET_VAL 0x10
/** Power down of frequency detector */
#define DCDC_OSC_CONF_PD_FDETECT 0x20
/** Power down of clock shaper */
#define DCDC_OSC_CONF_PD_SHAPER 0x40
/** Power down of oscillator core */
#define DCDC_OSC_CONF_PD_CORE 0x80
/* Fields of "OSC_STATUS" */
/** osc clk frequency detected */
#define DCDC_OSC_STATUS_CLK_FREQ 0x01
/*! @} */ /* DCDC_REGISTER */
#endif /* _drv_optic_reg_dcdc_h */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_fcsi_base_h
#define _drv_optic_reg_fcsi_base_h
/** \addtogroup FCSI_BASE
@{
*/
/** address range for txbosa
0x00--0x07 */
#define FCSI_TXBOSA_BASE 0x00
#define FCSI_TXBOSA_END 0x07
#define FCSI_TXBOSA_SIZE 0x08
/** address range for txomu
0x08--0x0A */
#define FCSI_TXOMU_BASE 0x08
#define FCSI_TXOMU_END 0x0A
#define FCSI_TXOMU_SIZE 0x03
/** address range for rxbosa
0x0B--0x0B */
#define FCSI_RXBOSA_BASE 0x0B
#define FCSI_RXBOSA_END 0x0B
#define FCSI_RXBOSA_SIZE 0x01
/** address range for rxomu
0x0D--0x0D */
#define FCSI_RXOMU_BASE 0x0D
#define FCSI_RXOMU_END 0x0D
#define FCSI_RXOMU_SIZE 0x01
/** address range for mm
0x0E--0x0E */
#define FCSI_MM_BASE 0x0E
#define FCSI_MM_END 0x0E
#define FCSI_MM_SIZE 0x01
/** address range for vdac
0x0F--0x0F */
#define FCSI_VDAC_BASE 0x0F
#define FCSI_VDAC_END 0x0F
#define FCSI_VDAC_SIZE 0x01
/** address range for bfd
0x10--0x12 */
#define FCSI_BFD_BASE 0x10
#define FCSI_BFD_END 0x12
#define FCSI_BFD_SIZE 0x03
/** address range for pi
0x13--0x13 */
#define FCSI_PI_BASE 0x13
#define FCSI_PI_END 0x13
#define FCSI_PI_SIZE 0x01
/** address range for cbias
0x14--0x15 */
#define FCSI_CBIAS_BASE 0x14
#define FCSI_CBIAS_END 0x15
#define FCSI_CBIAS_SIZE 0x02
/** address range for vdll
0x18--0x18 */
#define FCSI_VDLL_BASE 0x18
#define FCSI_VDLL_END 0x18
#define FCSI_VDLL_SIZE 0x01
/*! @} */ /* FCSI_BASE */
#endif /* _drv_optic_reg_fcsi_base_h */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_fcsi_bfd_h
#define _drv_optic_reg_fcsi_bfd_h
/** \addtogroup BFD_REGISTER
@{
*/
#ifndef __ASSEMBLY__
/* access macros */
#define bfd_r16(reg) reg_r16(&bfd->reg)
#define bfd_w16(val, reg) reg_w16(val, &bfd->reg)
#define bfd_w16_mask(clear, set, reg) reg_w16_mask(clear, set, &bfd->reg)
#define bfd_r16_table(reg, idx) reg_r16_table(bfd->reg, idx)
#define bfd_w16_table(val, reg, idx) reg_w16_table(val, bfd->reg, idx)
#define bfd_w16_table_mask(clear, set, reg, idx) reg_w16_table_mask(clear, set, bfd->reg, idx)
#define bfd_adr_table(reg, idx) adr_table(bfd->reg, idx)
/** BFD register structure */
struct fcsi_reg_bfd
{
/** Gain Values Register; #16
This Register serves as shadow register for the gain_tia(2:0) signal controlled from the PMA. gain_tia selects one field from this register: */
unsigned short gvs; /* 0x00 */
/** Control Register 0; #17 */
unsigned short ctrl0; /* 0x01 */
/** Control Register 1; #18 */
unsigned short ctrl1; /* 0x02 */
};
#define FCSI_BFD_GVS ((volatile unsigned short*)(FCSI_BFD_BASE + 0x00))
#define FCSI_BFD_CTRL0 ((volatile unsigned short*)(FCSI_BFD_BASE + 0x01))
#define FCSI_BFD_CTRL1 ((volatile unsigned short*)(FCSI_BFD_BASE + 0x02))
#define FCSI_PI_CTRL ((volatile unsigned short*)(FCSI_PI_BASE + 0x00))
#else /* __ASSEMBLY__ */
#define FCSI_BFD_GVS (FCSI_BFD_BASE + 0x00)
#define FCSI_BFD_CTRL0 (FCSI_BFD_BASE + 0x01)
#define FCSI_BFD_CTRL1 (FCSI_BFD_BASE + 0x02)
#define FCSI_PI_CTRL (FCSI_BFD_BASE + 0x00)
#endif /* __ASSEMBLY__ */
/* Fields of "Gain Values Register; #16" */
/** FCSI Gain (bfd_fcsi_gain) 3
See field GAIN0 for the coding details. */
#define BFD_GVS_GAIN3_MASK 0xF000
/** field offset */
#define BFD_GVS_GAIN3_OFFSET 12
/** FCSI Gain (bfd_fcsi_gain) 2
See field GAIN0 for the coding details. */
#define BFD_GVS_GAIN2_MASK 0x0F00
/** field offset */
#define BFD_GVS_GAIN2_OFFSET 8
/** FCSI Gain (bfd_fcsi_gain) 1
See field GAIN0 for the coding details. */
#define BFD_GVS_GAIN1_MASK 0x00F0
/** field offset */
#define BFD_GVS_GAIN1_OFFSET 4
/** FCSI Gain (bfd_fcsi_gain) 0
The gain coding is not described here. */
#define BFD_GVS_GAIN0_MASK 0x000F
/** field offset */
#define BFD_GVS_GAIN0_OFFSET 0
/* Fields of "Control Register 0; #17" */
/** Bypass Leakage Compensation LD (bfd_ld_leak_bypass) */
#define BFD_CTRL0_BLLD 0x4000
/** No bypass */
#define BFD_CTRL0_BLLD_NBYP 0x0000
/** Bypass */
#define BFD_CTRL0_BLLD_BYP 0x4000
/** Common Mode Select (bfd_prog_vcm0v5)
Select the output common mode voltage of the limiting amplifier. The common mode voltage calculates as 0.45 + 25mV*this-field-value */
#define BFD_CTRL0_VCM0V5_MASK 0x3000
/** field offset */
#define BFD_CTRL0_VCM0V5_OFFSET 12
/** Common Mode Select (bfd_prog_vcm0v6)
Select the output common mode voltage of the limiting amplifier. */
#define BFD_CTRL0_VCM0V6_MASK 0x0C00
/** field offset */
#define BFD_CTRL0_VCM0V6_OFFSET 10
/** 0.60 Volts */
#define BFD_CTRL0_VCM0V6_V060 0x0000
/** 0.55 Volts */
#define BFD_CTRL0_VCM0V6_V055 0x0400
/** 0.65 Volts */
#define BFD_CTRL0_VCM0V6_V065 0x0800
/** 0.70 Volts */
#define BFD_CTRL0_VCM0V6_V070 0x0C00
/** CDR Off (bfd_cdr_dis) */
#define BFD_CTRL0_CDRO 0x0200
/** Default Operation. */
#define BFD_CTRL0_CDRO_DEF 0x0000
/** Clock generation outputs (div2, div4) are 0. */
#define BFD_CTRL0_CDRO_OFF 0x0200
/** Input Termination Select (bfd_rterm_sel)
The termination resistor */
#define BFD_CTRL0_RTSEL_MASK 0x01F0
/** field offset */
#define BFD_CTRL0_RTSEL_OFFSET 4
/** Bypass Leakage Compensation DAC (bfd_offdac_leak_bypass) */
#define BFD_CTRL0_BLCD 0x0008
/** No bypass */
#define BFD_CTRL0_BLCD_NBYP 0x0000
/** Bypass */
#define BFD_CTRL0_BLCD_BYP 0x0008
/** Common Mode Select (bfd_output_cm_sel)
Select the output common mode voltage of the bfd levelshiftblock. The common mode voltage calculates as VDD - 60mV*(this-field-value + 1) */
#define BFD_CTRL0_CMSEL_MASK 0x0007
/** field offset */
#define BFD_CTRL0_CMSEL_OFFSET 0
/* Fields of "Control Register 1; #18" */
/** PD LDO (pd_ldo)
powerdown of the internal linear regulator. */
#define BFD_CTRL1_PDLS 0x0800
/** red bias curr(ired)
Reduce bias current of the opamp of the linreg block. */
#define BFD_CTRL1_IRED 0x0400
/** VLDO_SEL (vldo_sel)
The output voltage of the internal bfd linreg is not described here. */
#define BFD_CTRL1_LDO_MASK 0x0300
/** field offset */
#define BFD_CTRL1_LDO_OFFSET 8
/** Clock Inversion Reset (bfd_rst_inv)
Invert the clock edge of the sync. clock for the reset. */
#define BFD_CTRL1_RINV 0x0080
/** non-inverted clk is used */
#define BFD_CTRL1_RINV_NINV 0x0000
/** inverted clk is used */
#define BFD_CTRL1_RINV_INV 0x0080
/** Clock Inversion (bfd_clk_edge_sel)
Inverts the divide by eight clock coming from the bfd block. */
#define BFD_CTRL1_CINV 0x0040
/** non-inverted clk is used */
#define BFD_CTRL1_CINV_NINV 0x0000
/** inverted clk is used */
#define BFD_CTRL1_CINV_INV 0x0040
/** Reset (bfd_rst)
Apply reset for all the DAC flipoflops and for the serializer block. */
#define BFD_CTRL1_RST 0x0020
/** No Reset */
#define BFD_CTRL1_RST_NRST 0x0000
/** Bypass Limiting Amplifier for P (byp_limit)1 */
#define BFD_CTRL1_BLAP1 0x0010
/** No bypass */
#define BFD_CTRL1_BLAP1_NBYP 0x0000
/** Bypass */
#define BFD_CTRL1_BLAP1_BYP 0x0010
/** Bypass Limiting Amplifier for P (byp_limit)0 */
#define BFD_CTRL1_BLAP0 0x0008
/** No bypass */
#define BFD_CTRL1_BLAP0_NBYP 0x0000
/** Bypass */
#define BFD_CTRL1_BLAP0_BYP 0x0008
/** Test DAC Select (bfd_test_dac_sel)
Select the DAC output voltages, used inside the measurement module */
#define BFD_CTRL1_TDSEL_MASK 0x0007
/** field offset */
#define BFD_CTRL1_TDSEL_OFFSET 0
/** leveldac for p0 */
#define BFD_CTRL1_TDSEL_LDP0 0x0000
/** leveldac for p1 */
#define BFD_CTRL1_TDSEL_LDP1 0x0000
/** fine offset DAC */
#define BFD_CTRL1_TDSEL_FOD 0x0000
/** coarse offset DAC */
#define BFD_CTRL1_TDSEL_COD 0x0000
/** None */
#define BFD_CTRL1_TDSEL_NONE 0x0000
/*! @} */ /* BFD_REGISTER */
#endif /* _drv_optic_reg_fcsi_bfd_h */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_fcsi_cbias_h
#define _drv_optic_reg_fcsi_cbias_h
/** \addtogroup CBIAS_REGISTER
@{
*/
#ifndef __ASSEMBLY__
/* access macros */
#define cbias_r16(reg) reg_r16(&cbias->reg)
#define cbias_w16(val, reg) reg_w16(val, &cbias->reg)
#define cbias_w16_mask(clear, set, reg) reg_w16_mask(clear, set, &cbias->reg)
#define cbias_r16_table(reg, idx) reg_r16_table(cbias->reg, idx)
#define cbias_w16_table(val, reg, idx) reg_w16_table(val, cbias->reg, idx)
#define cbias_w16_table_mask(clear, set, reg, idx) reg_w16_table_mask(clear, set, cbias->reg, idx)
#define cbias_adr_table(reg, idx) adr_table(cbias->reg, idx)
/** CBIAS register structure */
struct fcsi_reg_cbias
{
/** Central Bias Register 0; #20 */
unsigned short ctrl0; /* 0x00 */
/** Central Bias Register 1; #21 */
unsigned short ctrl1; /* 0x01 */
/** Reserved */
unsigned short res_0; /* 0x03 */
};
#define FCSI_CBIAS_CTRL0 ((volatile unsigned short*)(FCSI_CBIAS_BASE + 0x00))
#define FCSI_CBIAS_CTRL1 ((volatile unsigned short*)(FCSI_CBIAS_BASE + 0x01))
#else /* __ASSEMBLY__ */
#define FCSI_CBIAS_CTRL0 (FCSI_CBIAS_BASE + 0x00)
#define FCSI_CBIAS_CTRL1 (FCSI_CBIAS_BASE + 0x01)
#endif /* __ASSEMBLY__ */
/* Fields of "Central Bias Register 0; #20" */
/** Measurement VCM Reference Current (cb_imeasvcm_50u)
Reference current for the output common mode voltage of the measurement switched cap buffer. Nominal Value 50uA */
#define CBIAS_CTRL0_IMVCM_MASK 0x0C00
/** field offset */
#define CBIAS_CTRL0_IMVCM_OFFSET 10
/** 100 % */
#define CBIAS_CTRL0_IMVCM_P100 0x0000
/** 80 % */
#define CBIAS_CTRL0_IMVCM_P80 0x0400
/** 90 % */
#define CBIAS_CTRL0_IMVCM_P90 0x0800
/** 110 % */
#define CBIAS_CTRL0_IMVCM_P110 0x0C00
/** 1550nm DAC Reference Current (cb_idac1550_50u)
Reference current input of the 1550nm R2R DAC Nominal Value 50uA */
#define CBIAS_CTRL0_IDAC1550_MASK 0x0300
/** field offset */
#define CBIAS_CTRL0_IDAC1550_OFFSET 8
/** 100 % */
#define CBIAS_CTRL0_IDAC1550_P100 0x0000
/** 80 % */
#define CBIAS_CTRL0_IDAC1550_P80 0x0100
/** 90 % */
#define CBIAS_CTRL0_IDAC1550_P90 0x0200
/** 110 % */
#define CBIAS_CTRL0_IDAC1550_P110 0x0300
/** TXBOSA Bias Current (cb_itxbosa_50u)
Bias current of the tx bosa block and reference current for the bias and modulation dac. Nominal Value 50uA */
#define CBIAS_CTRL0_ITXBOSA_MASK 0x00C0
/** field offset */
#define CBIAS_CTRL0_ITXBOSA_OFFSET 6
/** 100 % */
#define CBIAS_CTRL0_ITXBOSA_P100 0x0000
/** 50 % */
#define CBIAS_CTRL0_ITXBOSA_P50 0x0040
/** 75 % */
#define CBIAS_CTRL0_ITXBOSA_P75 0x0080
/** 125 % */
#define CBIAS_CTRL0_ITXBOSA_P125 0x00C0
/** VCM0V6 Bias Current (cb_i_bfdvcm0v6_50u)
Bias current for the common mode voltage generation, derived from the 1.0V supply Nominal Value 50uA */
#define CBIAS_CTRL0_IVCM0V6_MASK 0x0030
/** field offset */
#define CBIAS_CTRL0_IVCM0V6_OFFSET 4
/** 100 % */
#define CBIAS_CTRL0_IVCM0V6_P100 0x0000
/** 50 % */
#define CBIAS_CTRL0_IVCM0V6_P50 0x0010
/** 75 % */
#define CBIAS_CTRL0_IVCM0V6_P75 0x0020
/** 125 % */
#define CBIAS_CTRL0_IVCM0V6_P125 0x0030
/** VCM0V5 Bias Current (cb_ibfd_vcm0v5_25u)
Bias current for the common mode voltage generation, derived from the 1.0V supply Nominal Value 25uA */
#define CBIAS_CTRL0_IVCM0V5_MASK 0x000C
/** field offset */
#define CBIAS_CTRL0_IVCM0V5_OFFSET 2
/** 100 % */
#define CBIAS_CTRL0_IVCM0V5_P100 0x0000
/** 50 % */
#define CBIAS_CTRL0_IVCM0V5_P50 0x0004
/** 75 % */
#define CBIAS_CTRL0_IVCM0V5_P75 0x0008
/** 125 % */
#define CBIAS_CTRL0_IVCM0V5_P125 0x000C
/** BFD Bias Current (cb_ibfd_50u)
Bias current for the bfd block and for the offset and level DACs inside the bfd module. Nominal Value 50uA */
#define CBIAS_CTRL0_IBFD_MASK 0x0003
/** field offset */
#define CBIAS_CTRL0_IBFD_OFFSET 0
/** 100 % */
#define CBIAS_CTRL0_IBFD_P100 0x0000
/** 50 % */
#define CBIAS_CTRL0_IBFD_P50 0x0001
/** 75 % */
#define CBIAS_CTRL0_IBFD_P75 0x0002
/** 125 % */
#define CBIAS_CTRL0_IBFD_P125 0x0003
/* Fields of "Central Bias Register 1; #21" */
/** Reference Current Trimming (cb_ui_ref_trimm)
Change the reference currents for the dacs and adc reference. */
#define CBIAS_CTRL1_UIRT_MASK 0xF000
/** field offset */
#define CBIAS_CTRL1_UIRT_OFFSET 12
/** 100.0 % */
#define CBIAS_CTRL1_UIRT_P100D0 0x0000
/** 102.4 % */
#define CBIAS_CTRL1_UIRT_P102D4 0x1000
/** 105.6 % */
#define CBIAS_CTRL1_UIRT_P105D6 0x2000
/** 108.8 % */
#define CBIAS_CTRL1_UIRT_P108D8 0x3000
/** 111.2 % */
#define CBIAS_CTRL1_UIRT_P111D2 0x4000
/** 115.2 % */
#define CBIAS_CTRL1_UIRT_P115D2 0x5000
/** 118.4 % */
#define CBIAS_CTRL1_UIRT_P118D4 0x6000
/** 122.4 % */
#define CBIAS_CTRL1_UIRT_P122D4 0x7000
/** 97.6 % */
#define CBIAS_CTRL1_UIRT_P97D6 0x8000
/** 95.2 % */
#define CBIAS_CTRL1_UIRT_P95D2 0x9000
/** 92.0 % */
#define CBIAS_CTRL1_UIRT_P92D0 0xA000
/** 88.8 % */
#define CBIAS_CTRL1_UIRT_P88D8 0xB000
/** 85.6 % */
#define CBIAS_CTRL1_UIRT_P85D6 0xC000
/** 83.2 % */
#define CBIAS_CTRL1_UIRT_P83D2 0xD000
/** 80.0 % */
#define CBIAS_CTRL1_UIRT_P80D0 0xE000
/** 78.0 % */
#define CBIAS_CTRL1_UIRT_P78D0 0xF000
/** Bias and Calibration Current Trimming (cb_ui_conv_trimm)
Change the bias currents and the calibration currents. */
#define CBIAS_CTRL1_UICT_MASK 0x0F00
/** field offset */
#define CBIAS_CTRL1_UICT_OFFSET 8
/** 100.0 % */
#define CBIAS_CTRL1_UICT_P100D0 0x0000
/** 102.4 % */
#define CBIAS_CTRL1_UICT_P102D4 0x0100
/** 105.6 % */
#define CBIAS_CTRL1_UICT_P105D6 0x0200
/** 108.8 % */
#define CBIAS_CTRL1_UICT_P108D8 0x0300
/** 111.2 % */
#define CBIAS_CTRL1_UICT_P111D2 0x0400
/** 115.2 % */
#define CBIAS_CTRL1_UICT_P115D2 0x0500
/** 118.4 % */
#define CBIAS_CTRL1_UICT_P118D4 0x0600
/** 122.4 % */
#define CBIAS_CTRL1_UICT_P122D4 0x0700
/** 97.6 % */
#define CBIAS_CTRL1_UICT_P97D6 0x0800
/** 95.2 % */
#define CBIAS_CTRL1_UICT_P95D2 0x0900
/** 92.0 % */
#define CBIAS_CTRL1_UICT_P92D0 0x0A00
/** 88.8 % */
#define CBIAS_CTRL1_UICT_P88D8 0x0B00
/** 85.6 % */
#define CBIAS_CTRL1_UICT_P85D6 0x0C00
/** 83.2 % */
#define CBIAS_CTRL1_UICT_P83D2 0x0D00
/** 80.0 % */
#define CBIAS_CTRL1_UICT_P80D0 0x0E00
/** 78.0 % */
#define CBIAS_CTRL1_UICT_P78D0 0x0F00
/** MM bias prog (cb_prog_300u)
. */
#define CBIAS_CTRL1_MCAL 0x0080
/** Bandgap Temperature Coefficient (cb_bgp_temp)
This value is represented as 2s-complement. So, it reaches from 111 (negative maximum) via 000 (neutral=default) to 011 (positive maximum). */
#define CBIAS_CTRL1_BGPT_MASK 0x0070
/** field offset */
#define CBIAS_CTRL1_BGPT_OFFSET 4
/** Central Biasing operating mode (cb_pd) */
#define CBIAS_CTRL1_PD 0x0008
/** Powerup. */
#define CBIAS_CTRL1_PD_PU 0x0000
/** Bandgap Reference Voltage (cb_bgp_abs)
Reference voltage of the bandgap. */
#define CBIAS_CTRL1_BGPV_MASK 0x0007
/** field offset */
#define CBIAS_CTRL1_BGPV_OFFSET 0
/** 502 mV */
#define CBIAS_CTRL1_BGPV_MV502 0x0000
/** 515 mV */
#define CBIAS_CTRL1_BGPV_MV515 0x0001
/** 528 mV */
#define CBIAS_CTRL1_BGPV_MV528 0x0002
/** 541 mV */
#define CBIAS_CTRL1_BGPV_MV541 0x0003
/** 489 mV */
#define CBIAS_CTRL1_BGPV_MV489 0x0004
/** 476 mV */
#define CBIAS_CTRL1_BGPV_MV476 0x0005
/** 463 mV */
#define CBIAS_CTRL1_BGPV_MV463 0x0006
/** 450 mV */
#define CBIAS_CTRL1_BGPV_MV450 0x0007
/*! @} */ /* CBIAS_REGISTER */
#endif /* _drv_optic_reg_fcsi_cbias_h */

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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_fcsi_mm_h
#define _drv_optic_reg_fcsi_mm_h
/** \addtogroup MM_REGISTER
@{
*/
#ifndef __ASSEMBLY__
/* access macros */
#define mm_r16(reg) reg_r16(&mm->reg)
#define mm_w16(val, reg) reg_w16(val, &mm->reg)
#define mm_w16_mask(clear, set, reg) reg_w16_mask(clear, set, &mm->reg)
#define mm_r16_table(reg, idx) reg_r16_table(mm->reg, idx)
#define mm_w16_table(val, reg, idx) reg_w16_table(val, mm->reg, idx)
#define mm_w16_table_mask(clear, set, reg, idx) reg_w16_table_mask(clear, set, mm->reg, idx)
#define mm_adr_table(reg, idx) adr_table(mm->reg, idx)
/** MM register structure */
struct fcsi_reg_mm
{
/** Measurement Module Control Register; #14 */
unsigned short ctrl; /* 0x00 */
};
#define FCSI_MM_CTRL ((volatile unsigned short*)(FCSI_MM_BASE + 0x00))
#else /* __ASSEMBLY__ */
#define FCSI_MM_CTRL (FCSI_MM_BASE + 0x00)
#endif /* __ASSEMBLY__ */
/* Fields of "Measurement Module Control Register; #14" */
/** Invert clock (cap_clk_sel)
invert sample clock of sc buffer () */
#define MM_CTRL_CINV 0x0080
/** NOT inverted clk for sc buffer. */
#define MM_CTRL_CINV_NINV_sc 0x0000
/** inverted clk for sc buffer. */
#define MM_CTRL_CINV_INV_sc 0x0080
/** OPAMP Bias Current Select (mm_iref_red) */
#define MM_CTRL_OPBIAS 0x0040
/** Default Operation. */
#define MM_CTRL_OPBIAS_DEF 0x0000
/** Reduce bias current of the opamp. */
#define MM_CTRL_OPBIAS_RED 0x0040
/** Reference Voltage Block Enable (mm_en_ref1v0)
Enables the reference voltage block. */
#define MM_CTRL_REFEN 0x0020
/** Disable */
#define MM_CTRL_REFEN_DIS 0x0000
/** Enable */
#define MM_CTRL_REFEN_EN 0x0020
/** Feedback Point Select (mm_sel_fb) */
#define MM_CTRL_FBSEL 0x0010
/** Feedback is taken at the pad. */
#define MM_CTRL_FBSEL_PAD 0x0000
/** Feedback is taken at the output of the opamp. */
#define MM_CTRL_FBSEL_OPAMP 0x0010
/** Reference Voltage Select (mm_vsel)
Select the reference voltage of the external thermistor. */
#define MM_CTRL_RVS_MASK 0x000C
/** field offset */
#define MM_CTRL_RVS_OFFSET 2
/** 0.93 Volt */
#define MM_CTRL_RVS_V093 0x0000
/** 0.99 Volt */
#define MM_CTRL_RVS_V099 0x0004
/** 1.05 Volt */
#define MM_CTRL_RVS_V105 0x0008
/** 1.175 Volt */
#define MM_CTRL_RVS_V1175 0x000C
/** Test Input N (mm_test_inn)
Enables the positive test input */
#define MM_CTRL_TINN 0x0002
/** Disable */
#define MM_CTRL_TINN_DIS 0x0000
/** Enable */
#define MM_CTRL_TINN_EN 0x0002
/** Test Input P (mm_test_inp)
Enables the positive test input */
#define MM_CTRL_TINP 0x0001
/** Disable */
#define MM_CTRL_TINP_DIS 0x0000
/** Enable */
#define MM_CTRL_TINP_EN 0x0001
/*! @} */ /* MM_REGISTER */
#endif /* _drv_optic_reg_fcsi_mm_h */

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src/drv_optic_reg_fcsi_rxbosa.h Normal file
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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_fcsi_rxbosa_h
#define _drv_optic_reg_fcsi_rxbosa_h
/** \addtogroup RXBOSA_REGISTER
@{
*/
#ifndef __ASSEMBLY__
/* access macros */
#define rxbosa_r16(reg) reg_r16(&rxbosa->reg)
#define rxbosa_w16(val, reg) reg_w16(val, &rxbosa->reg)
#define rxbosa_w16_mask(clear, set, reg) reg_w16_mask(clear, set, &rxbosa->reg)
#define rxbosa_r16_table(reg, idx) reg_r16_table(rxbosa->reg, idx)
#define rxbosa_w16_table(val, reg, idx) reg_w16_table(val, rxbosa->reg, idx)
#define rxbosa_w16_table_mask(clear, set, reg, idx) reg_w16_table_mask(clear, set, rxbosa->reg, idx)
#define rxbosa_adr_table(reg, idx) adr_table(rxbosa->reg, idx)
/** RXBOSA register structure */
struct fcsi_reg_rxbosa
{
/** RX Bosa Module Control Register; #11 */
unsigned short ctrl; /* 0x00 */
};
#define FCSI_RXBOSA_CTRL ((volatile unsigned short*)(FCSI_RXBOSA_BASE + 0x00))
#else /* __ASSEMBLY__ */
#define FCSI_RXBOSA_CTRL (FCSI_RXBOSA_BASE + 0x00)
#endif /* __ASSEMBLY__ */
/* Fields of "RX Bosa Module Control Register; #11" */
/** Comparator 3 Operating Mode (rx_pd_comp3) */
#define RXBOSA_CTRL_C3OM 0x4000
/** Powerup */
#define RXBOSA_CTRL_C3OM_PU 0x0000
/** Powerdown */
#define RXBOSA_CTRL_C3OM_PD 0x4000
/** Data Lo Comparator Operating Mode (rx_pd_comp_data_lo)
*/
#define RXBOSA_CTRL_DLCOM 0x2000
/** Powerup */
#define RXBOSA_CTRL_DLCOM_PU 0x0000
/** Powerdown */
#define RXBOSA_CTRL_DLCOM_PD 0x2000
/** Timing Shell Clock Inversion (rx_bosa_clk_edge_sel)
Inverts the divide by eight clock of the timingshell. */
#define RXBOSA_CTRL_CINV 0x1000
/** rising edge used inside the timing shell. */
#define RXBOSA_CTRL_CINV_NINV 0x0000
/** inverted clk is used inside the timing shell. */
#define RXBOSA_CTRL_CINV_INV 0x1000
/** Reset (rx_bosa_rst)
Apply reset to demultiplexers. */
#define RXBOSA_CTRL_RST 0x0800
/** No Reset */
#define RXBOSA_CTRL_RST_NRST 0x0000
/** Test DAC Select (rx_bosa_testdacx)
select the DAC output, which is fed to the measurement module. */
#define RXBOSA_CTRL_TDS_MASK 0x0700
/** field offset */
#define RXBOSA_CTRL_TDS_OFFSET 8
/** No DAC is selected. */
#define RXBOSA_CTRL_TDS_NONE 0x0000
/** Monitor DAC is selected. */
#define RXBOSA_CTRL_TDS_MON 0x0100
/** Datalo DAC is selected. */
#define RXBOSA_CTRL_TDS_DLO 0x0200
/** Datahi DAC is selected. */
#define RXBOSA_CTRL_TDS_DHI 0x0300
/** Zero DAC is selected. */
#define RXBOSA_CTRL_TDS_ZERO 0x0400
/** CDR Monitor (rx_bosa_cdr_off_monitor) */
#define RXBOSA_CTRL_CDRM 0x0080
/** Default Operation. */
#define RXBOSA_CTRL_CDRM_DEF 0x0000
/** Clock generation outputs (div2, div4) are 0. */
#define RXBOSA_CTRL_CDRM_OFF 0x0080
/** CDR DFE (rx_bosa_cdr_off_dfe) */
#define RXBOSA_CTRL_CDRD 0x0040
/** Default Operation. */
#define RXBOSA_CTRL_CDRD_DEF 0x0000
/** Clock generation outputs (div2, div4) are 0. */
#define RXBOSA_CTRL_CDRD_OFF 0x0040
/** CDR Fall (rx_bosa_cdr_off_fall) */
#define RXBOSA_CTRL_CDRF 0x0020
/** Default Operation. */
#define RXBOSA_CTRL_CDRF_DEF 0x0000
/** Clock generation outputs (div2, div4) are 0. */
#define RXBOSA_CTRL_CDRF_OFF 0x0020
/** CDR Rise (rx_bosa_cdr_off_rise) */
#define RXBOSA_CTRL_CDRR 0x0010
/** Default Operation. */
#define RXBOSA_CTRL_CDRR_DEF 0x0000
/** Clock generation outputs (div2, div4) are 0. */
#define RXBOSA_CTRL_CDRR_OFF 0x0010
/** Input Stage Operating Mode
Disabling is done via cascode transistors (rx_bosa_sgmii_pd_i). */
#define RXBOSA_CTRL_ISOM 0x0008
/** Powerup */
#define RXBOSA_CTRL_ISOM_PU 0x0000
/** Powerdown */
#define RXBOSA_CTRL_ISOM_PD 0x0008
/** Bypass Leakage Compensation OTA Datahi (rx_bosabyp_leak_ota_datahi) */
#define RXBOSA_CTRL_BLCH 0x0004
/** No bypass */
#define RXBOSA_CTRL_BLCH_NBYP 0x0000
/** Bypass */
#define RXBOSA_CTRL_BLCH_BYP 0x0004
/** Bypass Leakage Compensation OTA Datalo (rx_bosa_byp_leak_ota_datalo) */
#define RXBOSA_CTRL_BLCL 0x0002
/** No bypass */
#define RXBOSA_CTRL_BLCL_NBYP 0x0000
/** Bypass */
#define RXBOSA_CTRL_BLCL_BYP 0x0002
/** Bypass Leakage Compensation OTA Monitor (rx_bosa_byp_leak_ota_monitor) */
#define RXBOSA_CTRL_BLCM 0x0001
/** No bypass */
#define RXBOSA_CTRL_BLCM_NBYP 0x0000
/** Bypass */
#define RXBOSA_CTRL_BLCM_BYP 0x0001
/*! @} */ /* RXBOSA_REGISTER */
#endif /* _drv_optic_reg_fcsi_rxbosa_h */

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src/drv_optic_reg_fcsi_rxomu.h Normal file
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/******************************************************************************
Copyright (c) 2011
Lantiq Deutschland GmbH
For licensing information, see the file 'LICENSE' in the root folder of
this software module.
******************************************************************************/
#ifndef _drv_optic_reg_fcsi_rxomu_h
#define _drv_optic_reg_fcsi_rxomu_h
/** \addtogroup RXOMU_REGISTER
@{
*/
#ifndef __ASSEMBLY__
/* access macros */
#define rxomu_r16(reg) reg_r16(&rxomu->reg)
#define rxomu_w16(val, reg) reg_w16(val, &rxomu->reg)
#define rxomu_w16_mask(clear, set, reg) reg_w16_mask(clear, set, &rxomu->reg)
#define rxomu_r16_table(reg, idx) reg_r16_table(rxomu->reg, idx)
#define rxomu_w16_table(val, reg, idx) reg_w16_table(val, rxomu->reg, idx)
#define rxomu_w16_table_mask(clear, set, reg, idx) reg_w16_table_mask(clear, set, rxomu->reg, idx)
#define rxomu_adr_table(reg, idx) adr_table(rxomu->reg, idx)
/** RXOMU register structure */
struct fcsi_reg_rxomu
{
/** RX Omu Module Control Register; #13 */
unsigned short ctrl; /* 0x00 */
};
#define FCSI_RXOMU_CTRL ((volatile unsigned short*)(FCSI_RXOMU_BASE + 0x00))
#else /* __ASSEMBLY__ */
#define FCSI_RXOMU_CTRL (FCSI_RXOMU_BASE + 0x00)
#endif /* __ASSEMBLY__ */
/* Fields of "RX Omu Module Control Register; #13" */
/** Test DAC Select (rx_omu_test_dac)
select whether the DAC output is fed to the measurement module. */
#define RXOMU_CTRL_TDS 0x0010
/** No DAC is selected. */
#define RXOMU_CTRL_TDS_NONE 0x0000
/** DAC is selected. */
#define RXOMU_CTRL_TDS_DAC 0x0010
/** Clock Inversion (rx_omu_clk_edge_sel)
Inverts the divide by eight clock of the timingshell. */
#define RXOMU_CTRL_CINV 0x0008
/** rising edge used inside the timing shell. */
#define RXOMU_CTRL_CINV_NINV 0x0000
/** inverted clk is used inside the timing shell. */
#define RXOMU_CTRL_CINV_INV 0x0008
/** Clock/Data Recovery (rx_omu_cdr_off) */
#define RXOMU_CTRL_CDR 0x0004
/** Default Operation. */
#define RXOMU_CTRL_CDR_DEF 0x0000
/** Clock generation outputs (div2, div4) are 0. */
#define RXOMU_CTRL_CDR_OFF 0x0004
/** Bypass Leakage Compensation OTA (rx_omu_byp_leak_ota) */
#define RXOMU_CTRL_BLOC 0x0002
/** No bypass */
#define RXOMU_CTRL_BLOC_NBYP 0x0000
/** Bypass */
#define RXOMU_CTRL_BLOC_BYP 0x0002
/** Input Stage Operating Mode (rx_omu_sgmii_pd)
Disabling is done via cascode transistors. */
#define RXOMU_CTRL_ISOM 0x0001
/** Powerup. */
#define RXOMU_CTRL_ISOM_PU 0x0000
/** Powerdown. */
#define RXOMU_CTRL_ISOM_PD 0x0001
/*! @} */ /* RXOMU_REGISTER */
#endif /* _drv_optic_reg_fcsi_rxomu_h */

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