613 lines
27 KiB
C
613 lines
27 KiB
C
/******************************************************************************
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Copyright (c) 2012
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Lantiq Deutschland GmbH
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For licensing information, see the file 'LICENSE' in the root folder of
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this software module.
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******************************************************************************/
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#ifndef _drv_onu_reg_status_h
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#define _drv_onu_reg_status_h
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/** \addtogroup STATUS_REGISTER
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@{
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*/
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/* access macros */
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#define status_r32(reg) reg_r32(&status->reg)
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#define status_w32(val, reg) reg_w32(val, &status->reg)
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#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg)
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#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx)
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#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx)
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#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx)
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#define status_adr_table(reg, idx) adr_table(status->reg, idx)
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/** STATUS register structure */
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struct onu_reg_status
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{
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/** Reserved */
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unsigned int res_0[3]; /* 0x00000000 */
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/** Chip Identification Register */
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unsigned int chipid; /* 0x0000000C */
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/** Chip Location Register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int chiploc; /* 0x00000010 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red0; /* 0x00000014 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red1; /* 0x00000018 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red2; /* 0x0000001C */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red3; /* 0x00000020 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red4; /* 0x00000024 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red5; /* 0x00000028 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red6; /* 0x0000002C */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red7; /* 0x00000030 */
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/** Redundancy register
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int red8; /* 0x00000034 */
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/** SPARE fuse register 0
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int fuse0; /* 0x00000038 */
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/** Fuses for Analog modules
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int analog; /* 0x0000003C */
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/** Configuration fuses for drivers and pll
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int config; /* 0x00000040 */
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/** SPARE fuse register 1
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Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
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unsigned int fuse1; /* 0x00000044 */
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/** Configuration for sbs0 rambist */
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unsigned int mbcfg; /* 0x00000048 */
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/** sbs0 bist result and debug data */
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unsigned int mbdata; /* 0x0000004C */
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/** Reserved */
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unsigned int res_1[12]; /* 0x00000050 */
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};
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/* Fields of "Chip Identification Register" */
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/** Chip Version Number
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Version number is a constant field and can be changed by Redesign only. The chip version is coded by 3 characters XvY while v is the version, X = A,B,C and Y = 1,2,3 they will be coded in the CONFIG register field SUBVERS). */
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#define STATUS_CHIPID_VERSION_MASK 0xF0000000
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/** field offset */
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#define STATUS_CHIPID_VERSION_OFFSET 28
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/** Part Number, Constant Part
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The Part Number is fixed to 016Bhex. */
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#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000
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/** field offset */
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#define STATUS_CHIPID_PARTNR_OFFSET 12
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/** Manufacturer ID
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The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */
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#define STATUS_CHIPID_MANID_MASK 0x00000FFE
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/** field offset */
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#define STATUS_CHIPID_MANID_OFFSET 1
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/** Constant bit
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The value of bit field CONST1 is fixed to 1hex */
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#define STATUS_CHIPID_CONST1 0x00000001
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/* Fields of "Chip Location Register" */
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/** Chip Lot ID */
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#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000
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/** field offset */
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#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16
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/** Chip X Coordinate */
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#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00
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/** field offset */
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#define STATUS_CHIPLOC_CHIPX_OFFSET 8
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/** Chip Y Coordinate */
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#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF
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/** field offset */
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#define STATUS_CHIPLOC_CHIPY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED0_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED1_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED2_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED3_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED4_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED5_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED6_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED7_REDUNDANCY_OFFSET 0
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/* Fields of "Redundancy register" */
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/** Redundancy
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redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
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#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF
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/** field offset */
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#define STATUS_RED8_REDUNDANCY_OFFSET 0
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/* Fields of "SPARE fuse register 0" */
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/** Soft fuse control
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Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */
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#define STATUS_FUSE0_SFC 0x80000000
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/* Not selected
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#define STATUS_FUSE0_SFC_NSEL 0x00000000 */
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/** Selected */
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#define STATUS_FUSE0_SFC_SEL 0x80000000
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/** Soft control MBCFG
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Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */
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#define STATUS_FUSE0_SC_MBCFG 0x40000000
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/* Not selected
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#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */
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/** Selected */
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#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000
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/** Device Type
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different device types are coded in this fuse field */
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#define STATUS_FUSE0_F0_MASK 0x3C000000
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/** field offset */
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#define STATUS_FUSE0_F0_OFFSET 26
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/** FALCOND */
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#define STATUS_FUSE0_F0_FALCOND 0x00000000
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/** FALCONV */
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#define STATUS_FUSE0_F0_FALCONV 0x04000000
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/** FALCONM */
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#define STATUS_FUSE0_F0_FALCONM 0x08000000
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/** SFP */
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#define STATUS_FUSE0_F0_FALCONS 0x0C000000
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/** all other codes reserved for future applications */
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#define STATUS_FUSE0_F0_reserved 0x10000000
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/** VCALMM20 Voltage Reference
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Voltage Reference for calibration via R and constant current (20 uA) */
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#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000
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/** field offset */
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#define STATUS_FUSE0_VCALMM20_OFFSET 20
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/** VCALMM100 Voltage Reference
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Voltage Reference for calibration via R and constant current (100 uA) */
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#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000
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/** field offset */
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#define STATUS_FUSE0_VCALMM100_OFFSET 14
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/** VCALMM400 Voltage Reference
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Voltage Reference for calibration via R and constant current (400 uA) */
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#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00
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/** field offset */
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#define STATUS_FUSE0_VCALMM400_OFFSET 8
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/** RCALMM R error correction
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The resistance deviation from ideal R (1000 Ohm) */
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#define STATUS_FUSE0_RCALMM_MASK 0x000000FF
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/** field offset */
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#define STATUS_FUSE0_RCALMM_OFFSET 0
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/* Fields of "Fuses for Analog modules" */
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/** Status of written FUSES
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Defines which Fuses are activated */
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#define STATUS_ANALOG_FS_MASK 0xE0000000
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/** field offset */
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#define STATUS_ANALOG_FS_OFFSET 29
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/** A11 format, only VBGP and IREFBGP fused, DRIVE and BIAS DAC - 4 bit */
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#define STATUS_ANALOG_FS_FS0 0x00000000
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/** new format, VBGP, IREFBGP, DRIVE dac (5bit) and BIAS dac (5bit) fused */
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#define STATUS_ANALOG_FS_FS1 0x20000000
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/** All other codes reserved for future applications */
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#define STATUS_ANALOG_FS_FS2 0x40000000
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/** reserved Analog eFuses
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Reserved Register contains information stored in eFuses needed for the analog modules */
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#define STATUS_ANALOG_A0_MASK 0x1C000000
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/** field offset */
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#define STATUS_ANALOG_A0_OFFSET 26
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/** Absolut Temperature
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Temperature ERROR */
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#define STATUS_ANALOG_TEMPMM_MASK 0x03F00000
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/** field offset */
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#define STATUS_ANALOG_TEMPMM_OFFSET 20
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/** Drive DAC Gain */
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#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000F8000
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/** field offset */
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#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 15
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/** Bias Voltage Generation
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voltage dependency */
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#define STATUS_ANALOG_VBGP_MASK 0x00007000
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/** field offset */
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#define STATUS_ANALOG_VBGP_OFFSET 12
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/** Bias Current Generation */
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#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00
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/** field offset */
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#define STATUS_ANALOG_IREFBGP_OFFSET 8
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/** Bias Voltage Generation
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temperature dependency */
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#define STATUS_ANALOG_TBGP_MASK 0x000000E0
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/** field offset */
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#define STATUS_ANALOG_TBGP_OFFSET 5
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/** BIAS DAC Gain */
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#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000001F
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/** field offset */
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#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0
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/* Fields of "Configuration fuses for drivers and pll" */
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/** ddr PU driver
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ddr pullup driver strength adjustment */
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#define STATUS_CONFIG_DDRPU_MASK 0xC0000000
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/** field offset */
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#define STATUS_CONFIG_DDRPU_OFFSET 30
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/** ddr PD driver
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ddr pulldown driver strength adjustment */
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#define STATUS_CONFIG_DDRPD_MASK 0x30000000
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/** field offset */
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#define STATUS_CONFIG_DDRPD_OFFSET 28
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/** Authentification Unit enable
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This bit can only be set via eFuse and enables the authentification unit. */
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#define STATUS_CONFIG_SHA1EN 0x08000000
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/* Not selected
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#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */
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/** Selected */
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#define STATUS_CONFIG_SHA1EN_SEL 0x08000000
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/** Encryption Unit enable
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This bit can only be set via eFuse and enables the encryption unit. */
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#define STATUS_CONFIG_AESEN 0x04000000
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/* Not selected
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#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */
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/** Selected */
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#define STATUS_CONFIG_AESEN_SEL 0x04000000
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/** Subversion Number
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The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. The chip version is coded by 3 characters XvY; while v is the version coded in CHIPID Register field VERSION. Following codes are defined: */
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#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000
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/** field offset */
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#define STATUS_CONFIG_SUBVERS_OFFSET 22
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/** 1. Design Version */
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#define STATUS_CONFIG_SUBVERS_Av1 0x00000000
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/** Av2 */
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#define STATUS_CONFIG_SUBVERS_Av2 0x00400000
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/** Av3 */
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#define STATUS_CONFIG_SUBVERS_Av3 0x00800000
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/** Av4 */
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#define STATUS_CONFIG_SUBVERS_Av4 0x00C00000
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/** Bv1 */
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#define STATUS_CONFIG_SUBVERS_Bv1 0x01000000
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/** PLL settings
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PLL settings for infrastructure block */
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#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000
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/** field offset */
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#define STATUS_CONFIG_PLLINFRA_OFFSET 12
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/** GPE frequency selection
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frequency selection of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz */
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#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00
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/** field offset */
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#define STATUS_CONFIG_GPEFREQ_OFFSET 10
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/** RM enable
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Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */
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#define STATUS_CONFIG_RME 0x00000200
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/* Not selected
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#define STATUS_CONFIG_RME_NSEL 0x00000000 */
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/** Selected */
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#define STATUS_CONFIG_RME_SEL 0x00000200
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/** RM settings
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Read Marging Settings for all VIRAGE Memories except GPE */
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#define STATUS_CONFIG_RM_MASK 0x000001E0
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/** field offset */
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#define STATUS_CONFIG_RM_OFFSET 5
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/** RM enable for GPE Memories
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Activates the Read Margin Settings defined in the RM Field */
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#define STATUS_CONFIG_RMEGPE 0x00000010
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/* Not selected
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#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */
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/** Selected */
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#define STATUS_CONFIG_RMEGPE_SEL 0x00000010
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/** RM settings for GPE Memories
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Read Marging Settings for VIRAGE Memories in GPE module */
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#define STATUS_CONFIG_RMGPE_MASK 0x0000000F
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/** field offset */
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#define STATUS_CONFIG_RMGPE_OFFSET 0
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/* Fields of "SPARE fuse register 1" */
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/** spare fuse1
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eFuses not assigned to hw/sw, at the moment reserved for TE */
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#define STATUS_FUSE1_F1_MASK 0xFFF00000
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/** field offset */
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#define STATUS_FUSE1_F1_OFFSET 20
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/** FREE_1
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used for future application */
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#define STATUS_FUSE1_FR1_MASK 0x000F0000
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/** field offset */
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#define STATUS_FUSE1_FR1_OFFSET 16
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/** DCDC 1V0 OFFSET
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offset error sense path */
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#define STATUS_FUSE1_OFFSET1V0DCDC_MASK 0x0000F800
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/** field offset */
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#define STATUS_FUSE1_OFFSET1V0DCDC_OFFSET 11
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/** DCDC APD OFFSET
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offset error sense path */
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#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000007C0
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/** field offset */
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#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6
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/** DCDC APD GAIN
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gain error sense path */
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#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F
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/** field offset */
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#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0
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/* Fields of "Configuration for sbs0 rambist" */
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/** do not use only for debugging on testsystem
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the GPE SW bist will be shorten to 32 memory locations when it would be enabled by bootmode config */
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#define STATUS_MBCFG_MB_DBG 0x02000000
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/* Disable
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#define STATUS_MBCFG_MB_DBG_DIS 0x00000000 */
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/** Enable */
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#define STATUS_MBCFG_MB_DBG_EN 0x02000000
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/** Disable asc monitoring during boot-up
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Bit is used to avoid asc output for reducing pattern count on testsystem */
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#define STATUS_MBCFG_ASC_DBGDIS 0x01000000
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/* Disable
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#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */
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/** Enable */
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#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000
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/** Descrambling Enable/Disable
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Enables Address and Data Descrambling for internal Memory Test */
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#define STATUS_MBCFG_DSC 0x00800000
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/* Disable
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#define STATUS_MBCFG_DSC_DIS 0x00000000 */
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/** Enable */
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#define STATUS_MBCFG_DSC_EN 0x00800000
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/** Enable repair mode
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When bit is set redundancy repair mode is activated */
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#define STATUS_MBCFG_REPAIR 0x00400000
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/* Disable
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#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */
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/** Enable */
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#define STATUS_MBCFG_REPAIR_EN 0x00400000
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/** DEBUG Mode */
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#define STATUS_MBCFG_DBG 0x00200000
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/* Disable
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#define STATUS_MBCFG_DBG_DIS 0x00000000 */
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/** Enable */
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#define STATUS_MBCFG_DBG_EN 0x00200000
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/** Retention Time
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Length oft the Retention Time */
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#define STATUS_MBCFG_RTIME_MASK 0x001C0000
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/** field offset */
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#define STATUS_MBCFG_RTIME_OFFSET 18
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/** retention mode is switched off */
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#define STATUS_MBCFG_RTIME_RET0 0x00000000
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/** Retention time 50 ms */
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#define STATUS_MBCFG_RTIME_RET50 0x00040000
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/** Retention time 60 ms */
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#define STATUS_MBCFG_RTIME_RET60 0x00080000
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/** Retention time 70 ms */
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#define STATUS_MBCFG_RTIME_RET70 0x000C0000
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/** Retention time 80 ms */
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#define STATUS_MBCFG_RTIME_RET80 0x00100000
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/** Retention time 90 ms */
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#define STATUS_MBCFG_RTIME_RET90 0x00140000
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/** Retention time 1000 ms */
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#define STATUS_MBCFG_RTIME_RET1000 0x00180000
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/** Test ID
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Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
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#define STATUS_MBCFG_TID_5_MASK 0x00038000
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/** field offset */
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#define STATUS_MBCFG_TID_5_OFFSET 15
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/** No test is performed */
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#define STATUS_MBCFG_TID_5_NONE 0x00000000
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/** March test */
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#define STATUS_MBCFG_TID_5_MARCH 0x00008000
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/** Checkerboard test */
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#define STATUS_MBCFG_TID_5_CHCK 0x00010000
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/** Hammer test */
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#define STATUS_MBCFG_TID_5_HAM 0x00018000
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/** Address decoder test */
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#define STATUS_MBCFG_TID_5_ADEC 0x00020000
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/** Write mask byte test */
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#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000
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/** Reserved */
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#define STATUS_MBCFG_TID_5_RES 0x00030000
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/** Test ID
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Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
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#define STATUS_MBCFG_TID_4_MASK 0x00007000
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/** field offset */
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#define STATUS_MBCFG_TID_4_OFFSET 12
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/** No test is performed */
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#define STATUS_MBCFG_TID_4_NONE 0x00000000
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/** March test */
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#define STATUS_MBCFG_TID_4_MARCH 0x00001000
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/** Checkerboard test */
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#define STATUS_MBCFG_TID_4_CHCK 0x00002000
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/** Hammer test */
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#define STATUS_MBCFG_TID_4_HAM 0x00003000
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/** Address decoder test */
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#define STATUS_MBCFG_TID_4_ADEC 0x00004000
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/** Write mask byte test */
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#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000
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/** Reserved */
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#define STATUS_MBCFG_TID_4_RES 0x00006000
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/** Test ID
|
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Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
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#define STATUS_MBCFG_TID_3_MASK 0x00000E00
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/** field offset */
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#define STATUS_MBCFG_TID_3_OFFSET 9
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/** No test is performed */
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#define STATUS_MBCFG_TID_3_NONE 0x00000000
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/** March test */
|
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#define STATUS_MBCFG_TID_3_MARCH 0x00000200
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/** Checkerboard test */
|
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#define STATUS_MBCFG_TID_3_CHCK 0x00000400
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/** Hammer test */
|
|
#define STATUS_MBCFG_TID_3_HAM 0x00000600
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/** Address decoder test */
|
|
#define STATUS_MBCFG_TID_3_ADEC 0x00000800
|
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/** Write mask byte test */
|
|
#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00
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/** Reserved */
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|
#define STATUS_MBCFG_TID_3_RES 0x00000C00
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/** Test ID
|
|
Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
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#define STATUS_MBCFG_TID_2_MASK 0x000001C0
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/** field offset */
|
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#define STATUS_MBCFG_TID_2_OFFSET 6
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/** No test is performed */
|
|
#define STATUS_MBCFG_TID_2_NONE 0x00000000
|
|
/** March test */
|
|
#define STATUS_MBCFG_TID_2_MARCH 0x00000040
|
|
/** Checkerboard test */
|
|
#define STATUS_MBCFG_TID_2_CHCK 0x00000080
|
|
/** Hammer test */
|
|
#define STATUS_MBCFG_TID_2_HAM 0x000000C0
|
|
/** Address decoder test */
|
|
#define STATUS_MBCFG_TID_2_ADEC 0x00000100
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|
/** Write mask byte test */
|
|
#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140
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|
/** Reserved */
|
|
#define STATUS_MBCFG_TID_2_RES 0x00000180
|
|
/** Test ID
|
|
Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
#define STATUS_MBCFG_TID_1_MASK 0x00000038
|
|
/** field offset */
|
|
#define STATUS_MBCFG_TID_1_OFFSET 3
|
|
/** No test is performed */
|
|
#define STATUS_MBCFG_TID_1_NONE 0x00000000
|
|
/** March test */
|
|
#define STATUS_MBCFG_TID_1_MARCH 0x00000008
|
|
/** Checkerboard test */
|
|
#define STATUS_MBCFG_TID_1_CHCK 0x00000010
|
|
/** Hammer test */
|
|
#define STATUS_MBCFG_TID_1_HAM 0x00000018
|
|
/** Address decoder test */
|
|
#define STATUS_MBCFG_TID_1_ADEC 0x00000020
|
|
/** Write mask byte test */
|
|
#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028
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|
/** Reserved */
|
|
#define STATUS_MBCFG_TID_1_RES 0x00000030
|
|
/** Test ID
|
|
Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
#define STATUS_MBCFG_TID_0_MASK 0x00000007
|
|
/** field offset */
|
|
#define STATUS_MBCFG_TID_0_OFFSET 0
|
|
/** No test is performed */
|
|
#define STATUS_MBCFG_TID_0_NONE 0x00000000
|
|
/** March test */
|
|
#define STATUS_MBCFG_TID_0_MARCH 0x00000001
|
|
/** Checkerboard test */
|
|
#define STATUS_MBCFG_TID_0_CHCK 0x00000002
|
|
/** Hammer test */
|
|
#define STATUS_MBCFG_TID_0_HAM 0x00000003
|
|
/** Address decoder test */
|
|
#define STATUS_MBCFG_TID_0_ADEC 0x00000004
|
|
/** Write mask byte test */
|
|
#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005
|
|
/** Reserved */
|
|
#define STATUS_MBCFG_TID_0_RES 0x00000006
|
|
|
|
/* Fields of "sbs0 bist result and debug data" */
|
|
/** BIST result and debug data
|
|
Stores additional debug information */
|
|
#define STATUS_MBDATA_DATA_MASK 0xFFFC0000
|
|
/** field offset */
|
|
#define STATUS_MBDATA_DATA_OFFSET 18
|
|
/** MBIST NOGO
|
|
The BIST failed and cannot be repaired due to many failure locations, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_5_NOGO 0x00020000
|
|
/** MBIST FAILED
|
|
The BIST failed but can be repaired, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_5_FAIL 0x00010000
|
|
/** MBIST PASSED
|
|
The BIST passed without any Failures, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_5_PASS 0x00008000
|
|
/** MBIST NOGO
|
|
The BIST failed and cannot be repaired due to many failure locations, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_4_NOGO 0x00004000
|
|
/** MBIST FAILED
|
|
The BIST failed but can be repaired, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_4_FAIL 0x00002000
|
|
/** MBIST PASSED
|
|
The BIST passed without any Failures, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_4_PASS 0x00001000
|
|
/** MBIST NOGO
|
|
The BIST failed and cannot be repaired due to many failure locations, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_3_NOGO 0x00000800
|
|
/** MBIST FAILED
|
|
The BIST failed but can be repaired, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_3_FAIL 0x00000400
|
|
/** MBIST PASSED
|
|
The BIST passed without any Failures, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_3_PASS 0x00000200
|
|
/** MBIST NOGO
|
|
The BIST failed and cannot be repaired due to many failure locations, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_2_NOGO 0x00000100
|
|
/** MBIST FAILED
|
|
The BIST failed but can be repaired, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_2_FAIL 0x00000080
|
|
/** MBIST PASSED
|
|
The BIST passed without any Failures, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_2_PASS 0x00000040
|
|
/** MBIST NOGO
|
|
The BIST failed and cannot be repaired due to many failure locations, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_1_NOGO 0x00000020
|
|
/** MBIST FAILED
|
|
The BIST failed but can be repaired, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_1_FAIL 0x00000010
|
|
/** MBIST PASSED
|
|
The BIST passed without any Failures, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_1_PASS 0x00000008
|
|
/** MBIST NOGO
|
|
The BIST failed and cannot be repaired due to many failure locations, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_0_NOGO 0x00000004
|
|
/** MBIST FAILED
|
|
The BIST failed but can be repaired, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_0_FAIL 0x00000002
|
|
/** MBIST PASSED
|
|
The BIST passed without any Failures, depends on the TID setting in the MBCFG register this bit will be set or not */
|
|
#define STATUS_MBDATA_TID_0_PASS 0x00000001
|
|
|
|
/*! @} */ /* STATUS_REGISTER */
|
|
|
|
#endif /* _drv_onu_reg_status_h */
|