431 lines
17 KiB
C
431 lines
17 KiB
C
/******************************************************************************
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Copyright (c) 2011
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Lantiq Deutschland GmbH
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For licensing information, see the file 'LICENSE' in the root folder of
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this software module.
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******************************************************************************/
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#ifndef _drv_onu_reg_octrll_h
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#define _drv_onu_reg_octrll_h
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/** \addtogroup OCTRLL_REGISTER
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@{
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*/
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/* access macros */
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#define octrll_r32(reg) reg_r32(&octrll->reg)
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#define octrll_w32(val, reg) reg_w32(val, &octrll->reg)
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#define octrll_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &octrll->reg)
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#define octrll_r32_table(reg, idx) reg_r32_table(octrll->reg, idx)
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#define octrll_w32_table(val, reg, idx) reg_w32_table(val, octrll->reg, idx)
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#define octrll_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, octrll->reg, idx)
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#define octrll_adr_table(reg, idx) adr_table(octrll->reg, idx)
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/** OCTRLL register structure */
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struct onu_reg_octrll
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{
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/** Control Register */
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unsigned int ctrl; /* 0x00000000 */
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/** Configuration Register */
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unsigned int cfg; /* 0x00000004 */
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/** Raw Control Register */
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unsigned int rawctrl; /* 0x00000008 */
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/** Raw Configuration Register 0
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Note: Modify only when RAWCTRL.RAWTX is disabled! */
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unsigned int rawcfg0; /* 0x0000000C */
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/** Raw Configuration Register 1
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Note: Modify only when RAWCTRL.RAWTX is disabled! */
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unsigned int rawcfg1; /* 0x00000010 */
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/** Timeout Configuration Register
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This Register holds the Timeout Configuration */
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unsigned int toutcfg; /* 0x00000014 */
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/** DMAR Control Register */
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unsigned int dctrl; /* 0x00000018 */
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/** Transmitted Bytes Counter (Low Part)
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This counter is metering the transmitted Bytes for the LAN Interface. First the low and then the high part must be read. */
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unsigned int txbcntl; /* 0x0000001C */
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/** Transmitted Bytes Counter (High Part)
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This counter is metering the transmitted Bytes for the LAN Interface. First the low and then the high part must be read. */
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unsigned int txbcnth; /* 0x00000020 */
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/** Transmitted Packets Counter
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This counter is metering the transmitted Packets for the LAN Interface. */
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unsigned int txpcnt; /* 0x00000024 */
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/** Transmitted Packets MINSIZE-64 Counter
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This counter is metering the transmitted Packets with MINSIZE to 64 Bytes for the LAN Interface. */
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unsigned int txp64cnt; /* 0x00000028 */
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/** Transmitted Packets 65-127 Counter
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This counter is metering the transmitted Packets with 65 to 127 Bytes for the LAN Interface. */
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unsigned int txp65cnt; /* 0x0000002C */
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/** Transmitted Packets 128-255 Counter
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This counter is metering the transmitted Packets with 128 to 255 Bytes for the LAN Interface. */
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unsigned int txp128cnt; /* 0x00000030 */
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/** Transmitted Packets 256-511 Counter
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This counter is metering the transmitted Packets with 256 to 511 Bytes for the LAN Interface. */
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unsigned int txp256cnt; /* 0x00000034 */
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/** Transmitted Packets 512-1023 Counter
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This counter is metering the transmitted Packets with 512 to 1023 Bytes for the LAN Interface. */
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unsigned int txp512cnt; /* 0x00000038 */
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/** Transmitted Packets 1024-1518 Counter
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This counter is metering the transmitted Packets with 1024 to 1518 Bytes for the LAN Interface. */
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unsigned int txp1024cnt; /* 0x0000003C */
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/** Transmitted Packets 1519-MAXSIZE Counter
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This counter is metering the transmitted Packets with 1519 to MAXSIZE Bytes for the LAN Interface. */
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unsigned int txp1519cnt; /* 0x00000040 */
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/** DMAR Pointer Register
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This read only Register mirrors the DMAR.PTR Register and may be used for debugging. */
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unsigned int dptr; /* 0x00000044 */
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/** DMAR Context Register
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This read only Register mirrors the DMAR.CONTEXT Register and may be used for debugging. */
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unsigned int dcontext; /* 0x00000048 */
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/** State Register
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This Register shows the internal state. */
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unsigned int state; /* 0x0000004C */
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/** Reserved */
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unsigned int res_0[12]; /* 0x00000050 */
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/** IRN Capture Register
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This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
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unsigned int irncr; /* 0x00000080 */
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/** IRN Interrupt Control Register
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A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
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unsigned int irnicr; /* 0x00000084 */
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/** IRN Interrupt Enable Register
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This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
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unsigned int irnen; /* 0x00000088 */
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/** Reserved */
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unsigned int res_1[29]; /* 0x0000008C */
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};
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/* Fields of "Control Register" */
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/** Retransmission Enable
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This bit enables the retransmission mode.The value is stored in a shadow register and assigned to the internal register before the start of a packet.A read returns the shadowed value. */
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#define OCTRLL_CTRL_RTX 0x00000004
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/* Disable
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#define OCTRLL_CTRL_RTX_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_CTRL_RTX_EN 0x00000004
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/** Timeout Enable
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Note: Modify only when ACT is disabled!If set, the queues attached to this interface will be actively emptied after the programmable period TOUTCFG.TOUTVALUE of inactivity. */
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#define OCTRLL_CTRL_TOUTEN 0x00000002
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/* Disable
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#define OCTRLL_CTRL_TOUTEN_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_CTRL_TOUTEN_EN 0x00000002
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/** Activate Core State Machine
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This bit enables the OCTRL state machine.When deactivating, the current Ethernet frame is finished and then the OCTRL is on hold.Note 1: All static configuration must be done before activation.Note 2: Deactivation is for debugging only. act - deact - act is prohibited! */
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#define OCTRLL_CTRL_ACT 0x00000001
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/* Disable
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#define OCTRLL_CTRL_ACT_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_CTRL_ACT_EN 0x00000001
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/* Fields of "Configuration Register" */
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/** Egress Port Number
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Note: Modify only when CTRL.ACT is disabled!Assigned EPN0 to 71: Implemented EPN range71: No EPN assigned */
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#define OCTRLL_CFG_EPN_MASK 0x0000007F
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/** field offset */
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#define OCTRLL_CFG_EPN_OFFSET 0
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/* Fields of "Raw Control Register" */
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/** Transmit Frame in Raw Mode
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Note: Modify only when disabled, i.e. previous transmission is finished!Triggers Raw transmission when set by CPU.Acknowledge Raw transmission when reset by OCTRL. */
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#define OCTRLL_RAWCTRL_RAWTX 0x00000001
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/* Disable
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#define OCTRLL_RAWCTRL_RAWTX_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_RAWCTRL_RAWTX_EN 0x00000001
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/* Fields of "Raw Configuration Register 0" */
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/** Head LSA
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Head Logical Segment Address */
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#define OCTRLL_RAWCFG0_HLSA_MASK 0x00007FFF
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/** field offset */
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#define OCTRLL_RAWCFG0_HLSA_OFFSET 0
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/* Fields of "Raw Configuration Register 1" */
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/** Header Length
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Length of the Packet Header */
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#define OCTRLL_RAWCFG1_HDRL_MASK 0xFF000000
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/** field offset */
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#define OCTRLL_RAWCFG1_HDRL_OFFSET 24
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/** Offset
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Offset into Frame Segment(s) */
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#define OCTRLL_RAWCFG1_OFFS_MASK 0x00FF0000
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/** field offset */
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#define OCTRLL_RAWCFG1_OFFS_OFFSET 16
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/** Body Length
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Length of the Packet Body w/o FCS */
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#define OCTRLL_RAWCFG1_BDYL_MASK 0x0000FFFF
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/** field offset */
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#define OCTRLL_RAWCFG1_BDYL_OFFSET 0
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/* Fields of "Timeout Configuration Register" */
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/** Timeout Value
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This value determines the time till the packet is dropped.0x0000: no timeout0x0001: approx. 9.15ms0xFFFF: approx. 600sNote: The values are based on 312.5MHz core clock frequency. */
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#define OCTRLL_TOUTCFG_TOUTVALUE_MASK 0x0000FFFF
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/** field offset */
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#define OCTRLL_TOUTCFG_TOUTVALUE_OFFSET 0
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/* Fields of "DMAR Control Register" */
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/** Free Queue
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FSQM Queue selection for LSA freeing. */
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#define OCTRLL_DCTRL_FQ 0x00000001
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/* Select Queue 0 (Note: Usage is prohibited!)
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#define OCTRLL_DCTRL_FQ_Q0 0x00000000 */
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/** Select Queue 1 (Default) */
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#define OCTRLL_DCTRL_FQ_Q1 0x00000001
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/* Fields of "Transmitted Bytes Counter (Low Part)" */
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/** Counter Value (Low)
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Byte Counter Value (Low Part) */
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#define OCTRLL_TXBCNTL_BCNTL_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXBCNTL_BCNTL_OFFSET 0
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/* Fields of "Transmitted Bytes Counter (High Part)" */
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/** Counter Value (High)
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Byte Counter Value (High Part) */
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#define OCTRLL_TXBCNTH_BCNTH_MASK 0x0000FFFF
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/** field offset */
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#define OCTRLL_TXBCNTH_BCNTH_OFFSET 0
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/* Fields of "Transmitted Packets Counter" */
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/** Counter Value
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Packet Counter Value */
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#define OCTRLL_TXPCNT_PCNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXPCNT_PCNT_OFFSET 0
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/* Fields of "Transmitted Packets MINSIZE-64 Counter" */
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/** Counter Value
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Packet MINSIZE-64 Counter Value */
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#define OCTRLL_TXP64CNT_P64CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP64CNT_P64CNT_OFFSET 0
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/* Fields of "Transmitted Packets 65-127 Counter" */
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/** Counter Value
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Packet 65-127 Counter Value */
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#define OCTRLL_TXP65CNT_P65CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP65CNT_P65CNT_OFFSET 0
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/* Fields of "Transmitted Packets 128-255 Counter" */
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/** Counter Value
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Packet 128-255 Counter Value */
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#define OCTRLL_TXP128CNT_P128CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP128CNT_P128CNT_OFFSET 0
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/* Fields of "Transmitted Packets 256-511 Counter" */
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/** Counter Value
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Packet 256-511 Counter Value */
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#define OCTRLL_TXP256CNT_P256CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP256CNT_P256CNT_OFFSET 0
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/* Fields of "Transmitted Packets 512-1023 Counter" */
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/** Counter Value
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Packet 512-1023 Counter Value */
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#define OCTRLL_TXP512CNT_P512CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP512CNT_P512CNT_OFFSET 0
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/* Fields of "Transmitted Packets 1024-1518 Counter" */
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/** Counter Value
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Packet 1024-1518 Counter Value */
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#define OCTRLL_TXP1024CNT_P1024CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP1024CNT_P1024CNT_OFFSET 0
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/* Fields of "Transmitted Packets 1519-MAXSIZE Counter" */
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/** Counter Value
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Packet 1519-MAXSIZE Counter Value */
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#define OCTRLL_TXP1519CNT_P1519CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define OCTRLL_TXP1519CNT_P1519CNT_OFFSET 0
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/* Fields of "DMAR Pointer Register" */
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/** Tail LSA
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Tail Logical Segment Address */
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#define OCTRLL_DPTR_TLSA_MASK 0x7FFF0000
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/** field offset */
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#define OCTRLL_DPTR_TLSA_OFFSET 16
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/** Head LSA */
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#define OCTRLL_DPTR_HLSA_MASK 0x00007FFF
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/** field offset */
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#define OCTRLL_DPTR_HLSA_OFFSET 0
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/* Fields of "DMAR Context Register" */
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/** Header Length
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Length of the Packet Header */
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#define OCTRLL_DCONTEXT_HDRL_MASK 0xFF000000
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/** field offset */
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#define OCTRLL_DCONTEXT_HDRL_OFFSET 24
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/** Offset
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Offset into Frame Segment(s) */
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#define OCTRLL_DCONTEXT_OFFS_MASK 0x00FF0000
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/** field offset */
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#define OCTRLL_DCONTEXT_OFFS_OFFSET 16
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/** Body Length
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Length of the Packet Body w/o FCS */
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#define OCTRLL_DCONTEXT_BDYL_MASK 0x0000FFFF
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/** field offset */
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#define OCTRLL_DCONTEXT_BDYL_OFFSET 0
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/* Fields of "State Register" */
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/** Retransmission Enable
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This bit shows the value of the internal retransmission mode enable register. */
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#define OCTRLL_STATE_RTX 0x00080000
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/* Disable
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#define OCTRLL_STATE_RTX_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_STATE_RTX_EN 0x00080000
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/** Egress Port Filled
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Indicates whether Egress Port is filled or not. */
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#define OCTRLL_STATE_EPFILLED 0x00040000
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/* Not Filled
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#define OCTRLL_STATE_EPFILLED_NFILLED 0x00000000 */
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/** Filled */
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#define OCTRLL_STATE_EPFILLED_FILLED 0x00040000
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/** TX-Data Fifo Full
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Indicates whether the TX-Data Fifo is full or not. */
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#define OCTRLL_STATE_TXFIFOFULL 0x00020000
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/* FIFO not full: There is free space in the FIFO.
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#define OCTRLL_STATE_TXFIFOFULL_FNFULL 0x00000000 */
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/** FIFO full: There is no space in the FIFO. */
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#define OCTRLL_STATE_TXFIFOFULL_FFULL 0x00020000
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/** DMAR Data Ready
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Indicates whether DMAR Data is ready or not. */
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#define OCTRLL_STATE_DMARDRDY 0x00010000
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/* Not Ready
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#define OCTRLL_STATE_DMARDRDY_NRDY 0x00000000 */
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/** Ready */
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#define OCTRLL_STATE_DMARDRDY_RDY 0x00010000
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/** Transmission State
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Current state of data transmission. */
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#define OCTRLL_STATE_TX_MASK 0x00000007
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/** field offset */
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#define OCTRLL_STATE_TX_OFFSET 0
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/** Idle */
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#define OCTRLL_STATE_TX_IDLE 0x00000000
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/** Schedule */
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#define OCTRLL_STATE_TX_SCHEDULE 0x00000001
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/** DMAR open channel */
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#define OCTRLL_STATE_TX_DMAROPEN 0x00000002
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/** DMAR data transmission */
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#define OCTRLL_STATE_TX_DMARTX 0x00000003
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/** DMAR close channel */
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#define OCTRLL_STATE_TX_DMARCLOSE 0x00000004
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/** DMAR delete channel (deallocate segments in SSB) */
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#define OCTRLL_STATE_TX_DMARDELETE 0x00000005
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/** Retransmission acknowledge */
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#define OCTRLL_STATE_TX_RTXACK 0x00000006
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/* Fields of "IRN Capture Register" */
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/** PDU Length
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The PDU Length received from the TMU is zero, i.e. HDRL + BDYL = 0.The schedule response is discarded and the next pending PDU is processed.This bit contributes to the OCTRLL0_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define OCTRLL_IRNCR_PLEN 0x00080000
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/* Nothing
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#define OCTRLL_IRNCR_PLEN_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define OCTRLL_IRNCR_PLEN_INTACK 0x00080000
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/** Read: Interrupt occurred. */
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#define OCTRLL_IRNCR_PLEN_INTOCC 0x00080000
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/** OCTRL NIL LSA
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OCTRL has received a NIL LSA from TMU.The schedule response is discarded and the next pending PDU is processed.This bit contributes to the OCTRLL0_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define OCTRLL_IRNCR_NIL 0x00040000
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/* Nothing
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#define OCTRLL_IRNCR_NIL_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define OCTRLL_IRNCR_NIL_INTACK 0x00040000
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/** Read: Interrupt occurred. */
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#define OCTRLL_IRNCR_NIL_INTOCC 0x00040000
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/** DMAR NIL LSA
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DMAR has received a NIL LSA from FSQM, i.e. linked list in FSQM is corrupt.The PDU transmission is immediately stopped, the memory, allocated by the already transmitted bytes, is deallocated and the OCTRL will be disabled, i.e. CTRL.ACT = 0.This bit contributes to the OCTRLL0_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define OCTRLL_IRNCR_DNIL 0x00010000
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/* Nothing
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#define OCTRLL_IRNCR_DNIL_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define OCTRLL_IRNCR_DNIL_INTACK 0x00010000
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/** Read: Interrupt occurred. */
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#define OCTRLL_IRNCR_DNIL_INTOCC 0x00010000
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/** Timeout
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A timeout of the transmission backpressure has occured and the egress queue will be actively emptied. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define OCTRLL_IRNCR_TOUT 0x00000002
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/* Nothing
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#define OCTRLL_IRNCR_TOUT_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define OCTRLL_IRNCR_TOUT_INTACK 0x00000002
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/** Read: Interrupt occurred. */
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#define OCTRLL_IRNCR_TOUT_INTOCC 0x00000002
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/** RAW Transmission Acknowledge
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The Transmission in RAW mode has been finished. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define OCTRLL_IRNCR_RAWACK 0x00000001
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/* Nothing
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#define OCTRLL_IRNCR_RAWACK_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define OCTRLL_IRNCR_RAWACK_INTACK 0x00000001
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/** Read: Interrupt occurred. */
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#define OCTRLL_IRNCR_RAWACK_INTOCC 0x00000001
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/* Fields of "IRN Interrupt Control Register" */
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/** PDU Length
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNICR_PLEN 0x00080000
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/** OCTRL NIL LSA
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNICR_NIL 0x00040000
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/** DMAR NIL LSA
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNICR_DNIL 0x00010000
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/** Timeout
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNICR_TOUT 0x00000002
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/** RAW Transmission Acknowledge
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNICR_RAWACK 0x00000001
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/* Fields of "IRN Interrupt Enable Register" */
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/** PDU Length
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNEN_PLEN 0x00080000
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/* Disable
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#define OCTRLL_IRNEN_PLEN_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_IRNEN_PLEN_EN 0x00080000
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/** OCTRL NIL LSA
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNEN_NIL 0x00040000
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/* Disable
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#define OCTRLL_IRNEN_NIL_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_IRNEN_NIL_EN 0x00040000
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/** DMAR NIL LSA
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNEN_DNIL 0x00010000
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/* Disable
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#define OCTRLL_IRNEN_DNIL_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_IRNEN_DNIL_EN 0x00010000
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/** Timeout
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNEN_TOUT 0x00000002
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/* Disable
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#define OCTRLL_IRNEN_TOUT_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_IRNEN_TOUT_EN 0x00000002
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/** RAW Transmission Acknowledge
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define OCTRLL_IRNEN_RAWACK 0x00000001
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/* Disable
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#define OCTRLL_IRNEN_RAWACK_DIS 0x00000000 */
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/** Enable */
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#define OCTRLL_IRNEN_RAWACK_EN 0x00000001
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/*! @} */ /* OCTRLL_REGISTER */
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#endif /* _drv_onu_reg_octrll_h */
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