543 lines
23 KiB
C
543 lines
23 KiB
C
/******************************************************************************
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Copyright (c) 2012
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Lantiq Deutschland GmbH
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For licensing information, see the file 'LICENSE' in the root folder of
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this software module.
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******************************************************************************/
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#ifndef _drv_onu_reg_ictrlg_h
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#define _drv_onu_reg_ictrlg_h
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/** \addtogroup ICTRLG_REGISTER
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@{
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*/
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/* access macros */
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#define ictrlg_r32(reg) reg_r32(&ictrlg->reg)
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#define ictrlg_w32(val, reg) reg_w32(val, &ictrlg->reg)
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#define ictrlg_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ictrlg->reg)
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#define ictrlg_r32_table(reg, idx) reg_r32_table(ictrlg->reg, idx)
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#define ictrlg_w32_table(val, reg, idx) reg_w32_table(val, ictrlg->reg, idx)
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#define ictrlg_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ictrlg->reg, idx)
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#define ictrlg_adr_table(reg, idx) adr_table(ictrlg->reg, idx)
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/** ICTRLG register structure */
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struct onu_reg_ictrlg
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{
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/** Control Register
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This register provides the global ICTRLG controls. */
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unsigned int ctrl; /* 0x00000000 */
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/** DMAW Configuration Register
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This register contains necessary configuration elements for the DMAW. */
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unsigned int dmaw_cfg; /* 0x00000004 */
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/** Reassembly Timeout Control Register
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This register provides the rassembly timeout control. */
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unsigned int timeout; /* 0x00000008 */
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/** Reserved */
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unsigned int res_0[9]; /* 0x0000000C */
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/** Maximum allowed Size for PDU Type 0..7
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This register contains the maximum allowed size for PDU type 0..7. */
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unsigned int maxsize[8]; /* 0x00000030 */
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/** Total Received Bytes Counter (Low Part)
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This counter is metering the total number of received bytes. */
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unsigned int rxbcntl; /* 0x00000050 */
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/** Total Received Bytes Counter (High Part)
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This counter is metering the total number of received bytes. */
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unsigned int rxbcnth; /* 0x00000054 */
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/** Oversized non-OMCI PDUs Counter
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This counter is metering the number of oversized non-OMCI PDUs:- Oversized non-OMCI PDU Error (IRN*.OVRSIZE) */
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unsigned int ovrsize; /* 0x00000058 */
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/** DMAW Error Counter
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This counter is metering the number of DMAW Errors:- DMAW Out of FIFO Error (IRN*.DMAWOOF)- DMAW Out Of Memory Error (IRN*.DMAWOOM)- DMAW Timeout Error (IRN*.DMAWTMO)Note: Due to the LSA prefetch, the DMAW errors Out of Memory and Timeout can also occur when no PDU is processed or pending. */
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unsigned int dmawerr; /* 0x0000005C */
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/** OMCI Message Discard Counter
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This counter is metering the number of OMCI Messages which have been discarded due to:- Bad OMCI Errors (IRN*.BADOMCI) */
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unsigned int badomci; /* 0x00000060 */
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/** Ethernet FCS Error Counter
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This counter is metering the total number of Ethernet PDUs where the FCS check has failed:- FCS Errors (IRN*.FCSERR) */
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unsigned int fcserr; /* 0x00000064 */
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/** Reassembly Error Counter
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This counter is metering the number of reassembly errors:- Reassembly Timeout Error (IRN*.REASSERR)- Active Channels Overflow (IRN*.ACTCHAN)- Invalid GPIX Error (IRN*.INVGPIX) */
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unsigned int reasserr; /* 0x00000068 */
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/** Undersized Ethernet Frames Counter
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This counter is metering the number of Ethernet frames which are smaller than 64 bytes. */
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unsigned int undsize; /* 0x0000006C */
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/** Non-OMCI Packet Discard Counter
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This counter is metering the total number of non-OMCI PDUs which have been discarded due to:- Oversize Errors- Minimum Size Under-run- FCS Errors- DMAW Errors- Reassembly Timeout Error- Active Channels Overflow- Invalid GPIX Error */
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unsigned int pdc; /* 0x00000070 */
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/** Total Received PDUs Counter
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This counter is metering the total number of received PDUs. */
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unsigned int rxtpcnt; /* 0x00000074 */
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/** Reserved */
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unsigned int res_1[34]; /* 0x00000078 */
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/** IRN Capture Register
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This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
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unsigned int irncr; /* 0x00000100 */
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/** IRN Interrupt Control Register
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A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
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unsigned int irnicr; /* 0x00000104 */
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/** IRN Interrupt Enable Register
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This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
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unsigned int irnen; /* 0x00000108 */
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/** Reserved */
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unsigned int res_2[4029]; /* 0x0000010C */
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/** GEM Port Table
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The 4096 Entries are addressed by the GEM Port ID and providing the GPID to GPIX translation. */
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unsigned int gpt[4096]; /* 0x00004000 */
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/** GEM Port Index Configuration
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The 256 entries are addressed by GPT.GPIX. */
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unsigned int gpix_cfg[256]; /* 0x00008000 */
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/** GEM Port Index Received Frames Counter
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The 256 counters are metering the either the received GEM frames (CTRL.FRMCNT == 1) or PDUs (CTRL.FRMCNT == 0) for the corresponding GPIX. */
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unsigned int gpix_rxfcnt[256]; /* 0x00008400 */
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/** GEM Port Index Received Bytes Counter (Low Part)
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The 256 counters are metering the received bytes for the corresponding GPIX. */
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unsigned int gpix_rxbcntl[256]; /* 0x00008800 */
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/** GEM Port Index Received Bytes Counter (High Part)
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The 256 counters are metering the received bytes for the corresponding GPIX. */
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unsigned int gpix_rxbcnth[256]; /* 0x00008C00 */
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/** Reserved */
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unsigned int res_7[7168]; /* 0x00008D00 */
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};
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/* Fields of "Control Register" */
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/** Activate Debug Mode of the ICTRL Module
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This bit enables the Debug Mode of the ICTRL.If enabled, ICTRL will always write out data to the IQM, regardless of IQM FIFO state. */
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#define ICTRLG_CTRL_DBG 0x80000000
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/* Disable
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#define ICTRLG_CTRL_DBG_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_CTRL_DBG_EN 0x80000000
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/** GPIX_RXFCNT Fragmentation
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If enabled, GPIX_RXFCNT is counting received GEM frames else PDUs. */
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#define ICTRLG_CTRL_FRMCNT 0x00000020
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/* Disable
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#define ICTRLG_CTRL_FRMCNT_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_CTRL_FRMCNT_EN 0x00000020
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/** Activate CRC Checking for OMCI and Ethernet Frames
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This bit enables the CRC checking for OMCI and Ethernet frames. */
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#define ICTRLG_CTRL_CRC 0x00000010
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/* Disable
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#define ICTRLG_CTRL_CRC_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_CTRL_CRC_EN 0x00000010
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/** Activate Core State Machine
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This bit enables the ICTRL state machine.When deactivating, the current GEM frame is finished and then the ICTRL is on hold.Note 1: All static configuration must be done before activation.Note 2: Deactivation is for debugging only. act - deact - act is prohibited! */
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#define ICTRLG_CTRL_ACT 0x00000001
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/* Disable
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#define ICTRLG_CTRL_ACT_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_CTRL_ACT_EN 0x00000001
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/* Fields of "DMAW Configuration Register" */
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/** Synchronous Reset of DMAW */
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#define ICTRLG_DMAW_CFG_SRET 0x80000000
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/* NoReset
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#define ICTRLG_DMAW_CFG_SRET_NoReset 0x00000000 */
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/** Reset */
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#define ICTRLG_DMAW_CFG_SRET_Reset 0x80000000
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/** Alloc Queue Selection
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FSQM Queue selection for LSA allocation. */
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#define ICTRLG_DMAW_CFG_ALLOCQ 0x00000200
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/* Select Queue 0 (Note: Usage is prohibited!)
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#define ICTRLG_DMAW_CFG_ALLOCQ_Q0 0x00000000 */
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/** Select Queue 1 (Default) */
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#define ICTRLG_DMAW_CFG_ALLOCQ_Q1 0x00000200
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/** Free Queue Selection
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FSQM Queue selection for LSA freeing. */
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#define ICTRLG_DMAW_CFG_FREEQ 0x00000100
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/* Select Queue 0 (Note: Usage is prohibited!)
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#define ICTRLG_DMAW_CFG_FREEQ_Q0 0x00000000 */
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/** Select Queue 1 (Default) */
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#define ICTRLG_DMAW_CFG_FREEQ_Q1 0x00000100
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/** FSQM LSA Request Limitation
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This is the number of wait cycles until a LSA request to FSQM issues an error. */
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#define ICTRLG_DMAW_CFG_LSARLMT_MASK 0x000000FF
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/** field offset */
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#define ICTRLG_DMAW_CFG_LSARLMT_OFFSET 0
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/* Fields of "Reassembly Timeout Control Register" */
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/** Limit for Reassembly Timeout Counter
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This value determines the time budget for a fragmented PDU.When the budged is consumed the packet is dropped.0x0: no check0x1: approx. 3.2ns0xFFFF_FFFF: approx. 13,7sNote: The values are based on 312.5MHz core clock frequency. */
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#define ICTRLG_TIMEOUT_LIMIT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_TIMEOUT_LIMIT_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 0" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE0_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE0_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 1" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE1_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE1_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 2" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE2_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE2_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 3" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE3_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE3_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 4" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE4_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE4_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 5" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE5_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE5_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 6" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE6_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE6_SIZE_OFFSET 0
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/* Fields of "Maximum allowed Size for PDU Type 7" */
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/** Size
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This register holds the size in bytes.0x0: no check */
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#define ICTRLG_MAXSIZE7_SIZE_MASK 0x0000FFFF
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/** field offset */
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#define ICTRLG_MAXSIZE7_SIZE_OFFSET 0
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/* Fields of "Total Received Bytes Counter (Low Part)" */
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/** Counter
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Counter value (Low Part).Note: First the Low and then the High Part has to be read. */
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#define ICTRLG_RXBCNTL_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_RXBCNTL_CNT_OFFSET 0
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/* Fields of "Total Received Bytes Counter (High Part)" */
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/** Counter
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Counter value (High Part).Note: First the Low and then the High Part has to be read. */
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#define ICTRLG_RXBCNTH_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_RXBCNTH_CNT_OFFSET 0
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/* Fields of "Oversized non-OMCI PDUs Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_OVRSIZE_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_OVRSIZE_CNT_OFFSET 0
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/* Fields of "DMAW Error Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_DMAWERR_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_DMAWERR_CNT_OFFSET 0
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/* Fields of "OMCI Message Discard Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_BADOMCI_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_BADOMCI_CNT_OFFSET 0
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/* Fields of "Ethernet FCS Error Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_FCSERR_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_FCSERR_CNT_OFFSET 0
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/* Fields of "Reassembly Error Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_REASSERR_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_REASSERR_CNT_OFFSET 0
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/* Fields of "Undersized Ethernet Frames Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_UNDSIZE_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_UNDSIZE_CNT_OFFSET 0
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/* Fields of "Non-OMCI Packet Discard Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_PDC_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_PDC_CNT_OFFSET 0
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/* Fields of "Total Received PDUs Counter" */
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/** Counter
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This register holds the counter value. */
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#define ICTRLG_RXTPCNT_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_RXTPCNT_CNT_OFFSET 0
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/* Fields of "IRN Capture Register" */
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/** DMAW Out of FIFO Error
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Indicates that the IQM fifo was full when trying to enqueue the PDU.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_DMAWOOF 0x04000000
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/* Nothing
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#define ICTRLG_IRNCR_DMAWOOF_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_DMAWOOF_INTACK 0x04000000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_DMAWOOF_INTOCC 0x04000000
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/** DMAW Out Of Memory Error
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Indicates that the LSA request to FSQM returned NIL.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_DMAWOOM 0x02000000
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/* Nothing
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#define ICTRLG_IRNCR_DMAWOOM_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_DMAWOOM_INTACK 0x02000000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_DMAWOOM_INTOCC 0x02000000
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/** DMAW Timeout Error
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Indicates that the LSA request to FSQM went into timeout.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_DMAWTMO 0x01000000
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/* Nothing
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#define ICTRLG_IRNCR_DMAWTMO_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_DMAWTMO_INTACK 0x01000000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_DMAWTMO_INTOCC 0x01000000
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/** Minimum Size non-OMCI PDU Under-run
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Indicates that a non-OMCI PDU has under-run the minimum size of 5 bytes.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_MINSIZE 0x00400000
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/* Nothing
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#define ICTRLG_IRNCR_MINSIZE_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_MINSIZE_INTACK 0x00400000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_MINSIZE_INTOCC 0x00400000
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/** Reassembly Timeout Error
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Indicates that a reassembly timeout has occurred.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_REASSERR 0x00200000
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/* Nothing
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#define ICTRLG_IRNCR_REASSERR_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_REASSERR_INTACK 0x00200000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_REASSERR_INTOCC 0x00200000
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/** Invalid GPIX Error
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Indicates that the GPID has pointed to an invalid GPIX, i.e. GPT[GPID].VALID = 0.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_INVGPIX 0x00100000
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/* Nothing
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#define ICTRLG_IRNCR_INVGPIX_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_INVGPIX_INTACK 0x00100000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_INVGPIX_INTOCC 0x00100000
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/** Active Channels Overflow
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Indicates that the number of active channels has exceeded the maximum number of 2.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_ACTCHAN 0x00080000
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/* Nothing
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#define ICTRLG_IRNCR_ACTCHAN_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_ACTCHAN_INTACK 0x00080000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_ACTCHAN_INTOCC 0x00080000
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/** FCS Error
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Indicates that the Ethernet frame FCS check has failed.Note: There is no FCS check for oversized Ethernet frames.This bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_FCSERR 0x00040000
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/* Nothing
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#define ICTRLG_IRNCR_FCSERR_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_FCSERR_INTACK 0x00040000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_FCSERR_INTOCC 0x00040000
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/** Bad OMCI Error
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Indicates that one of the following OMCI errors has occurred:- Oversize Errors (PLI MAXSIZE && MAXSIZE 0 && PDUT == OMCI)- Minimum Size Under-run (PLI - CRC Errors- DMAW Errors- Reassembly Timeout ErrorThis bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_BADOMCI 0x00020000
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/* Nothing
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#define ICTRLG_IRNCR_BADOMCI_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_BADOMCI_INTACK 0x00020000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_BADOMCI_INTOCC 0x00020000
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/** Oversized non-OMCI PDU Error
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Indicates that a non-OMCI PDU has been oversized, i.e.sum(PLI) MAXSIZE && MAXSIZE 0 && PDUT != OMCIThis bit contributes to the ICTRLG_ERR interrupt. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
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#define ICTRLG_IRNCR_OVRSIZE 0x00010000
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/* Nothing
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#define ICTRLG_IRNCR_OVRSIZE_NULL 0x00000000 */
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/** Write: Acknowledge the interrupt. */
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#define ICTRLG_IRNCR_OVRSIZE_INTACK 0x00010000
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/** Read: Interrupt occurred. */
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#define ICTRLG_IRNCR_OVRSIZE_INTOCC 0x00010000
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/* Fields of "IRN Interrupt Control Register" */
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/** DMAW Out of FIFO Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_DMAWOOF 0x04000000
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/** DMAW Out Of Memory Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_DMAWOOM 0x02000000
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/** DMAW Timeout Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_DMAWTMO 0x01000000
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/** Minimum Size non-OMCI PDU Under-run
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_MINSIZE 0x00400000
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/** Reassembly Timeout Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_REASSERR 0x00200000
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/** Invalid GPIX Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_INVGPIX 0x00100000
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/** Active Channels Overflow
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_ACTCHAN 0x00080000
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/** FCS Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_FCSERR 0x00040000
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/** Bad OMCI Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_BADOMCI 0x00020000
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/** Oversized non-OMCI PDU Error
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Interrupt control bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNICR_OVRSIZE 0x00010000
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/* Fields of "IRN Interrupt Enable Register" */
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/** DMAW Out of FIFO Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_DMAWOOF 0x04000000
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/* Disable
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#define ICTRLG_IRNEN_DMAWOOF_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_DMAWOOF_EN 0x04000000
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/** DMAW Out Of Memory Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_DMAWOOM 0x02000000
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/* Disable
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#define ICTRLG_IRNEN_DMAWOOM_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_DMAWOOM_EN 0x02000000
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/** DMAW Timeout Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_DMAWTMO 0x01000000
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/* Disable
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#define ICTRLG_IRNEN_DMAWTMO_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_DMAWTMO_EN 0x01000000
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/** Minimum Size non-OMCI PDU Under-run
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_MINSIZE 0x00400000
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/* Disable
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#define ICTRLG_IRNEN_MINSIZE_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_MINSIZE_EN 0x00400000
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/** Reassembly Timeout Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_REASSERR 0x00200000
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/* Disable
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#define ICTRLG_IRNEN_REASSERR_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_REASSERR_EN 0x00200000
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/** Invalid GPIX Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_INVGPIX 0x00100000
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/* Disable
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#define ICTRLG_IRNEN_INVGPIX_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_INVGPIX_EN 0x00100000
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/** Active Channels Overflow
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_ACTCHAN 0x00080000
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/* Disable
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#define ICTRLG_IRNEN_ACTCHAN_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_ACTCHAN_EN 0x00080000
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/** FCS Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_FCSERR 0x00040000
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/* Disable
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#define ICTRLG_IRNEN_FCSERR_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_FCSERR_EN 0x00040000
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/** Bad OMCI Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_BADOMCI 0x00020000
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/* Disable
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#define ICTRLG_IRNEN_BADOMCI_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_BADOMCI_EN 0x00020000
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/** Oversized non-OMCI PDU Error
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Interrupt enable bit for the corresponding bit in the IRNCR register. */
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#define ICTRLG_IRNEN_OVRSIZE 0x00010000
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/* Disable
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#define ICTRLG_IRNEN_OVRSIZE_DIS 0x00000000 */
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/** Enable */
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#define ICTRLG_IRNEN_OVRSIZE_EN 0x00010000
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/* Fields of "GEM Port Table" */
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/** Valid Bit
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GEM Port Index valid flag.Note: Reset not valid (RAM)! */
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#define ICTRLG_GPT_VALID 0x00000100
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/* Not Valid
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#define ICTRLG_GPT_VALID_NV 0x00000000 */
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/** Valid */
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#define ICTRLG_GPT_VALID_V 0x00000100
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/** GEM Port Index
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The GPIX addresses the corresponding entry in GPIX_CFG.Note: Reset not valid (RAM)! */
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#define ICTRLG_GPT_GPIX_MASK 0x000000FF
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/** field offset */
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#define ICTRLG_GPT_GPIX_OFFSET 0
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/* Fields of "GEM Port Index Configuration" */
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/** Ingress Queue Number
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Ingress queue number:0 - IQM queue 51 - IQM queue 62,3 - IQM queue 7Note: Reset not valid (RAM)! */
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#define ICTRLG_GPIX_CFG_IQN_MASK 0x00000018
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/** field offset */
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#define ICTRLG_GPIX_CFG_IQN_OFFSET 3
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/** PDU Type
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Indicates the base Protocol for each GEM portNote: Reset not valid (RAM)! */
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#define ICTRLG_GPIX_CFG_PDUT_MASK 0x00000007
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/** field offset */
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#define ICTRLG_GPIX_CFG_PDUT_OFFSET 0
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/* Fields of "GEM Port Index Received Frames Counter" */
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/** Counter
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Counter value.Note: Reset not valid (RAM)! */
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#define ICTRLG_GPIX_RXFCNT_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_GPIX_RXFCNT_CNT_OFFSET 0
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/* Fields of "GEM Port Index Received Bytes Counter (Low Part)" */
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/** Counter
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Counter value (Low Part).Note 1: Reset not valid (RAM)!Note 2: First the Low and then the High Part has to be read. */
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#define ICTRLG_GPIX_RXBCNTL_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_GPIX_RXBCNTL_CNT_OFFSET 0
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/* Fields of "GEM Port Index Received Bytes Counter (High Part)" */
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/** Counter
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Counter value (High Part).Note 1: Reset not valid (RAM)!Note 2: First the Low and then the High Part has to be read. */
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#define ICTRLG_GPIX_RXBCNTH_CNT_MASK 0xFFFFFFFF
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/** field offset */
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#define ICTRLG_GPIX_RXBCNTH_CNT_OFFSET 0
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/*! @} */ /* ICTRLG_REGISTER */
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#endif /* _drv_onu_reg_ictrlg_h */
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