651 lines
16 KiB
C
651 lines
16 KiB
C
/******************************************************************************
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Copyright (c) 2011
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Lantiq Deutschland GmbH
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For licensing information, see the file 'LICENSE' in the root folder of
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this software module.
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******************************************************************************/
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#include "drv_onu_api.h"
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#include "drv_onu_register.h"
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#include "drv_onu_ll_sys.h"
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#include "drv_onu_ll_octrlg.h"
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STATIC int octrlg_basic_init(void);
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STATIC void octrlg_tcont_map_init(void);
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STATIC void octrlg_tcont_table_init(void);
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STATIC void octrlg_gpix_table_init(void);
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int octrlg_init(void)
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{
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uint32_t i;
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/*
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Enable module clock, release reset. This is mandatory before
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accessing module's registers.
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*/
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sys_gpe_hw_activate_or_reboot(SYS_GPE_ACT_GPONE_SET);
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if (octrlg_basic_init() != 0)
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return -1;
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/*
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OCTRLG.TCMAP[0..1023] = 0x0000 0000
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OCTRLG.TCTABLE[0..15] = 0xFFFF FFFF
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OCTRLG.GPIXTABLE[0..127] = 0x0000 0000
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*/
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octrlg_tcont_map_init();
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octrlg_tcont_table_init();
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octrlg_gpix_table_init();
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/* Initialization of counter memories */
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for (i = 0; i < GPIXTABLE_LEN; i++) {
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octrlg_w32(0, txpcnt[i]);
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octrlg_w32(0, txbcntl[i]);
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}
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return 0;
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}
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/*
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nGemBlockLength: configure in OCTRLG, OCTRLG.CFG0.IBS = 2^15/gem_block_len
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gem_payload_sz_max: configure in OCTRLG, OCTRLG.CFG1.GEMPLSIZE
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*/
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int octrlg_config_set(const uint32_t gem_block_len,
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const uint32_t gem_payload_sz_max)
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{
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if (gem_block_len == 0)
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return -1;
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octrlg_w32_mask(OCTRLG_CFG0_IBS_MASK,
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(((1 << 15) / gem_block_len) & OCTRLG_CFG0_IBS_MASK),
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cfg0);
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octrlg_w32_mask(OCTRLG_CFG1_GEMPLSIZE_MASK,
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((gem_payload_sz_max << OCTRLG_CFG1_GEMPLSIZE_OFFSET) &
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OCTRLG_CFG1_GEMPLSIZE_MASK), cfg1);
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return 0;
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}
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int octrlg_config_get(uint32_t *gem_block_len, uint32_t *gem_payload_sz_max)
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{
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if (octrlg_r32(cfg0) & OCTRLG_CFG0_IBS_MASK)
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*gem_block_len =
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(1 << 15) / (octrlg_r32(cfg0) & OCTRLG_CFG0_IBS_MASK);
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*gem_payload_sz_max =
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(octrlg_r32(cfg1) & OCTRLG_CFG1_GEMPLSIZE_MASK) >>
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OCTRLG_CFG1_GEMPLSIZE_OFFSET;
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return 0;
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}
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void octrlg_dbru_mode_dbg_set(const uint32_t act)
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{
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octrlg_w32_mask(OCTRLG_CFG1_DBRUDBG_EN,
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act ? OCTRLG_CFG1_DBRUDBG_EN : 0, cfg1);
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}
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void octrlg_dbru_mode_dbg_get(uint32_t *act)
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{
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*act = (octrlg_r32(cfg1) & OCTRLG_CFG1_DBRUDBG_EN) ? true : false;
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}
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void octrlg_dbru_debug_set(const uint32_t mode2y,
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const uint32_t mode2g,
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const uint32_t mode1)
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{
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octrlg_w32_mask(OCTRLG_DBRUDBG_DBRU2Y_MASK |
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OCTRLG_DBRUDBG_DBRU2G_MASK |
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OCTRLG_DBRUDBG_DBRU1_MASK,
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(mode2y << OCTRLG_DBRUDBG_DBRU2Y_OFFSET) |
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(mode2g << OCTRLG_DBRUDBG_DBRU2G_OFFSET) |
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(mode1 << OCTRLG_DBRUDBG_DBRU1_OFFSET),
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dbrudbg);
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}
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#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
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void octrlg_dbru_debug_get(uint32_t *mode2y, uint32_t *mode2g, uint32_t *mode1)
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{
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uint32_t reg;
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reg = octrlg_r32(dbrudbg);
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*mode2y = (reg & OCTRLG_DBRUDBG_DBRU2Y_MASK) >>
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OCTRLG_DBRUDBG_DBRU2Y_OFFSET;
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*mode2g = (reg & OCTRLG_DBRUDBG_DBRU2G_MASK) >>
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OCTRLG_DBRUDBG_DBRU2G_OFFSET;
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*mode1 = (reg & OCTRLG_DBRUDBG_DBRU1_MASK) >>
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OCTRLG_DBRUDBG_DBRU1_OFFSET;
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}
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#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
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void octrlg_dbru_mode_get(uint32_t *mode)
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{
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*mode = (octrlg_r32(tcreq) & OCTRLG_TCREQ_DBRU_MASK) >>
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OCTRLG_TCREQ_DBRU_OFFSET;
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}
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/**
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OCTRLG.TCTABLE[n].REPN[n] = egress_port_idx, with n = tcont_idx
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*/
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int octrlg_epn_set(const uint32_t tcont_idx, const uint32_t egress_port_idx,
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const uint32_t prempted_epn_idx)
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{
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if (tcont_idx >= ONU_GPE_MAX_TCONT)
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return -1;
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octrlg_w32_mask(OCTRLG_TCTABLE0_REPN0_MASK,
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((egress_port_idx << OCTRLG_TCTABLE0_REPN0_OFFSET) &
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OCTRLG_TCTABLE0_REPN0_MASK),
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tctable[tcont_idx]);
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octrlg_w32_mask(OCTRLG_TCTABLE0_PEPN0_MASK,
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((prempted_epn_idx << OCTRLG_TCTABLE0_PEPN0_OFFSET) &
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OCTRLG_TCTABLE0_PEPN0_MASK),
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tctable[tcont_idx]);
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return 0;
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}
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int octrlg_epn_get(const uint32_t tcont_idx, uint32_t *egress_port_idx,
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uint32_t *prempted_epn_idx)
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{
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if (tcont_idx >= ONU_GPE_MAX_TCONT) {
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*egress_port_idx = 0;
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*prempted_epn_idx = 0;
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return -1;
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}
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*egress_port_idx =
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(octrlg_r32(tctable[tcont_idx]) & OCTRLG_TCTABLE0_REPN0_MASK)
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>> OCTRLG_TCTABLE0_REPN0_OFFSET;
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*prempted_epn_idx =
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(octrlg_r32(tctable[tcont_idx]) & OCTRLG_TCTABLE0_PEPN0_MASK)
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>> OCTRLG_TCTABLE0_PEPN0_OFFSET;
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return 0;
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}
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/** Hardware Programming Details
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The following hardware functions must be configured:
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- tcont_idx: selects the table entry
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- alloc_id : Allocation ID of the T-CONT
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- valid : true indicates that the Alloc Id has been assigned and is
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valid.
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The T-CONT Table is addressed by the 12-bit alloc_id value, the
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tcont_idx is written as the data value to the selected table location,
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together with the valid indication being set (0b1).
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OCTRLG(OCTRLG), TCMAP[n].TCIX[n]: write a free T-CONT index value
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(tcont_idx)
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into the location that is defined by
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n = alloc_id.
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OCTRLG(OCTRLG), TCMAP[n].V[n] : enable T-CONT index value
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at the location that is defined by
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n = alloc_id, by setting the related valid
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bit.
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*/
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int octrlg_tcont_set(const uint32_t tcont_idx, const uint32_t alloc_id)
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{
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octrlg_w32((tcont_idx & OCTRLG_TCMAP0_TCIX0_MASK) |
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OCTRLG_TCMAP0_V0, tcmap[alloc_id]);
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return 0;
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}
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/** Hardware Programming Details
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The following hardware functions must be handled:
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The T-CONT mapping table is read at the location given by the Allocation ID.
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If the valid flag is set, the index value is returned with valid = true.
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If the valid is not set, the index value is returned with valid = false.
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The hardware table is located in OCTRLG (TCMAP),
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TCMAP[n].TCIX[n], n = Allocation ID
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TCMAP[n].V[n], n = Allocation ID
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*/
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int octrlg_tcont_get(const uint32_t tcont_idx, uint32_t *alloc_id)
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{
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uint32_t i, val;
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for (i = 0; i < TCMAP_LEN; i++) {
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val = octrlg_r32(tcmap[i]);
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if ((val & OCTRLG_TCMAP0_V0) == 0)
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continue;
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if (tcont_idx == (val & OCTRLG_TCMAP0_TCIX0_MASK)) {
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*alloc_id = i;
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return 0;
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}
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}
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*alloc_id = 0;
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return -1;
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}
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/** Hardware Programming Details
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The following hardware functions must be handled:
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The T-CONT mapping table is searched for an entry that matches the
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tcont_idx with the valid bit being set. If the given tcont_idx value is
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out of range (>= ONU_GPE_MAX_TCONT), an error code is returned
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(GPE_STATUS_VALUE_RANGE_ERR).
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If found, the table entry is set to "invalid".
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If no match is found within the table (the table address range (Allocation
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ID value range) is from ONU_GPE_MIN_ALLOCATION_ID to
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ONU_GPE_MAX_ALLOCATION_ID), the return status is set
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to GPE_STATUS_NOT_AVAILABLE.
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The hardware table to be searched and modified is located in
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OCTRLG, TCMAP[n].V[n] = 0b0 (n = Allocation ID).
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*/
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int octrlg_tcont_delete(const uint32_t tcont_idx)
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{
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uint32_t i, val;
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for (i = 0; i < TCMAP_LEN; i++) {
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val = octrlg_r32(tcmap[i]);
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if ((val & OCTRLG_TCMAP0_V0) == 0)
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continue;
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if (tcont_idx == (val & OCTRLG_TCMAP0_TCIX0_MASK)) {
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octrlg_w32(0, tcmap[i]);
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return 0;
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}
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}
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return -1;
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}
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/** Direct deletion of an entry in TCMAP table by TCONT ID
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- alloc_id: TCONT ID is an index of an entry to be deleted
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*/
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int octrlg_tcont_alloc_id_delete(const uint32_t alloc_id)
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{
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if (alloc_id >= TCMAP_LEN)
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return -1;
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octrlg_w32(0, tcmap[alloc_id]);
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return 0;
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}
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int octrlg_tcont_alloc_id_get(const uint32_t alloc_id, uint32_t *tcont_idx)
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{
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uint32_t val;
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val = octrlg_r32(tcmap[alloc_id]);
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if ((val & OCTRLG_TCMAP0_V0) == 0)
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return -1;
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*tcont_idx = val & OCTRLG_TCMAP0_TCIX0_MASK;
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return 0;
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}
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/**
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Read hardware counter.
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- gpix: selects the GEM port index (0..ONU_GPE_MAX_GPIX - 1)
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- tx_frames: OCTRLG.TXPCNT(gem_port_index)
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- tx_bytes: OCTRLG.TXBCNTH(gem_port_index)*2^32 +
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OCTRLG.TXBCNTL(gem_port_index)
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Hardware Programming Details
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These are the counters that are provided by the OCTRLG blocks of the OCTRLG
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module. The counters wrap around an need to be checked regularly.
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*/
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int octrlg_gem_counter_get(const uint32_t gpix,
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struct gpe_cnt_octrlg_gem_val *counter)
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{
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uint32_t l, h;
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if (gpix >= ONU_GPE_MAX_GPIX)
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return -1;
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counter->tx_frames = (uint64_t)octrlg_r32(txpcnt[gpix]);
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/* First the Low and then the High Part has to be read. No overflow
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checks are needed since the HW stores the high part on the low
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part read access*/
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l = octrlg_r32(txbcntl[gpix]);
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h = octrlg_r32(txbcnth[gpix]);
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counter->tx_bytes = ((uint64_t)h << 32) | l;
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return 0;
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}
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/**
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Read hardware counters from OCTRLG:
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- tx_gem_idle_frames_total: OCTRLG.TXTICNT
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- tx_gem_frames_total: OCTRLG.TXTPCNT
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- tx_gem_bytes_total: OCTRLG.TXCNT
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- tx_tcont_total: OCTRLG.TXTTCNT
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Hardware Programming Details
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These are the counters that are provided by the OCTRLG block of the OCTRLG
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module. The counters wrap around an need to be checked regularly.
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*/
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int octrlg_counter_get(struct gpe_cnt_octrlg_val *counter)
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{
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uint32_t l, h;
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if (octrlg_is_enabled()) {
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counter->tx_gem_idle_frames_total = octrlg_r32(txticnt);
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counter->tx_gem_frames_total = octrlg_r32(txtpcnt);
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counter->tx_gem_bytes_total = octrlg_r32(txtcnt);
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counter->tx_tcont_total = octrlg_r32(txttcnt);
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/* First the Low and then the High Part has to be read. No
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overflow checks are needed since the HW stores the high part
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on the low part read access*/
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l = octrlg_r32(txtbcntl);
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h = octrlg_r32(txtbcnth);
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counter->tx_gem_pdu_bytes_total = ((uint64_t)h << 32) | l;
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} else {
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memset(counter, 0x00, sizeof(struct gpe_cnt_octrlg_val));
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}
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return 0;
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}
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int octrlg_gem_port_set(const uint32_t gem_port_id,
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const uint32_t gem_port_index,
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const enum gpe_direction data_direction)
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{
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if ((uint32_t)data_direction & (uint32_t)GPE_DIRECTION_UPSTREAM)
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octrlg_w32(gem_port_id, gpixtable[gem_port_index]);
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return 0;
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}
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int octrlg_gpix_get(const uint32_t gem_port_id, uint32_t *gem_port_index)
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{
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uint32_t i;
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for (i = 0; i < GPIXTABLE_LEN; i++) {
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if (octrlg_r32(gpixtable[i]) == gem_port_id) {
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*gem_port_index = i;
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return 0;
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}
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}
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return -1;
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}
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int octrlg_gem_port_delete(const uint32_t gem_port_index)
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{
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octrlg_w32(0x0, gpixtable[gem_port_index]);
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return 0;
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}
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/*
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OCTRLG.CFG0.IDLELEN = 4
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OCTRLG.CFG1.GEMPLSIZE = 0x0FFF
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OCTRLG.IDLEFRAME0.IFB0 = 0xB6
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OCTRLG.IDLEFRAME0.IFB1 = 0xAB
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OCTRLG.IDLEFRAME0.IFB2 = 0x31
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OCTRLG.IDLEFRAME0.IFB3 = 0xE0
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OCTRLG.IDLEFRAME1.IFB4 = 0x55
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*/
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STATIC int octrlg_basic_init(void)
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{
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uint32_t cfg;
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octrlg_w32(0, ctrl);
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cfg = 0x0;
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/* set FIFO watermarks
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* Set value of 4 - this results in the ability to serve single
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T-Cont Requests down to 16 bytes.
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*/
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set_val(cfg, 4, OCTRLG_CFG0_GTCFIFOTHRES_MASK,
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OCTRLG_CFG0_GTCFIFOTHRES_OFFSET);
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set_val(cfg, 4, OCTRLG_CFG0_IDLELEN_MASK, OCTRLG_CFG0_IDLELEN_OFFSET);
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octrlg_w32(cfg, cfg0);
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if (octrlg_config_set(48, 4095) != 0)
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return -1;
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octrlg_w32(OCTRLG_DCTRL_FQ_Q1, dctrl);
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/* Registers IDLEFRAME0...15 are left in reset state, which
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is the standardized idle frame header followed by all zeroes.
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*/
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/* Make OCTRLG counter count per packet, not per GEM frame */
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octrlg_w32(OCTRLG_CFG1_GEMPLSIZE_MASK, cfg1);
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/* reset register-based counters */
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octrlg_w32(0, txtpcnt);
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octrlg_w32(0, txtbcnth);
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octrlg_w32(0, txtbcntl);
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octrlg_w32(0, txticnt);
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octrlg_w32(0, txtcnt);
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octrlg_w32(0, txttcnt);
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return 0;
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}
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/*
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tcmap[alloc_id] = tcont_index | valid bit
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*/
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STATIC void octrlg_tcont_map_init(void)
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{
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/* All T-Cont IDs invalid */
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uint32_t i;
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for (i = 0; i < TCMAP_LEN; i++)
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octrlg_w32(0x0, tcmap[i]);
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}
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/*
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tctable[tcont_index] = epn
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*/
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STATIC void octrlg_tcont_table_init(void)
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{
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uint32_t i;
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for (i = 0; i < ONU_GPE_MAX_TCONT; i++)
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octrlg_w32(0xFFFFFFFF, tctable[i]);
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octrlg_epn_set(OMCI_TCIX, 127, ONU_GPE_OMCI_EGRESS_PORT);
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}
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/*
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gpixtable[gpix] = gpid
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*/
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STATIC void octrlg_gpix_table_init(void)
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{
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/* all GPIXs translate into GPID=0 */
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uint32_t i;
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for (i = 0; i < GPIXTABLE_LEN; i++)
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octrlg_w32(0x0, gpixtable[i]);
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}
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void octrlg_enable(const uint32_t act)
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{
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/* enable/disable the module */
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octrlg_w32_mask(OCTRLG_CTRL_ACT_EN, act ? OCTRLG_CTRL_ACT_EN : 0, ctrl);
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}
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uint32_t octrlg_is_enabled(void)
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{
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return (octrlg_r32(ctrl) & OCTRLG_CTRL_ACT_EN) ? true : false;
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|
}
|
|
|
|
#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
|
|
void octrlg_gtc_fifo_threshold_set(const uint32_t value)
|
|
{
|
|
octrlg_w32_mask(value, OCTRLG_CFG0_GTCFIFOTHRES_MASK, cfg0);
|
|
}
|
|
#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
|
|
|
|
#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
|
|
void octrlg_gtc_fifo_threshold_get(uint32_t *value)
|
|
{
|
|
*value = (octrlg_r32(cfg0) & OCTRLG_CFG0_GTCFIFOTHRES_MASK)
|
|
>> OCTRLG_CFG0_GTCFIFOTHRES_OFFSET;
|
|
}
|
|
#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
|
|
|
|
#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
|
|
int octrlg_idle_len_set(const uint32_t value)
|
|
{
|
|
uint32_t reg = 0, val;
|
|
|
|
if (value == 0)
|
|
return -1;
|
|
|
|
val = (uint32_t)(value - 1);
|
|
|
|
set_val(reg, val, OCTRLG_CFG0_IDLELEN_MASK, OCTRLG_CFG0_IDLELEN_OFFSET);
|
|
|
|
octrlg_w32_mask(value, OCTRLG_CFG0_IDLELEN_MASK, cfg0);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
|
|
|
|
uint32_t octrlg_idle_len_get(void)
|
|
{
|
|
uint32_t val;
|
|
|
|
val = (octrlg_r32(cfg0) & OCTRLG_CFG0_IDLELEN_MASK)
|
|
>> OCTRLG_CFG0_IDLELEN_OFFSET;
|
|
return (uint32_t)(val + 1);
|
|
}
|
|
|
|
#ifdef ONU_LIBRARY
|
|
/** Reads total transmitted bytes counter and recalculate
|
|
laser life time.
|
|
|
|
\remarks This function is used by optic library and
|
|
is called at least each 27 seconds
|
|
*/
|
|
void octrlg_laser_ageupdate ( uint32_t *seconds )
|
|
{
|
|
uint32_t reg, diff;
|
|
static uint32_t reg_old = 0;
|
|
static uint32_t last = 0;
|
|
|
|
reg = octrlg_r32 (txtcnt);
|
|
if (reg > reg_old)
|
|
diff = reg - reg_old;
|
|
else
|
|
diff = 0xFFFFFFFF - reg_old + reg + 1;
|
|
/* not clear on read */
|
|
reg_old = reg;
|
|
/* counter = 19440 in 125 us */
|
|
*seconds = diff / (0x9450C00);
|
|
last += (diff % (0x9450C00));
|
|
if (last > 0x9450C00) {
|
|
(*seconds) ++;
|
|
last -= 0x9450C00;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
|
|
void octrlg_interrupt_mask_set(const uint32_t value)
|
|
{
|
|
octrlg_w32(value, irnen);
|
|
}
|
|
#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
|
|
|
|
#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
|
|
void octrlg_interrupt_set(const uint32_t value)
|
|
{
|
|
octrlg_w32(value, irnicr);
|
|
}
|
|
#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
|
|
|
|
#ifdef INCLUDE_UNUSED_LL_FUNCTIONS
|
|
void octrlg_interrupt_get(uint32_t *value)
|
|
{
|
|
*value = octrlg_r32(irncr);
|
|
}
|
|
#endif /* #ifdef INCLUDE_UNUSED_LL_FUNCTIONS*/
|
|
|
|
#if defined(INCLUDE_DUMP)
|
|
|
|
void octrlg_dump(struct seq_file *s)
|
|
{
|
|
if (sys_gpe_hw_is_activated(SYS_GPE_ACT_GPONE_SET) == 0) {
|
|
seq_printf(s, "octrlg not activated\n");
|
|
return;
|
|
}
|
|
|
|
#define dump_reg(reg) \
|
|
seq_printf(s, "%-14s = 0x%08x\n", # reg, octrlg_r32(reg))
|
|
|
|
dump_reg(ctrl);
|
|
dump_reg(cfg0);
|
|
dump_reg(cfg1);
|
|
dump_reg(dctrl);
|
|
dump_reg(txtpcnt);
|
|
dump_reg(txttcnt);
|
|
dump_reg(txticnt);
|
|
dump_reg(txtcnt);
|
|
dump_reg(txtbcntl);
|
|
dump_reg(txtbcnth);
|
|
dump_reg(txbcntl);
|
|
dump_reg(tcreq);
|
|
dump_reg(tcstate);
|
|
dump_reg(irnicr);
|
|
#undef dump_reg
|
|
}
|
|
|
|
void octrlg_table_dump(struct seq_file *s)
|
|
{
|
|
uint32_t i, k;
|
|
|
|
if (sys_gpe_hw_is_activated(SYS_GPE_ACT_GPONE_SET) == 0) {
|
|
seq_printf(s, "octrlg not activated\n");
|
|
return;
|
|
}
|
|
seq_printf(s, "tcmap table\n");
|
|
for (i = 0; i < TCMAP_LEN;) {
|
|
seq_printf(s, "%08x: ", octrlg_adr_table(tcmap, i));
|
|
for (k = 0; k < 16 && i < TCMAP_LEN; k++, i++)
|
|
seq_printf(s, "%08x ", octrlg_r32(tcmap[i]));
|
|
seq_printf(s, "\n");
|
|
}
|
|
|
|
seq_printf(s, "tcont table\n");
|
|
for (i = 0; i < ONU_GPE_MAX_TCONT;) {
|
|
seq_printf(s, "%08x: ", octrlg_adr_table(tctable, i));
|
|
for (k = 0; k < 16 && i < ONU_GPE_MAX_TCONT; k++, i++)
|
|
seq_printf(s, "%08x ", octrlg_r32(tctable[i]));
|
|
seq_printf(s, "\n");
|
|
}
|
|
|
|
seq_printf(s, "gpix table\n");
|
|
for (i = 0; i < GPIXTABLE_LEN;) {
|
|
seq_printf(s, "%08x: ", octrlg_adr_table(gpixtable, i));
|
|
for (k = 0; k < 16 && i < GPIXTABLE_LEN; k++, i++)
|
|
seq_printf(s, "%08x ", octrlg_r32(gpixtable[i]));
|
|
seq_printf(s, "\n");
|
|
}
|
|
|
|
seq_printf(s, "txpcnt table\n");
|
|
for (i = 0; i < GPIXTABLE_LEN;) {
|
|
seq_printf(s, "%08x: ", octrlg_adr_table(txpcnt, i));
|
|
for (k = 0; k < 16 && i < GPIXTABLE_LEN; k++, i++)
|
|
seq_printf(s, "%08x ", octrlg_r32(txpcnt[i]));
|
|
seq_printf(s, "\n");
|
|
}
|
|
|
|
seq_printf(s, "dptr table\n");
|
|
for (i = 0; i < DPTRTABLE_LEN;) {
|
|
seq_printf(s, "%08x: ", octrlg_adr_table(dptr, i));
|
|
for (k = 0; k < 16 && i < GPIXTABLE_LEN; k++, i++)
|
|
seq_printf(s, "%08x ", octrlg_r32(dptr[i]));
|
|
seq_printf(s, "\n");
|
|
}
|
|
|
|
seq_printf(s, "dcontext table\n");
|
|
for (i = 0; i < DPTRTABLE_LEN;) {
|
|
seq_printf(s, "%08x: ", octrlg_adr_table(dcontext, i));
|
|
for (k = 0; k < 16 && i < GPIXTABLE_LEN; k++, i++)
|
|
seq_printf(s, "%08x ", octrlg_r32(dcontext[i]));
|
|
seq_printf(s, "\n");
|
|
}
|
|
}
|
|
|
|
#endif
|