Commit Graph

1129 Commits

Author SHA1 Message Date
Xavier Arteaga e832769ae6 Updated copyright 2020-03-16 11:26:06 +01:00
yagoda 943d90bc48 consolidating different ringbuffer functionalities into one, adding unit tests for ringbuffer 2020-03-16 07:48:10 +01:00
Daniel Willmann 275f26d875 liblte_mme.h: Add/fix UE_TEST_LOOP/DEACT_TEST_MODE msg types 2020-03-15 18:27:51 +01:00
Francisco Paisana 5330249625 created tti_point type and unit test. Added also the tti_point to the scheduler harqs, and rrc procedure 2020-03-13 19:20:40 +00:00
Xavier Arteaga 5af89513eb use double precission for frequency in srsue and srsenb 2020-03-13 14:01:58 +01:00
Xavier Arteaga 834a081c09 Add EPRE measurement to PUSCH decoder 2020-03-13 14:01:58 +01:00
Ismael Gomez e8b8c9922e
Add RF per-channel frequency band constraints (#1026) 2020-03-12 23:06:09 +01:00
Francisco Paisana 7548402632 change scell activation interface to use arrays. Added a method to the scheduler to get the current set of activated carriers 2020-03-11 21:56:33 +01:00
Xavier Arteaga 590847e794 TTI semaphore requires protection in wait_all 2020-03-11 21:17:13 +01:00
Xavier Arteaga 76408b195e Rename TX_DELAY and FDD_HARQ_DELAY_MS 2020-03-11 21:16:36 +01:00
Xavier Arteaga 65711d06dc PRACH TA base default to 0 and apply clang-format 2020-03-11 16:58:00 +01:00
Xavier Arteaga e8f9bfc6ba Addition of PRACH TA correction 2020-03-11 16:25:56 +01:00
Andre Puschmann a8acd235f6 extend eNB MAC to support multiple CC per UE
- add tx/rx softbuffers for each CC that a UE might have
- make sure to call assign correct buffers when iterating
  over the CC for UL/DL grant assignment
2020-03-11 10:16:23 +01:00
Pedro Alvarez 96c82b3fc6 Moved PDCP configs to pdcp_config.h. Added `as_security_cfg_t` structure to hold access stratum keys.
Refactored PDCP, RRC and USIM accordingly.
2020-03-11 09:00:38 +00:00
Francisco Paisana 9ad80ee29f added initial_dl_cqi to the enb rr.cfg parser 2020-03-10 22:06:07 +00:00
Francisco Paisana fad897cb35 DL scheduler metric now takes into account the min and max of RBGs possible. This is to forbid segmentation of SRB0 allocations 2020-03-10 22:06:07 +00:00
Ismael Gomez bf6db92f04 Reset SRS properly on PHY defaults 2020-03-10 17:25:48 +01:00
Andre Puschmann f2e1bfa699 refactor naming for s/p/cell structs and {enb,ue}_cc_idx 2020-03-10 15:01:00 +01:00
Francisco Paisana 639f473042 fixed unsigned signed comparison 2020-03-10 14:17:49 +01:00
Francisco Paisana 1e63fa41cf made ue_cc_idx int to set to -1 for rar and bc allocs 2020-03-10 14:17:49 +01:00
Francisco Paisana f3c3c52fcd added ue_cc_idx to dci allocation 2020-03-10 14:17:49 +01:00
Francisco Paisana e62972d38e fix fdd delays in scheduler 2020-03-10 14:17:49 +01:00
Xavier Arteaga 002a68e183 SRSENB: hard-coded parametrized PUCCH DMRS correlation threshold 2020-03-10 09:19:54 +01:00
Xavier Arteaga 64caa4321b Fix UL control decoding. Some minor aesthetic changes. 2020-03-10 09:19:54 +01:00
Xavier Arteaga 44a5ce172e Added vector srslte_vec_avg_power_sf 2020-03-10 09:19:54 +01:00
Andre Puschmann 2edecea33e fix SIB transmission for CA
Avoid double buffering of SIBs in MAC as this would require one buffer for each CC.
Instead, use byte_buffer managed by RRC that contains packed SIBs to avoid
double memcpy for each SIB tx. Only use MAC provided buffer in error case.

Also avoid MAC calling RLC for each SIB and call RRC directly.
2020-03-09 14:18:09 +01:00
Andre Puschmann 120ad76c63 refactor cell param handling and fix SIB transmissions
- move cell specific eNB params to cell list in rr.conf
- make sure DL EARFCN and DL freq can be used to manually overwrite a single cell config
- fix SIB packing and transmission for multi cell configs
- introduce cell list to MAC
- adapt default enb.conf.example and rr.conf.example
2020-03-06 16:20:44 +01:00
Ismael Gomez 4e12405fff
Remove radio_multi class and organize channels, ports and carrier buffers (#1019) 2020-03-06 15:26:48 +01:00
Xavier Arteaga a968fb02d3 Increase PUCCH correlatiion threasholds 2020-03-06 13:58:49 +01:00
Xavier Arteaga da701cd82b SRSENB: Added PUSCH TA and EVM measurement. Some more PHY cleanup. 2020-03-06 13:58:49 +01:00
Xavier Arteaga 47cbbcbd57 Improve PUSCH UCI decoder 2020-03-06 13:58:49 +01:00
Pedro Alvarez bd3598f774 Moved srsEPC to the new S1AP library. Deleted liblte_s1ap.cc and liblte_s1ap.h. 2020-03-06 11:57:07 +00:00
Xavier Arteaga 96ffe1c3ad Commented class tti_semaphore 2020-03-06 12:24:28 +01:00
Francisco Paisana a6320f93b8 remove remaining const_casts 2020-03-05 20:23:07 +00:00
Francisco Paisana ec1f1cc677 remove const_casts from scheduler. Fix ODR issue 2020-03-05 20:23:07 +00:00
Andre Puschmann 664170fec6 pcap: add CC index when writing PCAP 2020-03-05 20:46:14 +01:00
Pedro Alvarez afc209711c Fix jump depending on uninitialized variable in srsenb::sched_ue::set_bearer_cfg_unlocked 2020-03-04 22:03:17 +01:00
Francisco Paisana 62609fdc11 fixed some logs. Also now use one single log obj for all the asn1 2020-03-03 21:26:50 +00:00
Francisco Paisana fed06138b9 moved rach_detected to stack thread. Created a more friendly interface to enqueue tasks in stack 2020-03-03 21:03:21 +00:00
Andre Puschmann e4b5fa122f add set_cell() call to PSCCH and allocate for max PRB in pscch_init() 2020-03-03 16:22:51 +01:00
Andre Puschmann 151ce10a96 remove SL specific CFO correction method 2020-03-03 16:22:51 +01:00
Andre Puschmann 09f7355870 use srslte_cell_sl_t in PSCCH 2020-03-03 16:22:51 +01:00
Andre Puschmann 14000f7ae7 adding phy_common_sl.{c,h} 2020-03-03 16:22:51 +01:00
Andre Puschmann 8b70ff7654 simplify SL chest and add RSRP and sync error measurements 2020-03-03 16:22:51 +01:00
Tiago Alves cabd9ae742 baseline implementation of pscch 2020-03-03 16:22:51 +01:00
Andre Puschmann a8bbe551ac move thread class into srslte namespace to avoid ambiguity between std::thread 2020-03-03 16:22:04 +01:00
Francisco Paisana ad9e126299 test for different enb_cc_idxs as pcell. Bug fixes 2020-03-02 16:33:31 +00:00
Xavier Arteaga 125747ae4a Added external C to phy_common header and ACK/NACK feedack mode parser 2020-03-02 12:19:09 +01:00
Xavier Arteaga a4135e41a5 Added PUCCH collision checker 2020-03-02 12:19:09 +01:00
Xavier Arteaga f35ed14f76 SRSENB: refactored PHY common UE database 2020-03-02 12:19:09 +01:00