SRSUE: SCell parameters condensed in a single structure
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@ -78,13 +78,15 @@ public:
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uint32_t pcell_report_period;
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bool pcell_first_measurement;
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// SCell EARFCN and PCI list
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uint32_t scell_earfcn[SRSLTE_MAX_CARRIERS - 1] = {};
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uint32_t scell_pci[SRSLTE_MAX_CARRIERS - 1] = {};
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// SCell EARFCN, PCI, configured and enabled list
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typedef struct {
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uint32_t earfcn = 0;
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uint32_t pci = 0;
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bool configured = false;
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bool enabled = false;
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} scell_cfg_t;
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scell_cfg_t scell_cfg[SRSLTE_MAX_CARRIERS];
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// SCell enable for Activation / Deactivation
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bool scell_configured[SRSLTE_MAX_CARRIERS];
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bool scell_enable[SRSLTE_MAX_CARRIERS]; /* Entry index 0 is reserved, do NOT use it for PCell */
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bool multiple_csi_request_enabled; /* True means cross scheduling enabled */
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bool cif_enabled; /* True means cross scheduling enabled */
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bool srs_request_enabled;
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@ -694,7 +694,7 @@ bool cc_worker::work_ul(srslte_uci_data_t* uci_data)
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set_uci_aperiodic_cqi(uci_data);
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} else {
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/* Check PCell and enabled secondary cells */
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if (cc_idx == 0 || phy->scell_enable[cc_idx]) {
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if (cc_idx == 0 || phy->scell_cfg[cc_idx].enabled) {
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set_uci_periodic_cqi(uci_data);
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}
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}
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@ -918,7 +918,7 @@ void cc_worker::set_uci_ack(srslte_uci_data_t* uci_data,
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// Only PCell generates ACK for all SCell
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for (uint32_t cc_idx = 0; cc_idx < phy->args->nof_carriers; cc_idx++) {
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if (cc_idx == 0 || phy->scell_configured[cc_idx]) {
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if (cc_idx == 0 || phy->scell_cfg[cc_idx].configured) {
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phy->get_dl_pending_ack(&sf_cfg_ul, cc_idx, &ack_info.cc[cc_idx]);
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nof_configured_carriers++;
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}
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@ -479,7 +479,7 @@ void phy::set_config_scell(asn1::rrc::scell_to_add_mod_r10_s* scell_config)
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scell_sync.at(m->radio_idx - 1)->set_scell_cell(cc_idx, &cell, earfcn);
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} else {
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// Change frequency only if the earfcn was modified
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if (common.scell_earfcn[cc_idx - 1] != earfcn) {
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if (common.scell_cfg[cc_idx].earfcn != earfcn) {
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float dl_freq = srslte_band_fd(earfcn) * 1e6f;
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float ul_freq = srslte_band_fu(srslte_band_ul_earfcn(earfcn)) * 1e6f;
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for (uint32_t p = 0; p < common.args->nof_rx_ant; p++) {
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@ -490,11 +490,10 @@ void phy::set_config_scell(asn1::rrc::scell_to_add_mod_r10_s* scell_config)
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}
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// Store SCell earfcn and pci
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common.scell_earfcn[cc_idx - 1] = earfcn;
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common.scell_pci[cc_idx - 1] = cell.id;
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// Set SCell as configured
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common.scell_configured[cc_idx] = true;
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common.scell_cfg[cc_idx].earfcn = earfcn;
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common.scell_cfg[cc_idx].pci = cell.id;
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common.scell_cfg[cc_idx].configured = true;
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common.scell_cfg[cc_idx].enabled = false;
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} else {
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log_h->console("Received SCell configuration for index %d but there are not enough CC workers available\n",
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scell_config->s_cell_idx_r10);
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@ -706,6 +706,7 @@ void phy_common::reset()
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ZERO_OBJECT(avg_snr_db_cqi);
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ZERO_OBJECT(avg_rsrp);
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ZERO_OBJECT(avg_rsrp_dbm);
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ZERO_OBJECT(scell_cfg);
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avg_rsrq_db = 0;
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pcell_report_period = 20;
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@ -714,8 +715,6 @@ void phy_common::reset()
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is_first_of_burst[i] = true;
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}
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ZERO_OBJECT(scell_configured);
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ZERO_OBJECT(scell_enable);
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multiple_csi_request_enabled = false;
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cif_enabled = false;
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srs_request_enabled = false;
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@ -897,7 +896,7 @@ bool phy_common::is_mbsfn_sf(srslte_mbsfn_cfg_t* cfg, uint32_t phy_tti)
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void phy_common::enable_scell(uint32_t cc_idx, bool enable)
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{
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if (cc_idx < SRSLTE_MAX_CARRIERS) {
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scell_enable[cc_idx] = enable;
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scell_cfg[cc_idx].enabled = enable;
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}
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}
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@ -228,7 +228,7 @@ void sf_worker::work_imp()
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if (carrier_idx == 0 && phy->is_mbsfn_sf(&mbsfn_cfg, tti)) {
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cc_workers[0]->work_dl_mbsfn(mbsfn_cfg); // Don't do chest_ok in mbsfn since it trigger measurements
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} else {
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if ((carrier_idx == 0) || phy->scell_enable[carrier_idx]) {
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if ((carrier_idx == 0) || phy->scell_cfg[carrier_idx].enabled) {
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rx_signal_ok = cc_workers[carrier_idx]->work_dl_regular();
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}
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}
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@ -348,13 +348,13 @@ void sf_worker::update_measurements()
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// Send report for PCell
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phy->stack->new_phy_meas(phy->avg_rsrp_dbm[0], phy->avg_rsrq_db, tti);
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} else {
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// Send report for SCell (if it they are enabled)
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if (phy->scell_enable[cc_idx]) {
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// Send report for SCell (if enabled)
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if (phy->scell_cfg[cc_idx].enabled) {
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phy->stack->new_phy_meas(phy->avg_rsrp_dbm[cc_idx],
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phy->avg_rsrq_db,
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tti,
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phy->scell_earfcn[cc_idx - 1],
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phy->scell_pci[cc_idx - 1]);
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phy->scell_cfg[cc_idx].earfcn,
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phy->scell_cfg[cc_idx].pci);
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}
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}
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}
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