fixeria
/
srsRAN
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

RRC-PHY interface (#639) 

RRC-PHY interface refactor. Moved RRC-MAC interface to rrc_asn1_utils and created RRC-PHY interface also in rrc_asn1_utils. All ASN1 includes should be made from rrc_asn1_utils only keeping ue_interfaces clean of ASN1

Tested with different common and dedicated configurations (64QAM UL, 256QAM, CA, SRS enabled/disabled, etc)
This commit is contained in:
Ismael Gomez 2019-09-04 16:59:10 +02:00 committed by GitHub
parent 2079c1324c
commit bfddc55148
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
36 changed files with 1021 additions and 1136 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/examples/pdsch_ue.c
View File

@ -789,7 +789,7 @@ int main(int argc, char **argv) {
dl_sf.tti = tti;
dl_sf.sf_type = sf_type;
ue_dl_cfg.cfg.tm = (srslte_tm_t)tm;
ue_dl_cfg.pdsch_use_tbs_index_alt = prog_args.enable_256qam;
ue_dl_cfg.cfg.pdsch.use_tbs_index_alt = prog_args.enable_256qam;
if ((ue_dl_cfg.cfg.tm == SRSLTE_TM1 && cell.nof_ports == 1) ||
(ue_dl_cfg.cfg.tm > SRSLTE_TM1 && cell.nof_ports > 1)) {

37
lib/include/srslte/asn1/rrc_asn1_utils.h
View File

@ -34,7 +34,18 @@ struct plmn_id_s;
struct s_tmsi_s;
struct rlc_cfg_c;
struct srb_to_add_mod_s;
struct sched_request_cfg_c;
struct mac_main_cfg_s;
struct rach_cfg_common_s;
struct time_align_timer_opts;
struct phys_cfg_ded_s;
struct prach_cfg_info_s;
struct pdsch_cfg_common_s;
struct pusch_cfg_common_s;
struct pucch_cfg_common_s;
struct srs_ul_cfg_common_c;
struct ul_pwr_ctrl_common_s;
struct scell_to_add_mod_r10_s;
} // namespace rrc
} // namespace asn1
@ -49,9 +60,33 @@ void to_asn1(asn1::rrc::plmn_id_s* asn1_type, const plmn_id_t& cfg);
s_tmsi_t make_s_tmsi_t(const asn1::rrc::s_tmsi_s& asn1_type);
void to_asn1(asn1::rrc::s_tmsi_s* asn1_type, const s_tmsi_t& cfg);
/***************************
* RLC Config
**************************/
rlc_config_t make_rlc_config_t(const asn1::rrc::rlc_cfg_c& asn1_type);
rlc_config_t make_rlc_config_t(const asn1::rrc::srb_to_add_mod_s& asn1_type);
void to_asn1(asn1::rrc::rlc_cfg_c* asn1_type, const rlc_config_t& cfg);
/***************************
* MAC Config
**************************/
void set_mac_cfg_t_sched_request_cfg(mac_cfg_t* cfg, const asn1::rrc::sched_request_cfg_c& asn1_type);
void set_mac_cfg_t_main_cfg(mac_cfg_t* cfg, const asn1::rrc::mac_main_cfg_s& asn1_type);
void set_mac_cfg_t_rach_cfg_common(mac_cfg_t* cfg, const asn1::rrc::rach_cfg_common_s& asn1_type);
void set_mac_cfg_t_time_alignment(mac_cfg_t* cfg, const asn1::rrc::time_align_timer_opts asn1_type);
/***************************
* PHY Config
**************************/
void set_phy_cfg_t_dedicated_cfg(phy_cfg_t* cfg, const asn1::rrc::phys_cfg_ded_s& asn1_type);
void set_phy_cfg_t_common_prach(phy_cfg_t* cfg, const asn1::rrc::prach_cfg_info_s* asn1_type, uint32_t root_seq_idx);
void set_phy_cfg_t_common_pdsch(phy_cfg_t* cfg, const asn1::rrc::pdsch_cfg_common_s& asn1_type);
void set_phy_cfg_t_common_pusch(phy_cfg_t* cfg, const asn1::rrc::pusch_cfg_common_s& asn1_type);
void set_phy_cfg_t_common_pucch(phy_cfg_t* cfg, const asn1::rrc::pucch_cfg_common_s& asn1_type);
void set_phy_cfg_t_common_srs(phy_cfg_t* cfg, const asn1::rrc::srs_ul_cfg_common_c& asn1_type);
void set_phy_cfg_t_common_pwr_ctrl(phy_cfg_t* cfg, const asn1::rrc::ul_pwr_ctrl_common_s& asn1_type);
void set_phy_cfg_t_scell_config(phy_cfg_t* cfg, const asn1::rrc::scell_to_add_mod_r10_s* asn1_type);
void set_phy_cfg_t_enable_64qam(phy_cfg_t* cfg, const bool enabled);
}
#endif // SRSLTE_RRC_ASN1_UTILS_H

154
lib/include/srslte/interfaces/rrc_interface_types.h
View File

@ -24,6 +24,7 @@
#include "srslte/common/bcd_helpers.h"
#include "srslte/config.h"
#include "srslte/srslte.h"
#include <string>
/************************
@ -292,6 +293,159 @@ public:
return rlc_cnfg;
}
};
/***************************
* MAC Config
**************************/
struct bsr_cfg_t {
int periodic_timer;
int retx_timer;
bsr_cfg_t() { reset(); }
void reset()
{
periodic_timer = -1;
retx_timer = 2560;
}
};
struct phr_cfg_t {
bool enabled;
int periodic_timer;
int prohibit_timer;
int db_pathloss_change;
bool extended;
phr_cfg_t() { reset(); }
void reset()
{
enabled = false;
periodic_timer = -1;
prohibit_timer = -1;
db_pathloss_change = -1;
extended = false;
}
};
struct sr_cfg_t {
bool enabled;
int dsr_transmax;
sr_cfg_t() { reset(); }
void reset()
{
enabled = false;
dsr_transmax = 0;
}
};
struct ul_harq_cfg_t {
uint32_t max_harq_msg3_tx;
uint32_t max_harq_tx;
ul_harq_cfg_t() { reset(); }
void reset()
{
max_harq_msg3_tx = 5;
max_harq_tx = 5;
}
};
struct rach_cfg_t {
bool enabled;
uint32_t nof_preambles;
uint32_t nof_groupA_preambles;
int32_t messagePowerOffsetGroupB;
uint32_t messageSizeGroupA;
uint32_t responseWindowSize;
uint32_t powerRampingStep;
uint32_t preambleTransMax;
int32_t iniReceivedTargetPower;
uint32_t contentionResolutionTimer;
uint32_t new_ra_msg_len;
rach_cfg_t() { reset(); }
void reset()
{
enabled = false;
nof_preambles = 0;
nof_groupA_preambles = 0;
messagePowerOffsetGroupB = 0;
messageSizeGroupA = 0;
responseWindowSize = 0;
powerRampingStep = 0;
preambleTransMax = 0;
iniReceivedTargetPower = 0;
contentionResolutionTimer = 0;
new_ra_msg_len = 0;
}
};
struct mac_cfg_t {
// Default constructor with default values as in 36.331 9.2.2
mac_cfg_t() { set_defaults(); }
void set_defaults()
{
rach_cfg.reset();
set_mac_main_cfg_default();
}
void set_mac_main_cfg_default()
{
bsr_cfg.reset();
phr_cfg.reset();
sr_cfg.reset();
harq_cfg.reset();
time_alignment_timer = -1;
}
bsr_cfg_t bsr_cfg;
phr_cfg_t phr_cfg;
sr_cfg_t sr_cfg;
rach_cfg_t rach_cfg;
ul_harq_cfg_t harq_cfg;
int time_alignment_timer;
};
/***************************
* PHY Config
**************************/
struct phy_cfg_t {
phy_cfg_t()
{
ZERO_OBJECT(ul_cfg);
ZERO_OBJECT(dl_cfg);
set_defaults_common();
set_defaults_dedicated();
}
void set_defaults_common()
{
ul_cfg.pucch.delta_pucch_shift = 1;
ul_cfg.power_ctrl.delta_f_pucch[0] = 0;
ul_cfg.power_ctrl.delta_f_pucch[1] = 1;
ul_cfg.power_ctrl.delta_f_pucch[2] = 0;
ul_cfg.power_ctrl.delta_f_pucch[3] = 0;
ul_cfg.power_ctrl.delta_f_pucch[4] = 0;
}
void set_defaults_dedicated()
{
dl_cfg.tm = SRSLTE_TM1;
ul_cfg.pusch.uci_offset.I_offset_ack = 10;
ul_cfg.pusch.uci_offset.I_offset_cqi = 15;
ul_cfg.pusch.uci_offset.I_offset_ri = 12;
ul_cfg.power_ctrl.acc_enabled = true;
ul_cfg.power_ctrl.p_srs_offset = 7;
// Rest of default values are 0 or false
}
srslte_dl_cfg_t dl_cfg;
srslte_ul_cfg_t ul_cfg;
srslte_prach_cfg_t prach_cfg;
};
} // namespace srslte
#endif // SRSLTE_RRC_INTERFACE_TYPES_H

237
lib/include/srslte/interfaces/ue_interfaces.h
View File

@ -37,6 +37,7 @@
#include "srslte/common/interfaces_common.h"
#include "srslte/common/security.h"
#include "srslte/common/stack_procedure.h"
#include "srslte/interfaces/rrc_interface_types.h"
#include "srslte/phy/channel/channel.h"
#include "srslte/phy/rf/rf.h"
@ -315,30 +316,6 @@ public:
virtual void write_pdu_mch(uint32_t lcid, uint8_t *payload, uint32_t nof_bytes) = 0;
};
//BSR interface for MUX
class bsr_interface_mux
{
public:
typedef enum {
LONG_BSR,
SHORT_BSR,
TRUNC_BSR
} bsr_format_t;
typedef struct {
bsr_format_t format;
uint32_t buff_size[4];
} bsr_t;
/* MUX calls BSR to check if it can fit a BSR into PDU */
virtual bool need_to_send_bsr_on_ul_grant(uint32_t grant_size, bsr_t *bsr) = 0;
/* MUX calls BSR to let it generate a padding BSR if there is space in PDU */
virtual bool generate_padding_bsr(uint32_t nof_padding_bytes, bsr_t *bsr) = 0;
};
/** MAC interface
*
*/
@ -439,195 +416,12 @@ public:
uint64_t contention_id;
} ue_rnti_t;
typedef struct ul_harq_cfg_t {
uint32_t max_harq_msg3_tx;
uint32_t max_harq_tx;
ul_harq_cfg_t() { reset(); }
void reset()
{
max_harq_msg3_tx = 5;
max_harq_tx = 5;
}
} ul_harq_cfg_t;
};
/* Interface RRC -> MAC */
class mac_interface_rrc : public mac_interface_rrc_common
{
public:
typedef struct bsr_cfg_t {
int periodic_timer;
int retx_timer;
bsr_cfg_t() { reset(); }
void reset()
{
periodic_timer = -1;
retx_timer = 2560;
}
} bsr_cfg_t;
typedef struct phr_cfg_t {
bool enabled;
int periodic_timer;
int prohibit_timer;
int db_pathloss_change;
bool extended;
phr_cfg_t() { reset(); }
void reset()
{
enabled = false;
periodic_timer = -1;
prohibit_timer = -1;
db_pathloss_change = -1;
extended = false;
}
} phr_cfg_t;
typedef struct sr_cfg_t {
bool enabled;
int dsr_transmax;
sr_cfg_t() { reset(); }
void reset()
{
enabled = false;
dsr_transmax = 0;
}
} sr_cfg_t;
typedef struct rach_cfg_t {
bool enabled;
uint32_t nof_preambles;
uint32_t nof_groupA_preambles;
int32_t messagePowerOffsetGroupB;
uint32_t messageSizeGroupA;
uint32_t responseWindowSize;
uint32_t powerRampingStep;
uint32_t preambleTransMax;
int32_t iniReceivedTargetPower;
uint32_t contentionResolutionTimer;
uint32_t new_ra_msg_len;
rach_cfg_t() { reset(); }
void reset()
{
enabled = false;
nof_preambles = 0;
nof_groupA_preambles = 0;
messagePowerOffsetGroupB = 0;
messageSizeGroupA = 0;
responseWindowSize = 0;
powerRampingStep = 0;
preambleTransMax = 0;
iniReceivedTargetPower = 0;
contentionResolutionTimer = 0;
new_ra_msg_len = 0;
}
} rach_cfg_t;
class mac_cfg_t
{
public:
// Default constructor with default values as in 36.331 9.2.2
mac_cfg_t() { set_defaults(); }
void set_defaults()
{
rach_cfg.reset();
set_mac_main_cfg_default();
}
void set_mac_main_cfg_default()
{
bsr_cfg.reset();
phr_cfg.reset();
sr_cfg.reset();
harq_cfg.reset();
time_alignment_timer = -1;
}
// Called only if section is present
void set_sched_request_cfg(asn1::rrc::sched_request_cfg_c& cfg)
{
sr_cfg.enabled = cfg.type() == asn1::rrc::setup_e::setup;
if (sr_cfg.enabled) {
sr_cfg.dsr_transmax = cfg.setup().dsr_trans_max.to_number();
}
}
// MAC-MainConfig section is always present
void set_mac_main_cfg(asn1::rrc::mac_main_cfg_s& cfg)
{
// Update values only if each section is present
if (cfg.phr_cfg_present) {
phr_cfg.enabled = cfg.phr_cfg.type() == asn1::rrc::setup_e::setup;
if (phr_cfg.enabled) {
phr_cfg.prohibit_timer = cfg.phr_cfg.setup().prohibit_phr_timer.to_number();
phr_cfg.periodic_timer = cfg.phr_cfg.setup().periodic_phr_timer.to_number();
phr_cfg.db_pathloss_change = cfg.phr_cfg.setup().dl_pathloss_change.to_number();
}
}
if (cfg.mac_main_cfg_v1020.is_present()) {
asn1::rrc::mac_main_cfg_s::mac_main_cfg_v1020_s_* mac_main_cfg_v1020 = cfg.mac_main_cfg_v1020.get();
phr_cfg.extended = mac_main_cfg_v1020->extended_phr_r10_present;
}
if (cfg.ul_sch_cfg_present) {
bsr_cfg.periodic_timer = cfg.ul_sch_cfg.periodic_bsr_timer.to_number();
bsr_cfg.retx_timer = cfg.ul_sch_cfg.retx_bsr_timer.to_number();
if (cfg.ul_sch_cfg.max_harq_tx_present) {
harq_cfg.max_harq_tx = cfg.ul_sch_cfg.max_harq_tx.to_number();
}
}
// TimeAlignmentDedicated overwrites Common??
time_alignment_timer = cfg.time_align_timer_ded.to_number();
}
// RACH-Common section is always present
void set_rach_cfg_common(asn1::rrc::rach_cfg_common_s& cfg)
{
// Preamble info
rach_cfg.nof_preambles = cfg.preamb_info.nof_ra_preambs.to_number();
if (cfg.preamb_info.preambs_group_a_cfg_present) {
rach_cfg.nof_groupA_preambles = cfg.preamb_info.preambs_group_a_cfg.size_of_ra_preambs_group_a.to_number();
rach_cfg.messageSizeGroupA = cfg.preamb_info.preambs_group_a_cfg.msg_size_group_a.to_number();
rach_cfg.messagePowerOffsetGroupB = cfg.preamb_info.preambs_group_a_cfg.msg_pwr_offset_group_b.to_number();
} else {
rach_cfg.nof_groupA_preambles = 0;
}
// Power ramping
rach_cfg.powerRampingStep = cfg.pwr_ramp_params.pwr_ramp_step.to_number();
rach_cfg.iniReceivedTargetPower = cfg.pwr_ramp_params.preamb_init_rx_target_pwr.to_number();
// Supervision info
rach_cfg.preambleTransMax = cfg.ra_supervision_info.preamb_trans_max.to_number();
rach_cfg.responseWindowSize = cfg.ra_supervision_info.ra_resp_win_size.to_number();
rach_cfg.contentionResolutionTimer = cfg.ra_supervision_info.mac_contention_resolution_timer.to_number();
// HARQ Msg3
harq_cfg.max_harq_msg3_tx = cfg.max_harq_msg3_tx;
}
void set_time_alignment(asn1::rrc::time_align_timer_e time_alignment_timer)
{
this->time_alignment_timer = time_alignment_timer.to_number();
}
bsr_cfg_t& get_bsr_cfg() { return bsr_cfg; }
phr_cfg_t& get_phr_cfg() { return phr_cfg; }
rach_cfg_t& get_rach_cfg() { return rach_cfg; }
sr_cfg_t& get_sr_cfg() { return sr_cfg; }
ul_harq_cfg_t& get_harq_cfg() { return harq_cfg; }
int get_time_alignment_timer() { return time_alignment_timer; }
private:
bsr_cfg_t bsr_cfg;
phr_cfg_t phr_cfg;
sr_cfg_t sr_cfg;
rach_cfg_t rach_cfg;
ul_harq_cfg_t harq_cfg;
int time_alignment_timer;
};
virtual void clear_rntis() = 0;
/* Instructs the MAC to start receiving BCCH */
@ -645,7 +439,7 @@ public:
virtual uint32_t get_current_tti() = 0;
virtual void set_config(mac_cfg_t& mac_cfg) = 0;
virtual void set_config(srslte::mac_cfg_t& mac_cfg) = 0;
virtual void get_rntis(ue_rnti_t *rntis) = 0;
virtual void set_contention_id(uint64_t uecri) = 0;
@ -780,19 +574,6 @@ public:
class phy_interface_rrc_lte
{
public:
struct phy_cfg_common_t {
asn1::rrc::prach_cfg_sib_s prach_cnfg;
asn1::rrc::pdsch_cfg_common_s pdsch_cnfg;
asn1::rrc::pusch_cfg_common_s pusch_cnfg;
asn1::rrc::phich_cfg_s phich_cnfg;
asn1::rrc::pucch_cfg_common_s pucch_cnfg;
asn1::rrc::srs_ul_cfg_common_c srs_ul_cnfg;
asn1::rrc::ul_pwr_ctrl_common_s ul_pwr_ctrl;
asn1::rrc::tdd_cfg_s tdd_cnfg;
asn1::rrc::srs_ant_port_e ant_info;
bool rrc_enable_64qam;
};
struct phy_cfg_mbsfn_t {
asn1::rrc::mbsfn_sf_cfg_s mbsfn_subfr_cnfg;
asn1::rrc::mbms_notif_cfg_r9_s mbsfn_notification_cnfg;
@ -800,19 +581,15 @@ public:
asn1::rrc::mcch_msg_s mcch;
};
typedef struct {
asn1::rrc::phys_cfg_ded_s dedicated;
phy_cfg_common_t common;
phy_cfg_mbsfn_t mbsfn;
} phy_cfg_t;
virtual void get_current_cell(srslte_cell_t *cell, uint32_t *current_earfcn = NULL) = 0;
virtual uint32_t get_current_earfcn() = 0;
virtual uint32_t get_current_pci() = 0;
virtual void set_config(phy_cfg_t* config) = 0;
virtual void set_config_scell(asn1::rrc::scell_to_add_mod_r10_s* scell_config) = 0;
virtual void set_config_tdd(asn1::rrc::tdd_cfg_s* tdd) = 0;
virtual void set_config(srslte::phy_cfg_t& config,
uint32_t cc_idx = 0,
uint32_t earfcn = 0,
srslte_cell_t* cell_info = nullptr) = 0;
virtual void set_config_tdd(srslte_tdd_config_t& tdd_config) = 0;
virtual void set_config_mbsfn_sib2(asn1::rrc::sib_type2_s* sib2) = 0;
virtual void set_config_mbsfn_sib13(asn1::rrc::sib_type13_r9_s* sib13) = 0;
virtual void set_config_mbsfn_mcch(asn1::rrc::mcch_msg_s* mcch) = 0;

2
lib/include/srslte/phy/ch_estimation/refsignal_ul.h
View File

@ -64,6 +64,8 @@ typedef struct SRSLTE_API {
uint32_t I_srs;
uint32_t k_tc;
uint32_t n_rrc;
bool dedicated_enabled;
bool common_enabled;
bool configured;
} srslte_refsignal_srs_cfg_t;

1
lib/include/srslte/phy/phch/dci.h
View File

@ -52,6 +52,7 @@
typedef struct {
bool multiple_csi_request_enabled;
bool cif_enabled;
bool cif_present;
bool srs_request_enabled;
bool ra_format_enabled;
} srslte_dci_cfg_t;

1
lib/include/srslte/phy/phch/pdsch_cfg.h
View File

@ -60,6 +60,7 @@ typedef struct SRSLTE_API {
float rs_power;
bool power_scale;
bool csi_enable;
bool use_tbs_index_alt;
union {
srslte_softbuffer_tx_t* tx[SRSLTE_MAX_CODEWORDS];

2
lib/include/srslte/phy/phch/pucch_cfg.h
View File

@ -62,7 +62,7 @@ typedef struct SRSLTE_API {
uint32_t n_pucch_2;
uint32_t n_pucch_sr;
bool simul_cqi_ack;
bool tdd_ack_bundle; // if false, multiplex
bool tdd_ack_multiplex; // if false, bundle
bool sps_enabled;
uint32_t tpc_for_pucch;

2
lib/include/srslte/phy/phch/uci_cfg.h
View File

@ -39,7 +39,7 @@ typedef struct SRSLTE_API {
uint32_t N_bundle;
uint32_t tdd_ack_M;
uint32_t tdd_ack_m;
bool tdd_is_bundling;
bool tdd_is_multiplex;
bool has_scell_ack;
} srslte_uci_cfg_ack_t;

9
lib/include/srslte/phy/ue/ue_dl.h
View File

@ -112,16 +112,15 @@ typedef struct SRSLTE_API {
typedef struct SRSLTE_API {
srslte_cqi_report_cfg_t cqi_report;
srslte_pdsch_cfg_t pdsch;
srslte_dci_cfg_t dci;
srslte_tm_t tm;
} srslte_dl_cfg_t;
typedef struct SRSLTE_API {
srslte_dl_cfg_t cfg;
srslte_chest_dl_cfg_t chest_cfg;
srslte_dci_cfg_t dci_cfg;
uint32_t last_ri;
float snr_to_cqi_offset;
bool pdsch_use_tbs_index_alt;
} srslte_ue_dl_cfg_t;
typedef struct {
@ -149,7 +148,7 @@ typedef struct {
srslte_ack_nack_feedback_mode_t ack_nack_feedback_mode;
bool is_grant_available;
bool is_pusch_available;
bool tdd_ack_bundle;
bool tdd_ack_multiplex;
bool simul_cqi_ack;
} srslte_pdsch_ack_t;
@ -182,13 +181,13 @@ SRSLTE_API int srslte_ue_dl_decode_fft_estimate_noguru(srslte_ue_dl_t* q,
/* Finds UL/DL DCI in the signal processed in a previous call to decode_fft_estimate() */
SRSLTE_API int srslte_ue_dl_find_ul_dci(srslte_ue_dl_t* q,
srslte_dl_sf_cfg_t* sf,
srslte_ue_dl_cfg_t* cfg,
srslte_ue_dl_cfg_t* dl_cfg,
uint16_t rnti,
srslte_dci_ul_t dci_msg[SRSLTE_MAX_DCI_MSG]);
SRSLTE_API int srslte_ue_dl_find_dl_dci(srslte_ue_dl_t* q,
srslte_dl_sf_cfg_t* sf,
srslte_ue_dl_cfg_t* cfg,
srslte_ue_dl_cfg_t* dl_cfg,
uint16_t rnti,
srslte_dci_dl_t dci_msg[SRSLTE_MAX_DCI_MSG]);

529
lib/src/asn1/rrc_asn1_utils.cc
View File

@ -74,6 +74,32 @@ void to_asn1(asn1::rrc::s_tmsi_s* asn1_type, const s_tmsi_t& cfg)
asn1_type->m_tmsi.from_number(cfg.m_tmsi);
}
/***************************
* CQI Report Aperiodic
**************************/
srslte_cqi_report_mode_t make_aperiodic_mode(const asn1::rrc::cqi_report_mode_aperiodic_e asn_mode)
{
switch (asn_mode) {
case asn1::rrc::cqi_report_mode_aperiodic_e::rm12:
return SRSLTE_CQI_MODE_12;
case asn1::rrc::cqi_report_mode_aperiodic_e::rm20:
return SRSLTE_CQI_MODE_20;
case asn1::rrc::cqi_report_mode_aperiodic_e::rm22:
return SRSLTE_CQI_MODE_22;
case asn1::rrc::cqi_report_mode_aperiodic_e::rm30:
return SRSLTE_CQI_MODE_30;
case asn1::rrc::cqi_report_mode_aperiodic_e::rm31:
return SRSLTE_CQI_MODE_31;
case asn1::rrc::cqi_report_mode_aperiodic_e::rm10_v1310:
case asn1::rrc::cqi_report_mode_aperiodic_e::rm11_v1310:
case asn1::rrc::cqi_report_mode_aperiodic_e::rm32_v1250:
fprintf(stderr, "Aperiodic mode %s not handled\n", asn_mode.to_string().c_str());
default:
return SRSLTE_CQI_MODE_NA;
}
}
/***************************
* Establishment Cause
**************************/
@ -155,4 +181,507 @@ void to_asn1(asn1::rrc::rlc_cfg_c* asn1_type, const srslte::rlc_config_t& cfg)
}
/***************************
* MAC Config
**************************/
void set_mac_cfg_t_sched_request_cfg(mac_cfg_t* cfg, const asn1::rrc::sched_request_cfg_c& asn1_type)
{
cfg->sr_cfg.enabled = asn1_type.type() == asn1::rrc::setup_e::setup;
if (cfg->sr_cfg.enabled) {
cfg->sr_cfg.dsr_transmax = asn1_type.setup().dsr_trans_max.to_number();
}
}
// MAC-MainConfig section is always present
void set_mac_cfg_t_main_cfg(mac_cfg_t* cfg, const asn1::rrc::mac_main_cfg_s& asn1_type)
{
// Update values only if each section is present
if (asn1_type.phr_cfg_present) {
cfg->phr_cfg.enabled = asn1_type.phr_cfg.type() == asn1::rrc::setup_e::setup;
if (cfg->phr_cfg.enabled) {
cfg->phr_cfg.prohibit_timer = asn1_type.phr_cfg.setup().prohibit_phr_timer.to_number();
cfg->phr_cfg.periodic_timer = asn1_type.phr_cfg.setup().periodic_phr_timer.to_number();
cfg->phr_cfg.db_pathloss_change = asn1_type.phr_cfg.setup().dl_pathloss_change.to_number();
}
}
if (asn1_type.mac_main_cfg_v1020.is_present()) {
cfg->phr_cfg.extended = asn1_type.mac_main_cfg_v1020.get()->extended_phr_r10_present;
}
if (asn1_type.ul_sch_cfg_present) {
cfg->bsr_cfg.periodic_timer = asn1_type.ul_sch_cfg.periodic_bsr_timer.to_number();
cfg->bsr_cfg.retx_timer = asn1_type.ul_sch_cfg.retx_bsr_timer.to_number();
if (asn1_type.ul_sch_cfg.max_harq_tx_present) {
cfg->harq_cfg.max_harq_tx = asn1_type.ul_sch_cfg.max_harq_tx.to_number();
}
}
// TimeAlignmentDedicated overwrites Common??
cfg->time_alignment_timer = asn1_type.time_align_timer_ded.to_number();
}
// RACH-Common section is always present
void set_mac_cfg_t_rach_cfg_common(mac_cfg_t* cfg, const asn1::rrc::rach_cfg_common_s& asn1_type)
{
// Preamble info
cfg->rach_cfg.nof_preambles = asn1_type.preamb_info.nof_ra_preambs.to_number();
if (asn1_type.preamb_info.preambs_group_a_cfg_present) {
cfg->rach_cfg.nof_groupA_preambles =
asn1_type.preamb_info.preambs_group_a_cfg.size_of_ra_preambs_group_a.to_number();
cfg->rach_cfg.messageSizeGroupA = asn1_type.preamb_info.preambs_group_a_cfg.msg_size_group_a.to_number();
cfg->rach_cfg.messagePowerOffsetGroupB =
asn1_type.preamb_info.preambs_group_a_cfg.msg_pwr_offset_group_b.to_number();
} else {
cfg->rach_cfg.nof_groupA_preambles = 0;
}
// Power ramping
cfg->rach_cfg.powerRampingStep = asn1_type.pwr_ramp_params.pwr_ramp_step.to_number();
cfg->rach_cfg.iniReceivedTargetPower = asn1_type.pwr_ramp_params.preamb_init_rx_target_pwr.to_number();
// Supervision info
cfg->rach_cfg.preambleTransMax = asn1_type.ra_supervision_info.preamb_trans_max.to_number();
cfg->rach_cfg.responseWindowSize = asn1_type.ra_supervision_info.ra_resp_win_size.to_number();
cfg->rach_cfg.contentionResolutionTimer = asn1_type.ra_supervision_info.mac_contention_resolution_timer.to_number();
// HARQ Msg3
cfg->harq_cfg.max_harq_msg3_tx = asn1_type.max_harq_msg3_tx;
}
void set_mac_cfg_t_time_alignment(mac_cfg_t* cfg, const asn1::rrc::time_align_timer_opts asn1_type)
{
cfg->time_alignment_timer = asn1_type.to_number();
}
void set_phy_cfg_t_dedicated_cfg(phy_cfg_t* cfg, const asn1::rrc::phys_cfg_ded_s& asn1_type)
{
if (asn1_type.pucch_cfg_ded_present) {
if (asn1_type.pucch_cfg_ded.tdd_ack_nack_feedback_mode_present) {
cfg->ul_cfg.pucch.tdd_ack_multiplex = asn1_type.pucch_cfg_ded.tdd_ack_nack_feedback_mode ==
asn1::rrc::pucch_cfg_ded_s::tdd_ack_nack_feedback_mode_e_::mux;
} else {
cfg->ul_cfg.pucch.tdd_ack_multiplex = false;
}
}
if (asn1_type.pucch_cfg_ded_v1020.is_present()) {
auto* pucch_cfg_ded = asn1_type.pucch_cfg_ded_v1020.get();
if (pucch_cfg_ded->pucch_format_r10_present) {
typedef asn1::rrc::pucch_cfg_ded_v1020_s::pucch_format_r10_c_ pucch_format_r10_t;
auto* pucch_format_r10 = &pucch_cfg_ded->pucch_format_r10;
if (pucch_format_r10->type() == pucch_format_r10_t::types::format3_r10) {
// Select feedback mode
cfg->ul_cfg.pucch.ack_nack_feedback_mode = SRSLTE_PUCCH_ACK_NACK_FEEDBACK_MODE_PUCCH3;
auto* format3_r13 = &pucch_format_r10->format3_r10();
for (uint32_t n = 0; n < SRSLTE_MIN(format3_r13->n3_pucch_an_list_r13.size(), SRSLTE_PUCCH_SIZE_AN_CS); n++) {
cfg->ul_cfg.pucch.n3_pucch_an_list[n] = format3_r13->n3_pucch_an_list_r13[n];
}
if (format3_r13->two_ant_port_activ_pucch_format3_r13_present) {
if (format3_r13->two_ant_port_activ_pucch_format3_r13.type() == asn1::rrc::setup_e::setup) {
// TODO: UL MIMO Configure PUCCH two antenna port
} else {
// TODO: UL MIMO Disable two antenna port
}
}
} else if (pucch_format_r10->type() == asn1::rrc::pucch_cfg_ded_v1020_s::pucch_format_r10_c_::types::ch_sel_r10) {
typedef pucch_format_r10_t::ch_sel_r10_s_ ch_sel_r10_t;
auto* ch_sel_r10 = &pucch_format_r10->ch_sel_r10();
if (ch_sel_r10->n1_pucch_an_cs_r10_present) {
typedef ch_sel_r10_t::n1_pucch_an_cs_r10_c_ n1_pucch_an_cs_r10_t;
auto* n1_pucch_an_cs_r10 = &ch_sel_r10->n1_pucch_an_cs_r10;
if (n1_pucch_an_cs_r10->type() == asn1::rrc::setup_e::setup) {
// Select feedback mode
cfg->ul_cfg.pucch.ack_nack_feedback_mode = SRSLTE_PUCCH_ACK_NACK_FEEDBACK_MODE_CS;
typedef n1_pucch_an_cs_r10_t::setup_s_::n1_pucch_an_cs_list_r10_l_ n1_pucch_an_cs_list_r10_t;
n1_pucch_an_cs_list_r10_t n1_pucch_an_cs_list =
ch_sel_r10->n1_pucch_an_cs_r10.setup().n1_pucch_an_cs_list_r10;
for (uint32_t i = 0; i < SRSLTE_MIN(n1_pucch_an_cs_list.size(), SRSLTE_PUCCH_NOF_AN_CS); i++) {
asn1::rrc::n1_pucch_an_cs_r10_l n1_pucch_an_cs = n1_pucch_an_cs_list[i];
for (uint32_t j = 0; j < SRSLTE_PUCCH_SIZE_AN_CS; j++) {
cfg->ul_cfg.pucch.n1_pucch_an_cs[j][i] = n1_pucch_an_cs[j];
}
}
} else {
cfg->ul_cfg.pucch.ack_nack_feedback_mode = SRSLTE_PUCCH_ACK_NACK_FEEDBACK_MODE_NORMAL;
}
}
} else {
// Do nothing
}
}
}
if (asn1_type.pusch_cfg_ded_present) {
cfg->ul_cfg.pusch.uci_offset.I_offset_ack = asn1_type.pusch_cfg_ded.beta_offset_ack_idx;
cfg->ul_cfg.pusch.uci_offset.I_offset_cqi = asn1_type.pusch_cfg_ded.beta_offset_cqi_idx;
cfg->ul_cfg.pusch.uci_offset.I_offset_ri = asn1_type.pusch_cfg_ded.beta_offset_ri_idx;
}
if (asn1_type.ul_pwr_ctrl_ded_present) {
cfg->ul_cfg.power_ctrl.p0_ue_pusch = asn1_type.ul_pwr_ctrl_ded.p0_ue_pusch;
cfg->ul_cfg.power_ctrl.delta_mcs_based =
asn1_type.ul_pwr_ctrl_ded.delta_mcs_enabled == asn1::rrc::ul_pwr_ctrl_ded_s::delta_mcs_enabled_e_::en0;
cfg->ul_cfg.power_ctrl.acc_enabled = asn1_type.ul_pwr_ctrl_ded.accumulation_enabled;
cfg->ul_cfg.power_ctrl.p0_ue_pucch = asn1_type.ul_pwr_ctrl_ded.p0_ue_pucch;
cfg->ul_cfg.power_ctrl.p_srs_offset = asn1_type.ul_pwr_ctrl_ded.p_srs_offset;
}
if (asn1_type.ul_pwr_ctrl_ded.filt_coef_present) {
// TODO
}
if (asn1_type.tpc_pdcch_cfg_pucch_present) {
// TODO
}
if (asn1_type.tpc_pdcch_cfg_pusch_present) {
// TODO
}
if (asn1_type.cqi_report_cfg_present) {
if (asn1_type.cqi_report_cfg.cqi_report_periodic_present) {
cfg->dl_cfg.cqi_report.periodic_configured =
asn1_type.cqi_report_cfg.cqi_report_periodic.type() == asn1::rrc::setup_e::setup;
if (cfg->dl_cfg.cqi_report.periodic_configured) {
cfg->ul_cfg.pucch.n_pucch_2 = asn1_type.cqi_report_cfg.cqi_report_periodic.setup().cqi_pucch_res_idx;
cfg->ul_cfg.pucch.simul_cqi_ack = asn1_type.cqi_report_cfg.cqi_report_periodic.setup().simul_ack_nack_and_cqi;
cfg->dl_cfg.cqi_report.pmi_idx = asn1_type.cqi_report_cfg.cqi_report_periodic.setup().cqi_pmi_cfg_idx;
cfg->dl_cfg.cqi_report.format_is_subband =
asn1_type.cqi_report_cfg.cqi_report_periodic.setup().cqi_format_ind_periodic.type().value ==
asn1::rrc::cqi_report_periodic_c::setup_s_::cqi_format_ind_periodic_c_::types::subband_cqi;
if (cfg->dl_cfg.cqi_report.format_is_subband) {
cfg->dl_cfg.cqi_report.subband_size =
asn1_type.cqi_report_cfg.cqi_report_periodic.setup().cqi_format_ind_periodic.subband_cqi().k;
}
if (asn1_type.cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx_present) {
cfg->dl_cfg.cqi_report.ri_idx = asn1_type.cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx;
cfg->dl_cfg.cqi_report.ri_idx_present = true;
} else {
cfg->dl_cfg.cqi_report.ri_idx_present = false;
}
} else {
cfg->ul_cfg.pucch.n_pucch_2 = 0;
cfg->ul_cfg.pucch.simul_cqi_ack = false;
}
}
if (asn1_type.cqi_report_cfg.cqi_report_mode_aperiodic_present) {
cfg->dl_cfg.cqi_report.aperiodic_configured = true;
cfg->dl_cfg.cqi_report.aperiodic_mode = make_aperiodic_mode(asn1_type.cqi_report_cfg.cqi_report_mode_aperiodic);
}
}
if (asn1_type.cqi_report_cfg_pcell_v1250.is_present()) {
auto cqi_report_cfg_pcell_v1250 = asn1_type.cqi_report_cfg_pcell_v1250.get();
if (cqi_report_cfg_pcell_v1250->alt_cqi_table_r12_present) {
cfg->dl_cfg.pdsch.use_tbs_index_alt = true;
}
} else {
cfg->dl_cfg.pdsch.use_tbs_index_alt = false;
}
if (asn1_type.srs_ul_cfg_ded_present) {
cfg->ul_cfg.srs.dedicated_enabled = asn1_type.srs_ul_cfg_ded.type() == asn1::rrc::setup_e::setup;
if (cfg->ul_cfg.srs.dedicated_enabled) {
cfg->ul_cfg.srs.configured = cfg->ul_cfg.srs.dedicated_enabled and cfg->ul_cfg.srs.common_enabled;
cfg->ul_cfg.srs.I_srs = asn1_type.srs_ul_cfg_ded.setup().srs_cfg_idx;
cfg->ul_cfg.srs.B = asn1_type.srs_ul_cfg_ded.setup().srs_bw;
cfg->ul_cfg.srs.b_hop = asn1_type.srs_ul_cfg_ded.setup().srs_hop_bw;
cfg->ul_cfg.srs.n_rrc = asn1_type.srs_ul_cfg_ded.setup().freq_domain_position;
cfg->ul_cfg.srs.k_tc = asn1_type.srs_ul_cfg_ded.setup().tx_comb;
cfg->ul_cfg.srs.n_srs = asn1_type.srs_ul_cfg_ded.setup().cyclic_shift;
}
}
if (asn1_type.ant_info_r10.is_present()) {
// Parse Release 10
asn1::rrc::ant_info_ded_r10_s::tx_mode_r10_e_::options tx_mode =
asn1_type.ant_info_r10->explicit_value_r10().tx_mode_r10.value;
if ((srslte_tm_t)tx_mode < SRSLTE_TMINV) {
cfg->dl_cfg.tm = (srslte_tm_t)tx_mode;
} else {
fprintf(stderr,
"Transmission mode (R10) %s is not supported\n",
asn1_type.ant_info_r10->explicit_value_r10().tx_mode_r10.to_string().c_str());
}
} else if (asn1_type.ant_info_present &&
asn1_type.ant_info.type() == asn1::rrc::phys_cfg_ded_s::ant_info_c_::types::explicit_value) {
// Parse Release 8
asn1::rrc::ant_info_ded_s::tx_mode_e_::options tx_mode = asn1_type.ant_info.explicit_value().tx_mode.value;
if ((srslte_tm_t)tx_mode < SRSLTE_TMINV) {
cfg->dl_cfg.tm = (srslte_tm_t)tx_mode;
} else {
fprintf(stderr,
"Transmission mode (R8) %s is not supported\n",
asn1_type.ant_info.explicit_value().tx_mode.to_string().c_str());
}
}
if (asn1_type.sched_request_cfg_present) {
if (asn1_type.sched_request_cfg_present and asn1_type.sched_request_cfg.type() == asn1::rrc::setup_e::setup) {
cfg->ul_cfg.pucch.I_sr = asn1_type.sched_request_cfg.setup().sr_cfg_idx;
cfg->ul_cfg.pucch.n_pucch_sr = asn1_type.sched_request_cfg.setup().sr_pucch_res_idx;
cfg->ul_cfg.pucch.sr_configured = true;
} else {
cfg->ul_cfg.pucch.I_sr = 0;
cfg->ul_cfg.pucch.n_pucch_sr = 0;
cfg->ul_cfg.pucch.sr_configured = false;
}
}
if (asn1_type.pdsch_cfg_ded_present) {
// Configure PDSCH
if (asn1_type.pdsch_cfg_ded_present && cfg->dl_cfg.pdsch.p_b < 4) {
cfg->dl_cfg.pdsch.p_a = asn1_type.pdsch_cfg_ded.p_a.to_number();
cfg->dl_cfg.pdsch.power_scale = true;
} else {
cfg->dl_cfg.pdsch.power_scale = false;
}
}
}
void set_phy_cfg_t_common_prach(phy_cfg_t* cfg, const asn1::rrc::prach_cfg_info_s* asn1_type, uint32_t root_seq_idx)
{
if (asn1_type) {
cfg->prach_cfg.config_idx = asn1_type->prach_cfg_idx;
cfg->prach_cfg.zero_corr_zone = asn1_type->zero_correlation_zone_cfg;
cfg->prach_cfg.freq_offset = asn1_type->prach_freq_offset;
cfg->prach_cfg.hs_flag = asn1_type->high_speed_flag;
}
cfg->prach_cfg.root_seq_idx = root_seq_idx;
}
void set_phy_cfg_t_common_pdsch(phy_cfg_t* cfg, const asn1::rrc::pdsch_cfg_common_s& asn1_type)
{
cfg->dl_cfg.pdsch.rs_power = (float)asn1_type.ref_sig_pwr;
cfg->dl_cfg.pdsch.p_b = asn1_type.p_b;
}
void set_phy_cfg_t_enable_64qam(phy_cfg_t* cfg, const bool enabled)
{
cfg->ul_cfg.pusch.enable_64qam = enabled;
}
void set_phy_cfg_t_common_pusch(phy_cfg_t* cfg, const asn1::rrc::pusch_cfg_common_s& asn1_type)
{
/* PUSCH DMRS signal configuration */
bzero(&cfg->ul_cfg.dmrs, sizeof(srslte_refsignal_dmrs_pusch_cfg_t));
cfg->ul_cfg.dmrs.group_hopping_en = asn1_type.ul_ref_sigs_pusch.group_hop_enabled;
cfg->ul_cfg.dmrs.sequence_hopping_en = asn1_type.ul_ref_sigs_pusch.seq_hop_enabled;
cfg->ul_cfg.dmrs.cyclic_shift = asn1_type.ul_ref_sigs_pusch.cyclic_shift;
cfg->ul_cfg.dmrs.delta_ss = asn1_type.ul_ref_sigs_pusch.group_assign_pusch;
/* PUSCH Hopping configuration */
bzero(&cfg->ul_cfg.hopping, sizeof(srslte_pusch_hopping_cfg_t));
cfg->ul_cfg.hopping.n_sb = asn1_type.pusch_cfg_basic.n_sb;
cfg->ul_cfg.hopping.hopping_offset = asn1_type.pusch_cfg_basic.pusch_hop_offset;
cfg->ul_cfg.hopping.hop_mode =
asn1_type.pusch_cfg_basic.hop_mode.value ==
asn1::rrc::pusch_cfg_common_s::pusch_cfg_basic_s_::hop_mode_e_::intra_and_inter_sub_frame
? cfg->ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTRA_SF
: cfg->ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTER_SF;
}
void set_phy_cfg_t_common_pucch(phy_cfg_t* cfg, const asn1::rrc::pucch_cfg_common_s& asn1_type)
{
/* PUCCH configuration */
cfg->ul_cfg.pucch.delta_pucch_shift = asn1_type.delta_pucch_shift.to_number();
cfg->ul_cfg.pucch.N_cs = asn1_type.n_cs_an;
cfg->ul_cfg.pucch.n_rb_2 = asn1_type.n_rb_cqi;
cfg->ul_cfg.pucch.N_pucch_1 = asn1_type.n1_pucch_an;
}
void set_phy_cfg_t_common_srs(phy_cfg_t* cfg, const asn1::rrc::srs_ul_cfg_common_c& asn1_type)
{
cfg->ul_cfg.srs.common_enabled = asn1_type.type() == asn1::rrc::setup_e::setup;
if (cfg->ul_cfg.srs.common_enabled) {
cfg->ul_cfg.srs.simul_ack = asn1_type.setup().ack_nack_srs_simul_tx;
cfg->ul_cfg.srs.bw_cfg = asn1_type.setup().srs_bw_cfg.to_number();
cfg->ul_cfg.srs.subframe_config = asn1_type.setup().srs_sf_cfg.to_number();
}
}
void set_phy_cfg_t_common_pwr_ctrl(phy_cfg_t* cfg, const asn1::rrc::ul_pwr_ctrl_common_s& asn1_type)
{
cfg->ul_cfg.power_ctrl.p0_nominal_pusch = asn1_type.p0_nominal_pusch;
cfg->ul_cfg.power_ctrl.alpha = asn1_type.alpha.to_number();
cfg->ul_cfg.power_ctrl.p0_nominal_pucch = asn1_type.p0_nominal_pucch;
cfg->ul_cfg.power_ctrl.delta_f_pucch[0] = asn1_type.delta_flist_pucch.delta_f_pucch_format1.to_number();
cfg->ul_cfg.power_ctrl.delta_f_pucch[1] = asn1_type.delta_flist_pucch.delta_f_pucch_format1b.to_number();
cfg->ul_cfg.power_ctrl.delta_f_pucch[2] = asn1_type.delta_flist_pucch.delta_f_pucch_format2.to_number();
cfg->ul_cfg.power_ctrl.delta_f_pucch[3] = asn1_type.delta_flist_pucch.delta_f_pucch_format2a.to_number();
cfg->ul_cfg.power_ctrl.delta_f_pucch[4] = asn1_type.delta_flist_pucch.delta_f_pucch_format2b.to_number();
cfg->ul_cfg.power_ctrl.delta_preamble_msg3 = asn1_type.delta_preamb_msg3;
}
void set_phy_cfg_t_scell_config(phy_cfg_t* cfg, const asn1::rrc::scell_to_add_mod_r10_s* asn1_type)
{
if (asn1_type->rr_cfg_common_scell_r10_present) {
// Enable always CSI request extra bit
cfg->dl_cfg.dci.multiple_csi_request_enabled = true;
auto* rr_cfg_common_scell_r10 = &asn1_type->rr_cfg_common_scell_r10;
if (rr_cfg_common_scell_r10->ul_cfg_r10_present) {
auto* ul_cfg_r10 = &rr_cfg_common_scell_r10->ul_cfg_r10;
// Parse Power control
auto* ul_pwr_ctrl_common_scell_r10 = &ul_cfg_r10->ul_pwr_ctrl_common_scell_r10;
bzero(&cfg->ul_cfg.power_ctrl, sizeof(srslte_ue_ul_powerctrl_t));
cfg->ul_cfg.power_ctrl.p0_nominal_pusch = ul_pwr_ctrl_common_scell_r10->p0_nominal_pusch_r10;
cfg->ul_cfg.power_ctrl.alpha = ul_pwr_ctrl_common_scell_r10->alpha_r10.to_number();
// Parse SRS
cfg->ul_cfg.srs.common_enabled = ul_cfg_r10->srs_ul_cfg_common_r10.type() == asn1::rrc::setup_e::setup;
if (cfg->ul_cfg.srs.common_enabled) {
auto* srs_ul_cfg_common = &ul_cfg_r10->srs_ul_cfg_common_r10.setup();
cfg->ul_cfg.srs.simul_ack = srs_ul_cfg_common->ack_nack_srs_simul_tx;
cfg->ul_cfg.srs.bw_cfg = srs_ul_cfg_common->srs_bw_cfg.to_number();
cfg->ul_cfg.srs.subframe_config = srs_ul_cfg_common->srs_sf_cfg.to_number();
}
// Parse PUSCH
auto* pusch_cfg_common = &ul_cfg_r10->pusch_cfg_common_r10;
bzero(&cfg->ul_cfg.hopping, sizeof(srslte_pusch_hopping_cfg_t));
cfg->ul_cfg.hopping.n_sb = pusch_cfg_common->pusch_cfg_basic.n_sb;
cfg->ul_cfg.hopping.hop_mode =
pusch_cfg_common->pusch_cfg_basic.hop_mode.value ==
asn1::rrc::pusch_cfg_common_s::pusch_cfg_basic_s_::hop_mode_e_::intra_and_inter_sub_frame
? cfg->ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTRA_SF
: cfg->ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTER_SF;
cfg->ul_cfg.hopping.hopping_offset = pusch_cfg_common->pusch_cfg_basic.pusch_hop_offset;
cfg->ul_cfg.pusch.enable_64qam = pusch_cfg_common->pusch_cfg_basic.enable64_qam;
}
}
if (asn1_type->rr_cfg_ded_scell_r10_present) {
auto* rr_cfg_ded_scell_r10 = &asn1_type->rr_cfg_ded_scell_r10;
if (rr_cfg_ded_scell_r10->phys_cfg_ded_scell_r10_present) {
auto* phys_cfg_ded_scell_r10 = &rr_cfg_ded_scell_r10->phys_cfg_ded_scell_r10;
// Parse nonUL Configuration
if (phys_cfg_ded_scell_r10->non_ul_cfg_r10_present) {
auto* non_ul_cfg = &phys_cfg_ded_scell_r10->non_ul_cfg_r10;
// Parse Transmission mode
if (non_ul_cfg->ant_info_r10_present) {
asn1::rrc::ant_info_ded_r10_s::tx_mode_r10_e_::options tx_mode = non_ul_cfg->ant_info_r10.tx_mode_r10.value;
if ((srslte_tm_t)tx_mode < SRSLTE_TMINV) {
cfg->dl_cfg.tm = (srslte_tm_t)tx_mode;
} else {
fprintf(stderr,
"Transmission mode (R10) %s is not supported\n",
non_ul_cfg->ant_info_r10.tx_mode_r10.to_string().c_str());
}
}
// Parse Cross carrier scheduling
if (non_ul_cfg->cross_carrier_sched_cfg_r10_present) {
typedef asn1::rrc::cross_carrier_sched_cfg_r10_s::sched_cell_info_r10_c_ sched_info_t;
typedef sched_info_t::types cross_carrier_type_e;
auto* sched_info = &non_ul_cfg->cross_carrier_sched_cfg_r10.sched_cell_info_r10;
cross_carrier_type_e cross_carrier_type = sched_info->type();
if (cross_carrier_type == cross_carrier_type_e::own_r10) {
cfg->dl_cfg.dci.cif_present = sched_info->own_r10().cif_presence_r10;
} else {
cfg->dl_cfg.dci.cif_present = false; // This CC does not have Carrier Indicator Field
// ue_cfg->dl_cfg.blablabla = sched_info->other_r10().pdsch_start_r10;
// ue_cfg->dl_cfg.blablabla = sched_info->other_r10().sched_cell_id_r10;
}
}
// Parse pdsch config dedicated
if (non_ul_cfg->pdsch_cfg_ded_r10_present) {
cfg->dl_cfg.pdsch.p_b = asn1_type->rr_cfg_common_scell_r10.non_ul_cfg_r10.pdsch_cfg_common_r10.p_b;
cfg->dl_cfg.pdsch.p_a = non_ul_cfg->pdsch_cfg_ded_r10.p_a.to_number();
cfg->dl_cfg.pdsch.power_scale = true;
}
}
// Parse UL Configuration
if (phys_cfg_ded_scell_r10->ul_cfg_r10_present) {
auto* ul_cfg_r10 = &phys_cfg_ded_scell_r10->ul_cfg_r10;
// Parse CQI param
if (ul_cfg_r10->cqi_report_cfg_scell_r10_present) {
auto* cqi_report_cfg = &ul_cfg_r10->cqi_report_cfg_scell_r10;
// Aperiodic report
if (cqi_report_cfg->cqi_report_mode_aperiodic_r10_present) {
cfg->dl_cfg.cqi_report.aperiodic_configured = true;
cfg->dl_cfg.cqi_report.aperiodic_mode = make_aperiodic_mode(cqi_report_cfg->cqi_report_mode_aperiodic_r10);
}
// Periodic report
if (cqi_report_cfg->cqi_report_periodic_scell_r10_present) {
if (cqi_report_cfg->cqi_report_periodic_scell_r10.type() == asn1::rrc::setup_e::setup) {
typedef asn1::rrc::cqi_report_periodic_r10_c::setup_s_ cqi_cfg_t;
cqi_cfg_t cqi_cfg = cqi_report_cfg->cqi_report_periodic_scell_r10.setup();
cfg->dl_cfg.cqi_report.periodic_configured = true;
cfg->dl_cfg.cqi_report.pmi_idx = cqi_cfg.cqi_pmi_cfg_idx;
cfg->dl_cfg.cqi_report.format_is_subband =
cqi_cfg.cqi_format_ind_periodic_r10.type().value ==
cqi_cfg_t::cqi_format_ind_periodic_r10_c_::types::subband_cqi_r10;
if (cfg->dl_cfg.cqi_report.format_is_subband) {
cfg->dl_cfg.cqi_report.subband_size = cqi_cfg.cqi_format_ind_periodic_r10.subband_cqi_r10().k;
}
if (cqi_cfg.ri_cfg_idx_present) {
cfg->dl_cfg.cqi_report.ri_idx = cqi_cfg.ri_cfg_idx;
cfg->dl_cfg.cqi_report.ri_idx_present = true;
} else {
cfg->dl_cfg.cqi_report.ri_idx_present = false;
}
} else {
// Release, disable periodic reporting
cfg->dl_cfg.cqi_report.periodic_configured = false;
}
}
}
// Sounding reference signals Dedicated
if (ul_cfg_r10->srs_ul_cfg_ded_r10_present) {
cfg->ul_cfg.srs.dedicated_enabled = ul_cfg_r10->srs_ul_cfg_ded_r10.type() == asn1::rrc::setup_e::setup;
if (cfg->ul_cfg.srs.dedicated_enabled) {
auto* srs_ul_cfg_ded_r10 = &ul_cfg_r10->srs_ul_cfg_ded_r10.setup();
cfg->ul_cfg.srs.configured = cfg->ul_cfg.srs.dedicated_enabled and cfg->ul_cfg.srs.common_enabled;
cfg->ul_cfg.srs.I_srs = srs_ul_cfg_ded_r10->srs_cfg_idx;
cfg->ul_cfg.srs.B = srs_ul_cfg_ded_r10->srs_bw;
cfg->ul_cfg.srs.b_hop = srs_ul_cfg_ded_r10->srs_hop_bw;
cfg->ul_cfg.srs.n_rrc = srs_ul_cfg_ded_r10->freq_domain_position;
cfg->ul_cfg.srs.k_tc = srs_ul_cfg_ded_r10->tx_comb;
cfg->ul_cfg.srs.n_srs = srs_ul_cfg_ded_r10->cyclic_shift;
}
}
}
if (phys_cfg_ded_scell_r10->cqi_report_cfg_scell_v1250.is_present()) {
// Enable/disable PDSCH 256QAM
auto cqi_report_cfg_scell = phys_cfg_ded_scell_r10->cqi_report_cfg_scell_v1250.get();
cfg->dl_cfg.pdsch.use_tbs_index_alt = cqi_report_cfg_scell->alt_cqi_table_r12_present;
} else {
// Assume there is no PDSCH 256QAM
cfg->dl_cfg.pdsch.use_tbs_index_alt = false;
}
}
}
}
} // namespace srslte

32
lib/src/phy/ue/ue_dl.c
View File

@ -479,7 +479,7 @@ static int dci_blind_search(srslte_ue_dl_t* q,
int srslte_ue_dl_find_ul_dci(srslte_ue_dl_t* q,
srslte_dl_sf_cfg_t* sf,
srslte_ue_dl_cfg_t* cfg,
srslte_ue_dl_cfg_t* dl_cfg,
uint16_t rnti,
srslte_dci_ul_t dci_ul[SRSLTE_MAX_DCI_MSG])
{
@ -497,7 +497,7 @@ int srslte_ue_dl_find_ul_dci(srslte_ue_dl_t* q,
uint32_t sf_idx = sf->tti % 10;
uint32_t cfi = sf->cfi;
set_mi_value(q, sf, cfg);
set_mi_value(q, sf, dl_cfg);
// Configure and run DCI blind search
dci_blind_search_t search_space;
@ -512,12 +512,12 @@ int srslte_ue_dl_find_ul_dci(srslte_ue_dl_t* q,
current_ss->format = SRSLTE_DCI_FORMAT0;
INFO("Searching UL C-RNTI in %d ue locations\n", search_space.nof_locations);
nof_msg = dci_blind_search(q, sf, rnti, current_ss, &cfg->dci_cfg, dci_msg);
nof_msg = dci_blind_search(q, sf, rnti, current_ss, &dl_cfg->cfg.dci, dci_msg);
}
// Unpack DCI messages
for (uint32_t i = 0; i < nof_msg; i++) {
if (srslte_dci_msg_unpack_pusch(&q->cell, sf, &cfg->dci_cfg, &dci_msg[i], &dci_ul[i])) {
if (srslte_dci_msg_unpack_pusch(&q->cell, sf, &dl_cfg->cfg.dci, &dci_msg[i], &dci_ul[i])) {
ERROR("Unpacking UL DCI\n");
return SRSLTE_ERROR;
}
@ -533,13 +533,13 @@ int srslte_ue_dl_find_ul_dci(srslte_ue_dl_t* q,
// Blind search for SI/P/RA-RNTI
static int find_dl_dci_type_siprarnti(srslte_ue_dl_t* q,
srslte_dl_sf_cfg_t* sf,
srslte_ue_dl_cfg_t* cfg,
srslte_ue_dl_cfg_t* dl_cfg,
uint16_t rnti,
srslte_dci_msg_t dci_msg[SRSLTE_MAX_DCI_MSG])
{
int ret = 0;
srslte_dci_cfg_t* dci_cfg = &cfg->dci_cfg;
srslte_dci_cfg_t* dci_cfg = &dl_cfg->cfg.dci;
// Configure and run DCI blind search
dci_blind_search_t search_space;
@ -575,7 +575,7 @@ static int find_dl_dci_type_crnti(srslte_ue_dl_t* q,
uint32_t sf_idx = sf->tti % 10;
uint32_t cfi = sf->cfi;
srslte_dci_cfg_t* dci_cfg = &cfg->dci_cfg;
srslte_dci_cfg_t* dci_cfg = &cfg->cfg.dci;
// Search UE-specific search space
if (q->pregen_rnti == rnti) {
@ -619,25 +619,25 @@ static int find_dl_dci_type_crnti(srslte_ue_dl_t* q,
int srslte_ue_dl_find_dl_dci(srslte_ue_dl_t* q,
srslte_dl_sf_cfg_t* sf,
srslte_ue_dl_cfg_t* cfg,
srslte_ue_dl_cfg_t* dl_cfg,
uint16_t rnti,
srslte_dci_dl_t dci_dl[SRSLTE_MAX_DCI_MSG])
{
set_mi_value(q, sf, cfg);
set_mi_value(q, sf, dl_cfg);
srslte_dci_msg_t dci_msg[SRSLTE_MAX_DCI_MSG];
int nof_msg = 0;
if (rnti == SRSLTE_SIRNTI || rnti == SRSLTE_PRNTI || SRSLTE_RNTI_ISRAR(rnti)) {
nof_msg = find_dl_dci_type_siprarnti(q, sf, cfg, rnti, dci_msg);
nof_msg = find_dl_dci_type_siprarnti(q, sf, dl_cfg, rnti, dci_msg);
} else {
nof_msg = find_dl_dci_type_crnti(q, sf, cfg, rnti, dci_msg);
nof_msg = find_dl_dci_type_crnti(q, sf, dl_cfg, rnti, dci_msg);
}
// Unpack DCI messages
for (uint32_t i = 0; i < nof_msg; i++) {
if (srslte_dci_msg_unpack_pdsch(&q->cell, sf, &cfg->dci_cfg, &dci_msg[i], &dci_dl[i])) {
if (srslte_dci_msg_unpack_pdsch(&q->cell, sf, &dl_cfg->cfg.dci, &dci_msg[i], &dci_dl[i])) {
ERROR("Unpacking DL DCI\n");
return SRSLTE_ERROR;
}
@ -651,7 +651,7 @@ int srslte_ue_dl_dci_to_pdsch_grant(srslte_ue_dl_t* q,
srslte_dci_dl_t* dci,
srslte_pdsch_grant_t* grant)
{
return srslte_ra_dl_dci_to_grant(&q->cell, sf, cfg->cfg.tm, cfg->pdsch_use_tbs_index_alt, dci, grant);
return srslte_ra_dl_dci_to_grant(&q->cell, sf, cfg->cfg.tm, cfg->cfg.pdsch.use_tbs_index_alt, dci, grant);
}
int srslte_ue_dl_decode_pdsch(srslte_ue_dl_t* q,
@ -1032,7 +1032,7 @@ void srslte_ue_dl_gen_ack(srslte_ue_dl_t* q,
uci_data->cfg.ack.tdd_ack_M = ack_value->M;
// ACK/NACK bundling or multiplexing and M=1
if (ack_info->tdd_ack_bundle || ack_value->M == 1) {
if (!ack_info->tdd_ack_multiplex || ack_value->M == 1) {
for (uint32_t tb = 0; tb < nof_tb; tb++) {
bool first_in_bundle = true;
for (uint32_t k = 0; k < ack_value->M; k++) {
@ -1090,10 +1090,10 @@ void srslte_ue_dl_gen_ack(srslte_ue_dl_t* q,
ack_info->V_dai_ul++; // Table 7.3-x
uci_data->cfg.ack.tdd_is_bundling = ack_info->tdd_ack_bundle;
uci_data->cfg.ack.tdd_is_multiplex = ack_info->tdd_ack_multiplex;
// Bundling or multiplexing and M=1
if (ack_info->tdd_ack_bundle || ack_info->cc[0].M == 1) {
if (!ack_info->tdd_ack_multiplex || ack_info->cc[0].M == 1) {
// 1 or 2 ACK/NACK bits
uci_data->cfg.ack.nof_acks = nof_tb;

2
lib/src/phy/ue/ue_ul.c
View File

@ -826,7 +826,7 @@ get_npucch(srslte_pucch_cfg_t* cfg, srslte_uci_cfg_t* uci_cfg, srslte_uci_value_
if (cell->frame_type == SRSLTE_FDD) {
n_pucch_res = uci_cfg->ack.ncce[0] + cfg->N_pucch_1;
} else {
if (uci_cfg->ack.tdd_is_bundling || uci_cfg->ack.tdd_ack_M == 1) {
if (!uci_cfg->ack.tdd_is_multiplex || uci_cfg->ack.tdd_ack_M == 1) {
n_pucch_res = n_pucch_i_tdd(
uci_cfg->ack.ncce[0], cfg->N_pucch_1, cell->nof_prb, uci_cfg->ack.tdd_ack_M, uci_cfg->ack.tdd_ack_m);
} else {

4
lib/test/phy/phy_dl_test.c
View File

@ -593,8 +593,8 @@ int main(int argc, char **argv) {
ue_dl_cfg.chest_cfg.cfo_estimate_enable = false;
ue_dl_cfg.chest_cfg.cfo_estimate_sf_mask = false;
ue_dl_cfg.chest_cfg.sync_error_enable = false;
ue_dl_cfg.dci_cfg = dci_cfg;
ue_dl_cfg.pdsch_use_tbs_index_alt = enable_256qam;
ue_dl_cfg.cfg.dci = dci_cfg;
ue_dl_cfg.cfg.pdsch.use_tbs_index_alt = enable_256qam;
srslte_pdsch_res_t pdsch_res[SRSLTE_MAX_CODEWORDS];
for (int i = 0; i < SRSLTE_MAX_CODEWORDS; i++) {

8
srsue/hdr/phy/cc_worker.h
View File

@ -23,6 +23,7 @@
#define SRSLTE_CC_WORKER_H
#include "phy_common.h"
#include "srslte/interfaces/ue_interfaces.h"
#include "srslte/srslte.h"
namespace srsue {
@ -45,8 +46,7 @@ public:
float get_ref_cfo();
void set_tdd_config(srslte_tdd_config_t config);
void set_pcell_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg);
void set_scell_config(asn1::rrc::scell_to_add_mod_r10_s* phy_cfg);
void set_config(srslte::phy_cfg_t& phy_cfg);
void set_crnti(uint16_t rnti);
void enable_pregen_signals(bool enabled);
@ -68,7 +68,6 @@ private:
uint32_t pid,
bool ul_grant_available,
mac_interface_phy_lte::mac_grant_ul_t* mac_grant);
void fill_dci_cfg(srslte_dci_cfg_t* cfg, bool rel10 = false);
// Cross-carried grants scheduled from PCell
void set_dl_pending_grant(uint32_t cc_idx, srslte_dci_dl_t* dl_dci);
@ -96,9 +95,6 @@ private:
void set_uci_aperiodic_cqi(srslte_uci_data_t* uci_data);
void set_uci_ack(srslte_uci_data_t* uci_data, bool is_grant_available, uint32_t dai_ul, bool is_pusch_available);
uint32_t get_wideband_cqi();
srslte_cqi_report_mode_t aperiodic_mode(asn1::rrc::cqi_report_mode_aperiodic_e mode);
void parse_antenna_info(asn1::rrc::phys_cfg_ded_s* dedicated);
void parse_pucch_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg);
/* Common objects */
phy_common* phy;

13
srsue/hdr/phy/phy.h
View File

@ -107,9 +107,10 @@ public:
void set_rar_grant(uint8_t grant_payload[SRSLTE_RAR_GRANT_LEN], uint16_t rnti) final;
/* Get/Set PHY parameters interface from RRC */
void set_config(phy_cfg_t* phy_cfg) final;
void set_config_scell(asn1::rrc::scell_to_add_mod_r10_s* scell_config) final;
void set_config_tdd(asn1::rrc::tdd_cfg_s* tdd) final;
void set_config(srslte::phy_cfg_t& config, uint32_t cc_idx, uint32_t earfcn, srslte_cell_t* cell_info) final;
void set_config_tdd(srslte_tdd_config_t& tdd_config) final;
#warning "Remove ASN1 from MBSFN"
void set_config_mbsfn_sib2(asn1::rrc::sib_type2_s* sib2) final;
void set_config_mbsfn_sib13(asn1::rrc::sib_type13_r9_s* sib13) final;
void set_config_mbsfn_mcch(asn1::rrc::mcch_msg_s* mcch) final;
@ -142,7 +143,7 @@ private:
const static int SF_RECV_THREAD_PRIO = 1;
const static int WORKERS_THREAD_PRIO = 2;
srslte::radio_interface_phy* radio = nullptr;
srslte::radio_interface_phy* radio = nullptr;
std::vector<std::unique_ptr<srslte::log_filter> > log_vec;
srslte::logger* logger = nullptr;
@ -160,8 +161,8 @@ private:
srslte_prach_cfg_t prach_cfg = {};
srslte_tdd_config_t tdd_config = {};
phy_interface_rrc_lte::phy_cfg_t config = {};
phy_args_t args = {};
srslte::phy_cfg_t config = {};
phy_args_t args = {};
/* Current time advance */
uint32_t n_ta = 0;

4
srsue/hdr/phy/phy_common.h
View File

@ -87,10 +87,6 @@ public:
} scell_cfg_t;
scell_cfg_t scell_cfg[SRSLTE_MAX_CARRIERS];
bool multiple_csi_request_enabled; /* True means cross scheduling enabled */
bool cif_enabled; /* True means cross scheduling enabled */
bool srs_request_enabled;
// Save last TBS for uplink (mcs >= 28)
srslte_ra_tb_t last_ul_tb[SRSLTE_MAX_HARQ_PROC][SRSLTE_MAX_CARRIERS];

35
srsue/hdr/phy/sf_worker.h
View File

@ -56,8 +56,7 @@ public:
void set_cfo(const uint32_t& cc_idx, float cfo);
void set_tdd_config(srslte_tdd_config_t config);
void set_pcell_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg);
void set_scell_config(uint32_t cc_idx, asn1::rrc::scell_to_add_mod_r10_s* scell_config);
void set_config(uint32_t cc_idx, srslte::phy_cfg_t& phy_cfg);
void set_crnti(uint16_t rnti);
void enable_pregen_signals(bool enabled);
@ -80,34 +79,36 @@ public:
private:
/* Inherited from thread_pool::worker. Function called every subframe to run the DL/UL processing */
void work_imp();
void reset_();
void update_measurements();
void reset_uci(srslte_uci_data_t* uci_data);
std::vector<cc_worker*> cc_workers;
phy_common* phy;
srslte::log* log_h;
srslte::log* log_phy_lib_h;
chest_feedback_itf* chest_loop;
phy_common* phy = nullptr;
;
srslte::log* log_h = nullptr;
;
srslte::log* log_phy_lib_h = nullptr;
;
chest_feedback_itf* chest_loop = nullptr;
pthread_mutex_t mutex;
srslte_cell_t cell;
srslte_tdd_config_t tdd_config;
srslte_cell_t cell = {};
srslte_tdd_config_t tdd_config = {};
bool cell_initiated;
bool cell_initiated = false;
cf_t* prach_ptr;
float prach_power;
cf_t* prach_ptr = nullptr;
float prach_power = 0;
uint32_t tti;
srslte_timestamp_t tx_time[SRSLTE_MAX_RADIOS];
uint32_t tx_sem_id;
int next_offset[SRSLTE_MAX_RADIOS];
uint32_t tti = 0;
uint32_t tx_sem_id = 0;
srslte_timestamp_t tx_time[SRSLTE_MAX_RADIOS] = {};
int next_offset[SRSLTE_MAX_RADIOS] = {};
uint32_t rssi_read_cnt;
uint32_t rssi_read_cnt = 0;
};
} // namespace srsue

22
srsue/hdr/stack/mac/proc_bsr.h
View File

@ -33,6 +33,24 @@
namespace srsue {
// BSR interface for MUX
class bsr_interface_mux
{
public:
typedef enum { LONG_BSR, SHORT_BSR, TRUNC_BSR } bsr_format_t;
typedef struct {
bsr_format_t format;
uint32_t buff_size[4];
} bsr_t;
/* MUX calls BSR to check if it can fit a BSR into PDU */
virtual bool need_to_send_bsr_on_ul_grant(uint32_t grant_size, bsr_t* bsr) = 0;
/* MUX calls BSR to let it generate a padding BSR if there is space in PDU */
virtual bool generate_padding_bsr(uint32_t nof_padding_bytes, bsr_t* bsr) = 0;
};
class bsr_proc : public srslte::timer_callback, public bsr_interface_mux
{
public:
@ -40,7 +58,7 @@ public:
void init(rlc_interface_mac* rlc, srslte::log* log_h, srslte::timers* timers_db);
void step(uint32_t tti);
void reset();
void set_config(mac_interface_rrc::bsr_cfg_t& bsr_cfg);
void set_config(srslte::bsr_cfg_t& bsr_cfg);
void setup_lcid(uint32_t lcid, uint32_t lcg, uint32_t priority);
void timer_expired(uint32_t timer_id);
@ -60,7 +78,7 @@ private:
srslte::log *log_h;
rlc_interface_mac *rlc;
mac_interface_rrc::bsr_cfg_t bsr_cfg;
srslte::bsr_cfg_t bsr_cfg;
bool initiated;

4
srsue/hdr/stack/mac/proc_phr.h
View File

@ -38,7 +38,7 @@ class phr_proc : public srslte::timer_callback
public:
phr_proc();
void init(phy_interface_mac_lte* phy_h, srslte::log* log_h_, srslte::timers* timers_db_);
void set_config(mac_interface_rrc::phr_cfg_t& cfg);
void set_config(srslte::phr_cfg_t& cfg);
void step(uint32_t tti);
void reset();
@ -55,7 +55,7 @@ private:
srslte::log* log_h;
phy_interface_mac_lte* phy_h;
srslte::timers* timers_db;
mac_interface_rrc::phr_cfg_t phr_cfg;
srslte::phr_cfg_t phr_cfg;
bool initiated;
int last_pathloss_db;
bool phr_is_triggered;

4
srsue/hdr/stack/mac/proc_ra.h
View File

@ -79,7 +79,7 @@ public:
void reset();
void set_config(mac_interface_rrc::rach_cfg_t& rach_cfg);
void set_config(srslte::rach_cfg_t& rach_cfg);
void start_pdcch_order();
void start_mac_order(uint32_t msg_len_bits = 56, bool is_ho = false);
@ -118,7 +118,7 @@ private:
srslte::rar_pdu rar_pdu_msg;
// Random Access parameters provided by higher layers defined in 5.1.1
mac_interface_rrc::rach_cfg_t rach_cfg, new_cfg;
srslte::rach_cfg_t rach_cfg, new_cfg;
int delta_preamble_db;
uint32_t maskIndex;

4
srsue/hdr/stack/mac/proc_sr.h
View File

@ -37,7 +37,7 @@ public:
sr_proc();
void init(phy_interface_mac_lte* phy_h, rrc_interface_mac* rrc, srslte::log* log_h);
void step(uint32_t tti);
void set_config(mac_interface_rrc::sr_cfg_t& cfg);
void set_config(srslte::sr_cfg_t& cfg);
void reset();
void start();
bool need_random_access();
@ -48,7 +48,7 @@ private:
int sr_counter;
bool is_pending_sr;
mac_interface_rrc::sr_cfg_t sr_cfg;
srslte::sr_cfg_t sr_cfg;
rrc_interface_mac *rrc;
phy_interface_mac_lte* phy_h;

4
srsue/hdr/stack/mac/ul_harq.h
View File

@ -48,7 +48,7 @@ public:
void reset();
void reset_ndi();
void set_config(mac_interface_rrc_common::ul_harq_cfg_t& harq_cfg);
void set_config(srslte::ul_harq_cfg_t& harq_cfg);
void start_pcap(srslte::mac_pcap* pcap_);
@ -112,7 +112,7 @@ private:
srslte::log* log_h;
mac_interface_rrc_common::ue_rnti_t* rntis;
mac_interface_rrc_common::ul_harq_cfg_t harq_cfg;
srslte::ul_harq_cfg_t harq_cfg;
float average_retx;
uint64_t nof_pkts;

7
srsue/hdr/stack/rrc/rrc.h
View File

@ -390,8 +390,8 @@ private:
uint16_t ho_src_rnti = 0;
cell_t ho_src_cell = {};
phy_interface_rrc_lte::phy_cfg_t current_phy_cfg, previous_phy_cfg = {};
mac_interface_rrc::mac_cfg_t current_mac_cfg, previous_mac_cfg = {};
srslte::phy_cfg_t current_phy_cfg, previous_phy_cfg = {};
srslte::mac_cfg_t current_mac_cfg, previous_mac_cfg = {};
bool pending_mob_reconf = false;
asn1::rrc::rrc_conn_recfg_s mob_reconf = {};
@ -668,9 +668,9 @@ private:
bool apply_rr_config_dedicated(asn1::rrc::rr_cfg_ded_s* cnfg);
void apply_scell_config(asn1::rrc::rrc_conn_recfg_r8_ies_s* reconfig_r8);
void apply_phy_config_dedicated(const asn1::rrc::phys_cfg_ded_s& phy_cnfg);
void apply_phy_scell_config(const asn1::rrc::scell_to_add_mod_r10_s* scell_config);
void apply_mac_config_dedicated_default();
void apply_mac_config_dedicated_explicit(asn1::rrc::mac_main_cfg_s mac_cfg);
void handle_sib1();
void handle_sib2();
@ -689,7 +689,6 @@ private:
// Helpers for setting default values
void set_phy_default_pucch_srs();
void set_phy_config_common_default();
void set_phy_config_dedicated_default();
void set_phy_default();
void set_mac_default();

488
srsue/src/phy/cc_worker.cc
View File

@ -21,7 +21,6 @@
#include "srslte/srslte.h"
#include "srsue/hdr/phy/cc_worker.h"
#include "srslte/interfaces/ue_interfaces.h"
#define Error(fmt, ...) \
if (SRSLTE_DEBUG_ENABLED) \
@ -111,6 +110,9 @@ cc_worker::cc_worker(uint32_t cc_idx, uint32_t max_prb, srsue::phy_common* phy,
chest_default_cfg = ue_dl_cfg.chest_cfg;
// Set default PHY params
reset();
if (phy->args->pdsch_8bit_decoder) {
ue_dl.pdsch.llr_is_8bit = true;
ue_dl.pdsch.dl_sch.llr_is_8bit = true;
@ -137,21 +139,9 @@ void cc_worker::reset()
bzero(&dl_metrics, sizeof(dl_metrics_t));
bzero(&ul_metrics, sizeof(ul_metrics_t));
phy_interface_rrc_lte::phy_cfg_t empty_cfg = {};
// defaults
empty_cfg.common.pucch_cnfg.delta_pucch_shift.value = pucch_cfg_common_s::delta_pucch_shift_opts::ds1;
empty_cfg.common.ul_pwr_ctrl.alpha.value = alpha_r12_opts::al0;
empty_cfg.common.ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format1.value =
delta_flist_pucch_s::delta_f_pucch_format1_opts::delta_f0;
empty_cfg.common.ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format1b.value =
delta_flist_pucch_s::delta_f_pucch_format1b_opts::delta_f1;
empty_cfg.common.ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format2.value =
delta_flist_pucch_s::delta_f_pucch_format2_opts::delta_f0;
empty_cfg.common.ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format2a.value =
delta_flist_pucch_s::delta_f_pucch_format2a_opts::delta_f0;
empty_cfg.common.ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format2b.value =
delta_flist_pucch_s::delta_f_pucch_format2b_opts::delta_f0;
set_pcell_config(&empty_cfg);
// constructor sets defaults
srslte::phy_cfg_t empty_cfg;
set_config(empty_cfg);
}
bool cc_worker::set_cell(srslte_cell_t cell)
@ -227,16 +217,6 @@ void cc_worker::enable_pregen_signals(bool enabled)
this->pregen_enabled = enabled;
}
void cc_worker::fill_dci_cfg(srslte_dci_cfg_t* cfg, bool rel10)
{
bzero(cfg, sizeof(srslte_dci_cfg_t));
if (rel10 && phy->cif_enabled) {
cfg->cif_enabled = phy->cif_enabled;
}
cfg->multiple_csi_request_enabled = phy->multiple_csi_request_enabled;
cfg->srs_request_enabled = phy->srs_request_enabled;
}
void cc_worker::set_dl_pending_grant(uint32_t cc_idx, srslte_dci_dl_t* dl_dci)
{
if (!pending_dl_grant[cc_idx].enable) {
@ -303,7 +283,7 @@ bool cc_worker::work_dl_regular()
}
/* Look for DL and UL dci(s) if this is PCell, or no cross-carrier scheduling is enabled */
if ((cc_idx == 0) || (!phy->cif_enabled)) {
if ((cc_idx == 0) || (!ue_dl_cfg.cfg.dci.cif_present)) {
found_dl_grant = decode_pdcch_dl() > 0;
decode_pdcch_ul();
}
@ -428,9 +408,9 @@ int cc_worker::decode_pdcch_dl()
if (dl_rnti) {
/* Blind search first without cross scheduling then with it if enabled */
for (int i = 0; i < (phy->cif_enabled ? 2 : 1) && !nof_grants; i++) {
fill_dci_cfg(&ue_dl_cfg.dci_cfg, i > 0);
for (int i = 0; i < (ue_dl_cfg.cfg.dci.cif_present ? 2 : 1) && !nof_grants; i++) {
Debug("PDCCH looking for rnti=0x%x\n", dl_rnti);
ue_dl_cfg.cfg.dci.cif_enabled = i > 0;
nof_grants = srslte_ue_dl_find_dl_dci(&ue_dl, &sf_cfg_dl, &ue_dl_cfg, dl_rnti, dci);
if (nof_grants < 0) {
Error("Looking for DL grants\n");
@ -787,8 +767,8 @@ int cc_worker::decode_pdcch_ul()
if (ul_rnti) {
/* Blind search first without cross scheduling then with it if enabled */
for (int i = 0; i < (phy->cif_enabled ? 2 : 1) && !nof_grants; i++) {
fill_dci_cfg(&ue_dl_cfg.dci_cfg, i > 0);
for (int i = 0; i < (ue_dl_cfg.cfg.dci.cif_present ? 2 : 1) && !nof_grants; i++) {
ue_dl_cfg.cfg.dci.cif_enabled = i > 0;
nof_grants = srslte_ue_dl_find_ul_dci(&ue_dl, &sf_cfg_dl, &ue_dl_cfg, ul_rnti, dci);
if (nof_grants < 0) {
Error("Looking for UL grants\n");
@ -939,7 +919,7 @@ void cc_worker::set_uci_ack(srslte_uci_data_t* uci_data,
ack_info.is_grant_available = is_grant_available;
ack_info.is_pusch_available = is_pusch_available;
ack_info.V_dai_ul = V_dai_ul;
ack_info.tdd_ack_bundle = ue_ul_cfg.ul_cfg.pucch.tdd_ack_bundle;
ack_info.tdd_ack_multiplex = ue_ul_cfg.ul_cfg.pucch.tdd_ack_multiplex;
ack_info.simul_cqi_ack = ue_ul_cfg.ul_cfg.pucch.simul_cqi_ack;
ack_info.ack_nack_feedback_mode = ue_ul_cfg.ul_cfg.pucch.ack_nack_feedback_mode;
ack_info.nof_cc = nof_configured_carriers;
@ -955,290 +935,15 @@ void cc_worker::set_uci_ack(srslte_uci_data_t* uci_data,
*
*/
srslte_cqi_report_mode_t cc_worker::aperiodic_mode(cqi_report_mode_aperiodic_e mode)
{
switch (mode) {
case cqi_report_mode_aperiodic_e::rm12:
return SRSLTE_CQI_MODE_12;
case cqi_report_mode_aperiodic_e::rm20:
return SRSLTE_CQI_MODE_20;
case cqi_report_mode_aperiodic_e::rm22:
return SRSLTE_CQI_MODE_22;
case cqi_report_mode_aperiodic_e::rm30:
return SRSLTE_CQI_MODE_30;
case cqi_report_mode_aperiodic_e::rm31:
return SRSLTE_CQI_MODE_31;
case cqi_report_mode_aperiodic_e::rm10_v1310:
case cqi_report_mode_aperiodic_e::rm11_v1310:
case cqi_report_mode_aperiodic_e::rm32_v1250:
fprintf(stderr, "Aperiodic mode %s not handled\n", mode.to_string().c_str());
default:
return SRSLTE_CQI_MODE_NA;
}
}
void cc_worker::parse_antenna_info(phys_cfg_ded_s* dedicated)
{
if (dedicated->ant_info_r10.is_present()) {
// Parse Release 10
ant_info_ded_r10_s::tx_mode_r10_e_::options tx_mode =
dedicated->ant_info_r10->explicit_value_r10().tx_mode_r10.value;
if ((srslte_tm_t)tx_mode < SRSLTE_TMINV) {
ue_dl_cfg.cfg.tm = (srslte_tm_t)tx_mode;
} else {
fprintf(stderr,
"Transmission mode (R10) %s is not supported\n",
dedicated->ant_info_r10->explicit_value_r10().tx_mode_r10.to_string().c_str());
}
} else if (dedicated->ant_info_present &&
dedicated->ant_info.type() == phys_cfg_ded_s::ant_info_c_::types::explicit_value) {
// Parse Release 8
ant_info_ded_s::tx_mode_e_::options tx_mode = dedicated->ant_info.explicit_value().tx_mode.value;
if ((srslte_tm_t)tx_mode < SRSLTE_TMINV) {
ue_dl_cfg.cfg.tm = (srslte_tm_t)tx_mode;
} else {
fprintf(stderr,
"Transmission mode (R8) %s is not supported\n",
dedicated->ant_info.explicit_value().tx_mode.to_string().c_str());
}
} else {
if (cell.nof_ports == 1) {
// No antenna info provided
ue_dl_cfg.cfg.tm = SRSLTE_TM1;
} else {
// No antenna info provided
ue_dl_cfg.cfg.tm = SRSLTE_TM2;
}
}
}
void cc_worker::parse_pucch_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg)
{
phy_interface_rrc_lte::phy_cfg_common_t* common = &phy_cfg->common;
phys_cfg_ded_s* dedicated = &phy_cfg->dedicated;
/* PUCCH configuration */
bzero(&ue_ul_cfg.ul_cfg.pucch, sizeof(srslte_pucch_cfg_t));
ue_ul_cfg.ul_cfg.pucch.delta_pucch_shift = common->pucch_cnfg.delta_pucch_shift.to_number();
ue_ul_cfg.ul_cfg.pucch.N_cs = common->pucch_cnfg.n_cs_an;
ue_ul_cfg.ul_cfg.pucch.n_rb_2 = common->pucch_cnfg.n_rb_cqi;
/* PUCCH Scheduling configuration */
ue_ul_cfg.ul_cfg.pucch.n_pucch_1[0] = 0; // TODO: n_pucch_1 for SPS
ue_ul_cfg.ul_cfg.pucch.n_pucch_1[1] = 0;
ue_ul_cfg.ul_cfg.pucch.n_pucch_1[2] = 0;
ue_ul_cfg.ul_cfg.pucch.n_pucch_1[3] = 0;
ue_ul_cfg.ul_cfg.pucch.N_pucch_1 = common->pucch_cnfg.n1_pucch_an;
if (dedicated->cqi_report_cfg.cqi_report_periodic_present and
dedicated->cqi_report_cfg.cqi_report_periodic.type().value == setup_e::setup) {
ue_ul_cfg.ul_cfg.pucch.n_pucch_2 = dedicated->cqi_report_cfg.cqi_report_periodic.setup().cqi_pucch_res_idx;
ue_ul_cfg.ul_cfg.pucch.simul_cqi_ack = dedicated->cqi_report_cfg.cqi_report_periodic.setup().simul_ack_nack_and_cqi;
} else {
// FIXME: put is_pucch_configured flag here?
ue_ul_cfg.ul_cfg.pucch.n_pucch_2 = 0;
ue_ul_cfg.ul_cfg.pucch.simul_cqi_ack = false;
}
/* SR configuration */
if (dedicated->sched_request_cfg_present and dedicated->sched_request_cfg.type() == setup_e::setup) {
ue_ul_cfg.ul_cfg.pucch.I_sr = dedicated->sched_request_cfg.setup().sr_cfg_idx;
ue_ul_cfg.ul_cfg.pucch.n_pucch_sr = dedicated->sched_request_cfg.setup().sr_pucch_res_idx;
ue_ul_cfg.ul_cfg.pucch.sr_configured = true;
} else {
ue_ul_cfg.ul_cfg.pucch.I_sr = 0;
ue_ul_cfg.ul_cfg.pucch.n_pucch_sr = 0;
ue_ul_cfg.ul_cfg.pucch.sr_configured = false;
}
if (dedicated->pucch_cfg_ded.tdd_ack_nack_feedback_mode_present) {
ue_ul_cfg.ul_cfg.pucch.tdd_ack_bundle =
dedicated->pucch_cfg_ded.tdd_ack_nack_feedback_mode == pucch_cfg_ded_s::tdd_ack_nack_feedback_mode_e_::bundling;
} else {
ue_ul_cfg.ul_cfg.pucch.tdd_ack_bundle = false;
}
if (dedicated->pucch_cfg_ded_v1020.is_present()) {
pucch_cfg_ded_v1020_s* pucch_cfg_ded = dedicated->pucch_cfg_ded_v1020.get();
if (pucch_cfg_ded->pucch_format_r10_present) {
typedef pucch_cfg_ded_v1020_s::pucch_format_r10_c_ pucch_format_r10_t;
pucch_format_r10_t* pucch_format_r10 = &pucch_cfg_ded->pucch_format_r10;
if (pucch_format_r10->type() == pucch_format_r10_t::types::format3_r10) {
// Select feedback mode
ue_ul_cfg.ul_cfg.pucch.ack_nack_feedback_mode = SRSLTE_PUCCH_ACK_NACK_FEEDBACK_MODE_PUCCH3;
pucch_format3_conf_r13_s* format3_r13 = &pucch_format_r10->format3_r10();
for (uint32_t n = 0; n < SRSLTE_MIN(format3_r13->n3_pucch_an_list_r13.size(), SRSLTE_PUCCH_SIZE_AN_CS); n++) {
ue_ul_cfg.ul_cfg.pucch.n3_pucch_an_list[n] = format3_r13->n3_pucch_an_list_r13[n];
}
if (format3_r13->two_ant_port_activ_pucch_format3_r13_present) {
if (format3_r13->two_ant_port_activ_pucch_format3_r13.type() == setup_e::setup) {
// TODO: UL MIMO Configure PUCCH two antenna port
} else {
// TODO: UL MIMO Disable two antenna port
}
}
} else if (pucch_format_r10->type() == pucch_cfg_ded_v1020_s::pucch_format_r10_c_::types::ch_sel_r10) {
typedef pucch_format_r10_t::ch_sel_r10_s_ ch_sel_r10_t;
ch_sel_r10_t* ch_sel_r10 = &pucch_format_r10->ch_sel_r10();
if (ch_sel_r10->n1_pucch_an_cs_r10_present) {
typedef ch_sel_r10_t::n1_pucch_an_cs_r10_c_ n1_pucch_an_cs_r10_t;
n1_pucch_an_cs_r10_t* n1_pucch_an_cs_r10 = &ch_sel_r10->n1_pucch_an_cs_r10;
if (n1_pucch_an_cs_r10->type() == setup_e::setup) {
// Select feedback mode
ue_ul_cfg.ul_cfg.pucch.ack_nack_feedback_mode = SRSLTE_PUCCH_ACK_NACK_FEEDBACK_MODE_CS;
typedef n1_pucch_an_cs_r10_t::setup_s_::n1_pucch_an_cs_list_r10_l_ n1_pucch_an_cs_list_r10_t;
n1_pucch_an_cs_list_r10_t n1_pucch_an_cs_list =
ch_sel_r10->n1_pucch_an_cs_r10.setup().n1_pucch_an_cs_list_r10;
for (uint32_t i = 0; i < SRSLTE_MIN(n1_pucch_an_cs_list.size(), SRSLTE_PUCCH_NOF_AN_CS); i++) {
n1_pucch_an_cs_r10_l n1_pucch_an_cs = n1_pucch_an_cs_list[i];
for (uint32_t j = 0; j < SRSLTE_PUCCH_SIZE_AN_CS; j++) {
ue_ul_cfg.ul_cfg.pucch.n1_pucch_an_cs[j][i] = n1_pucch_an_cs[j];
}
}
} else {
ue_ul_cfg.ul_cfg.pucch.ack_nack_feedback_mode = SRSLTE_PUCCH_ACK_NACK_FEEDBACK_MODE_NORMAL;
}
}
} else {
// Do nothing
}
}
}
}
/* Translates RRC structs into PHY structs
*/
void cc_worker::set_pcell_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg)
void cc_worker::set_config(srslte::phy_cfg_t& phy_cfg)
{
phy_interface_rrc_lte::phy_cfg_common_t* common = &phy_cfg->common;
phys_cfg_ded_s* dedicated = &phy_cfg->dedicated;
// Configure PDSCH
if (dedicated->pdsch_cfg_ded_present && common->pdsch_cnfg.p_b < 4) {
ue_dl_cfg.cfg.pdsch.p_a = dedicated->pdsch_cfg_ded.p_a.to_number();
ue_dl_cfg.cfg.pdsch.p_b = common->pdsch_cnfg.p_b;
ue_dl_cfg.cfg.pdsch.power_scale = true;
} else {
ue_dl_cfg.cfg.pdsch.power_scale = false;
}
ue_dl_cfg.cfg.pdsch.rs_power = (float)common->pdsch_cnfg.ref_sig_pwr;
parse_antenna_info(dedicated);
// Configure PUSCH
ue_ul_cfg.ul_cfg.pusch.enable_64qam =
phy_cfg->common.pusch_cnfg.pusch_cfg_basic.enable64_qam && phy_cfg->common.rrc_enable_64qam;
/* PUSCH DMRS signal configuration */
bzero(&ue_ul_cfg.ul_cfg.dmrs, sizeof(srslte_refsignal_dmrs_pusch_cfg_t));
ue_ul_cfg.ul_cfg.dmrs.group_hopping_en = common->pusch_cnfg.ul_ref_sigs_pusch.group_hop_enabled;
ue_ul_cfg.ul_cfg.dmrs.sequence_hopping_en = common->pusch_cnfg.ul_ref_sigs_pusch.seq_hop_enabled;
ue_ul_cfg.ul_cfg.dmrs.cyclic_shift = common->pusch_cnfg.ul_ref_sigs_pusch.cyclic_shift;
ue_ul_cfg.ul_cfg.dmrs.delta_ss = common->pusch_cnfg.ul_ref_sigs_pusch.group_assign_pusch;
/* PUSCH Hopping configuration */
bzero(&ue_ul_cfg.ul_cfg.hopping, sizeof(srslte_pusch_hopping_cfg_t));
ue_ul_cfg.ul_cfg.hopping.n_sb = common->pusch_cnfg.pusch_cfg_basic.n_sb;
ue_ul_cfg.ul_cfg.hopping.hop_mode =
common->pusch_cnfg.pusch_cfg_basic.hop_mode.value ==
pusch_cfg_common_s::pusch_cfg_basic_s_::hop_mode_e_::intra_and_inter_sub_frame
? ue_ul_cfg.ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTRA_SF
: ue_ul_cfg.ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTER_SF;
ue_ul_cfg.ul_cfg.hopping.hopping_offset = common->pusch_cnfg.pusch_cfg_basic.pusch_hop_offset;
/* PUSCH UCI configuration */
bzero(&ue_ul_cfg.ul_cfg.pusch.uci_offset, sizeof(srslte_uci_offset_cfg_t));
ue_ul_cfg.ul_cfg.pusch.uci_offset.I_offset_ack = dedicated->pusch_cfg_ded.beta_offset_ack_idx;
ue_ul_cfg.ul_cfg.pusch.uci_offset.I_offset_cqi = dedicated->pusch_cfg_ded.beta_offset_cqi_idx;
ue_ul_cfg.ul_cfg.pusch.uci_offset.I_offset_ri = dedicated->pusch_cfg_ded.beta_offset_ri_idx;
parse_pucch_config(phy_cfg);
/* SRS Configuration */
bzero(&ue_ul_cfg.ul_cfg.srs, sizeof(srslte_refsignal_srs_cfg_t));
ue_ul_cfg.ul_cfg.srs.configured = dedicated->srs_ul_cfg_ded_present and
dedicated->srs_ul_cfg_ded.type() == setup_e::setup and
common->srs_ul_cnfg.type() == setup_e::setup;
if (ue_ul_cfg.ul_cfg.srs.configured) {
ue_ul_cfg.ul_cfg.srs.I_srs = dedicated->srs_ul_cfg_ded.setup().srs_cfg_idx;
ue_ul_cfg.ul_cfg.srs.B = dedicated->srs_ul_cfg_ded.setup().srs_bw;
ue_ul_cfg.ul_cfg.srs.b_hop = dedicated->srs_ul_cfg_ded.setup().srs_hop_bw;
ue_ul_cfg.ul_cfg.srs.n_rrc = dedicated->srs_ul_cfg_ded.setup().freq_domain_position;
ue_ul_cfg.ul_cfg.srs.k_tc = dedicated->srs_ul_cfg_ded.setup().tx_comb;
ue_ul_cfg.ul_cfg.srs.n_srs = dedicated->srs_ul_cfg_ded.setup().cyclic_shift;
ue_ul_cfg.ul_cfg.srs.simul_ack = common->srs_ul_cnfg.setup().ack_nack_srs_simul_tx;
ue_ul_cfg.ul_cfg.srs.bw_cfg = common->srs_ul_cnfg.setup().srs_bw_cfg.to_number();
ue_ul_cfg.ul_cfg.srs.subframe_config = common->srs_ul_cnfg.setup().srs_sf_cfg.to_number();
}
/* UL power control configuration */
bzero(&ue_ul_cfg.ul_cfg.power_ctrl, sizeof(srslte_ue_ul_powerctrl_t));
ue_ul_cfg.ul_cfg.power_ctrl.p0_nominal_pusch = common->ul_pwr_ctrl.p0_nominal_pusch;
ue_ul_cfg.ul_cfg.power_ctrl.alpha = common->ul_pwr_ctrl.alpha.to_number();
ue_ul_cfg.ul_cfg.power_ctrl.p0_nominal_pucch = common->ul_pwr_ctrl.p0_nominal_pucch;
ue_ul_cfg.ul_cfg.power_ctrl.delta_f_pucch[0] =
common->ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format1.to_number();
ue_ul_cfg.ul_cfg.power_ctrl.delta_f_pucch[1] =
common->ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format1b.to_number();
ue_ul_cfg.ul_cfg.power_ctrl.delta_f_pucch[2] =
common->ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format2.to_number();
ue_ul_cfg.ul_cfg.power_ctrl.delta_f_pucch[3] =
common->ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format2a.to_number();
ue_ul_cfg.ul_cfg.power_ctrl.delta_f_pucch[4] =
common->ul_pwr_ctrl.delta_flist_pucch.delta_f_pucch_format2b.to_number();
ue_ul_cfg.ul_cfg.power_ctrl.delta_preamble_msg3 = common->ul_pwr_ctrl.delta_preamb_msg3;
ue_ul_cfg.ul_cfg.power_ctrl.p0_ue_pusch = dedicated->ul_pwr_ctrl_ded.p0_ue_pusch;
ue_ul_cfg.ul_cfg.power_ctrl.delta_mcs_based =
dedicated->ul_pwr_ctrl_ded.delta_mcs_enabled == ul_pwr_ctrl_ded_s::delta_mcs_enabled_e_::en0;
ue_ul_cfg.ul_cfg.power_ctrl.acc_enabled = dedicated->ul_pwr_ctrl_ded.accumulation_enabled;
ue_ul_cfg.ul_cfg.power_ctrl.p0_ue_pucch = dedicated->ul_pwr_ctrl_ded.p0_ue_pucch;
ue_ul_cfg.ul_cfg.power_ctrl.p_srs_offset = dedicated->ul_pwr_ctrl_ded.p_srs_offset;
/* CQI configuration */
bzero(&ue_dl_cfg.cfg.cqi_report, sizeof(srslte_cqi_report_cfg_t));
ue_dl_cfg.cfg.cqi_report.periodic_configured = dedicated->cqi_report_cfg.cqi_report_periodic_present and
dedicated->cqi_report_cfg.cqi_report_periodic.type() == setup_e::setup;
if (ue_dl_cfg.cfg.cqi_report.periodic_configured) {
ue_dl_cfg.cfg.cqi_report.pmi_idx = dedicated->cqi_report_cfg.cqi_report_periodic.setup().cqi_pmi_cfg_idx;
ue_dl_cfg.cfg.cqi_report.format_is_subband =
dedicated->cqi_report_cfg.cqi_report_periodic.setup().cqi_format_ind_periodic.type().value ==
cqi_report_periodic_c::setup_s_::cqi_format_ind_periodic_c_::types::subband_cqi;
if (ue_dl_cfg.cfg.cqi_report.format_is_subband) {
ue_dl_cfg.cfg.cqi_report.subband_size =
dedicated->cqi_report_cfg.cqi_report_periodic.setup().cqi_format_ind_periodic.subband_cqi().k;
}
if (dedicated->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx_present) {
if (cell.nof_ports == 1) {
log_h->warning("Received Rank Indication report configuration but only 1 antenna is available\n");
}
ue_dl_cfg.cfg.cqi_report.ri_idx = dedicated->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx;
ue_dl_cfg.cfg.cqi_report.ri_idx_present = true;
} else {
ue_dl_cfg.cfg.cqi_report.ri_idx_present = false;
}
}
if (dedicated->cqi_report_cfg.cqi_report_mode_aperiodic_present) {
ue_dl_cfg.cfg.cqi_report.aperiodic_configured = true;
ue_dl_cfg.cfg.cqi_report.aperiodic_mode = aperiodic_mode(dedicated->cqi_report_cfg.cqi_report_mode_aperiodic);
}
if (dedicated->cqi_report_cfg_pcell_v1250.is_present()) {
auto cqi_report_cfg_pcell_v1250 = dedicated->cqi_report_cfg_pcell_v1250.get();
if (cqi_report_cfg_pcell_v1250->alt_cqi_table_r12_present) {
ue_dl_cfg.pdsch_use_tbs_index_alt = true;
}
} else {
ue_dl_cfg.pdsch_use_tbs_index_alt = false;
}
// Save configuration
ue_dl_cfg.cfg = phy_cfg.dl_cfg;
ue_ul_cfg.ul_cfg = phy_cfg.ul_cfg;
// Update signals
if (pregen_enabled) {
Info("Pre-generating UL signals...\n");
srslte_ue_ul_pregen_signals(&ue_ul, &ue_ul_cfg);
@ -1246,165 +951,6 @@ void cc_worker::set_pcell_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg)
}
}
void cc_worker::set_scell_config(asn1::rrc::scell_to_add_mod_r10_s* phy_cfg)
{
if (phy_cfg->rr_cfg_common_scell_r10_present) {
rr_cfg_common_scell_r10_s* rr_cfg_common_scell_r10 = &phy_cfg->rr_cfg_common_scell_r10;
if (rr_cfg_common_scell_r10->ul_cfg_r10_present) {
typedef rr_cfg_common_scell_r10_s::ul_cfg_r10_s_ ul_cfg_r10_t;
ul_cfg_r10_t* ul_cfg_r10 = &rr_cfg_common_scell_r10->ul_cfg_r10;
// Parse Power control
ul_pwr_ctrl_common_scell_r10_s* ul_pwr_ctrl_common_scell_r10 = &ul_cfg_r10->ul_pwr_ctrl_common_scell_r10;
bzero(&ue_ul_cfg.ul_cfg.power_ctrl, sizeof(srslte_ue_ul_powerctrl_t));
ue_ul_cfg.ul_cfg.power_ctrl.p0_nominal_pusch = ul_pwr_ctrl_common_scell_r10->p0_nominal_pusch_r10;
ue_ul_cfg.ul_cfg.power_ctrl.alpha = ul_pwr_ctrl_common_scell_r10->alpha_r10.to_number();
// Parse SRS
typedef srs_ul_cfg_common_c::setup_s_ srs_ul_cfg_common_t;
if (ul_cfg_r10->srs_ul_cfg_common_r10.type() == setup_e::setup) {
srs_ul_cfg_common_t* srs_ul_cfg_common = &ul_cfg_r10->srs_ul_cfg_common_r10.setup();
ue_ul_cfg.ul_cfg.srs.configured = true;
ue_ul_cfg.ul_cfg.srs.simul_ack = srs_ul_cfg_common->ack_nack_srs_simul_tx;
ue_ul_cfg.ul_cfg.srs.bw_cfg = srs_ul_cfg_common->srs_bw_cfg.to_number();
ue_ul_cfg.ul_cfg.srs.subframe_config = srs_ul_cfg_common->srs_sf_cfg.to_number();
} else {
ue_ul_cfg.ul_cfg.srs.configured = false;
}
// Parse PUSCH
pusch_cfg_common_s* pusch_cfg_common = &ul_cfg_r10->pusch_cfg_common_r10;
bzero(&ue_ul_cfg.ul_cfg.hopping, sizeof(srslte_pusch_hopping_cfg_t));
ue_ul_cfg.ul_cfg.hopping.n_sb = pusch_cfg_common->pusch_cfg_basic.n_sb;
ue_ul_cfg.ul_cfg.hopping.hop_mode =
pusch_cfg_common->pusch_cfg_basic.hop_mode.value ==
pusch_cfg_common_s::pusch_cfg_basic_s_::hop_mode_e_::intra_and_inter_sub_frame
? ue_ul_cfg.ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTRA_SF
: ue_ul_cfg.ul_cfg.hopping.SRSLTE_PUSCH_HOP_MODE_INTER_SF;
ue_ul_cfg.ul_cfg.hopping.hopping_offset = pusch_cfg_common->pusch_cfg_basic.pusch_hop_offset;
ue_ul_cfg.ul_cfg.pusch.enable_64qam = pusch_cfg_common->pusch_cfg_basic.enable64_qam;
}
}
if (phy_cfg->rr_cfg_ded_scell_r10_present) {
rr_cfg_ded_scell_r10_s* rr_cfg_ded_scell_r10 = &phy_cfg->rr_cfg_ded_scell_r10;
if (rr_cfg_ded_scell_r10->phys_cfg_ded_scell_r10_present) {
phys_cfg_ded_scell_r10_s* phys_cfg_ded_scell_r10 = &rr_cfg_ded_scell_r10->phys_cfg_ded_scell_r10;
// Parse nonUL Configuration
if (phys_cfg_ded_scell_r10->non_ul_cfg_r10_present) {
typedef phys_cfg_ded_scell_r10_s::non_ul_cfg_r10_s_ non_ul_cfg_t;
non_ul_cfg_t* non_ul_cfg = &phys_cfg_ded_scell_r10->non_ul_cfg_r10;
// Parse Transmission mode
if (non_ul_cfg->ant_info_r10_present) {
ant_info_ded_r10_s::tx_mode_r10_e_::options tx_mode = non_ul_cfg->ant_info_r10.tx_mode_r10.value;
if ((srslte_tm_t)tx_mode < SRSLTE_TMINV) {
ue_dl_cfg.cfg.tm = (srslte_tm_t)tx_mode;
} else {
fprintf(stderr,
"Transmission mode (R10) %s is not supported\n",
non_ul_cfg->ant_info_r10.tx_mode_r10.to_string().c_str());
}
}
// Parse Cross carrier scheduling
if (non_ul_cfg->cross_carrier_sched_cfg_r10_present) {
typedef cross_carrier_sched_cfg_r10_s::sched_cell_info_r10_c_ sched_info_t;
typedef sched_info_t::types cross_carrier_type_e;
sched_info_t* sched_info = &non_ul_cfg->cross_carrier_sched_cfg_r10.sched_cell_info_r10;
cross_carrier_type_e cross_carrier_type = sched_info->type();
if (cross_carrier_type == cross_carrier_type_e::own_r10) {
ue_dl_cfg.dci_cfg.cif_enabled = sched_info->own_r10().cif_presence_r10;
} else {
ue_dl_cfg.dci_cfg.cif_enabled = false; // This CC does not have Carrier Indicator Field
// ue_dl_cfg.blablabla = sched_info->other_r10().pdsch_start_r10;
// ue_dl_cfg.blablabla = sched_info->other_r10().sched_cell_id_r10;
}
}
// Parse pdsch config dedicated
if (non_ul_cfg->pdsch_cfg_ded_r10_present) {
ue_dl_cfg.cfg.pdsch.p_b = phy_cfg->rr_cfg_common_scell_r10.non_ul_cfg_r10.pdsch_cfg_common_r10.p_b;
ue_dl_cfg.cfg.pdsch.p_a = non_ul_cfg->pdsch_cfg_ded_r10.p_a.to_number();
ue_dl_cfg.cfg.pdsch.power_scale = true;
}
}
// Parse UL Configuration
if (phys_cfg_ded_scell_r10->ul_cfg_r10_present) {
typedef phys_cfg_ded_scell_r10_s::ul_cfg_r10_s_ ul_cfg_t;
ul_cfg_t* ul_cfg = &phys_cfg_ded_scell_r10->ul_cfg_r10;
// Parse CQI param
if (ul_cfg->cqi_report_cfg_scell_r10_present) {
cqi_report_cfg_scell_r10_s* cqi_report_cfg = &ul_cfg->cqi_report_cfg_scell_r10;
// Aperiodic report
if (cqi_report_cfg->cqi_report_mode_aperiodic_r10_present) {
ue_dl_cfg.cfg.cqi_report.aperiodic_configured = true;
ue_dl_cfg.cfg.cqi_report.aperiodic_mode = aperiodic_mode(cqi_report_cfg->cqi_report_mode_aperiodic_r10);
}
// Periodic report
if (cqi_report_cfg->cqi_report_periodic_scell_r10_present) {
if (cqi_report_cfg->cqi_report_periodic_scell_r10.type() == setup_e::setup) {
typedef cqi_report_periodic_r10_c::setup_s_ cqi_cfg_t;
cqi_cfg_t cqi_cfg = cqi_report_cfg->cqi_report_periodic_scell_r10.setup();
ue_dl_cfg.cfg.cqi_report.periodic_configured = true;
ue_dl_cfg.cfg.cqi_report.pmi_idx = cqi_cfg.cqi_pmi_cfg_idx;
ue_dl_cfg.cfg.cqi_report.format_is_subband =
cqi_cfg.cqi_format_ind_periodic_r10.type().value ==
cqi_cfg_t::cqi_format_ind_periodic_r10_c_::types::subband_cqi_r10;
if (ue_dl_cfg.cfg.cqi_report.format_is_subband) {
ue_dl_cfg.cfg.cqi_report.subband_size = cqi_cfg.cqi_format_ind_periodic_r10.subband_cqi_r10().k;
}
if (cqi_cfg.ri_cfg_idx_present) {
ue_dl_cfg.cfg.cqi_report.ri_idx = cqi_cfg.ri_cfg_idx;
ue_dl_cfg.cfg.cqi_report.ri_idx_present = true;
} else {
ue_dl_cfg.cfg.cqi_report.ri_idx_present = false;
}
} else {
// Release, disable periodic reporting
ue_dl_cfg.cfg.cqi_report.periodic_configured = false;
}
}
}
if (ul_cfg->srs_ul_cfg_ded_r10_present) {
// Sounding reference signals
if (ul_cfg->srs_ul_cfg_ded_r10.type() == setup_e::setup) {
srs_ul_cfg_ded_c::setup_s_* srs_ul_cfg_ded_r10 = &ul_cfg->srs_ul_cfg_ded_r10.setup();
ue_ul_cfg.ul_cfg.srs.I_srs = srs_ul_cfg_ded_r10->srs_cfg_idx;
ue_ul_cfg.ul_cfg.srs.B = srs_ul_cfg_ded_r10->srs_bw;
ue_ul_cfg.ul_cfg.srs.b_hop = srs_ul_cfg_ded_r10->srs_hop_bw;
ue_ul_cfg.ul_cfg.srs.n_rrc = srs_ul_cfg_ded_r10->freq_domain_position;
ue_ul_cfg.ul_cfg.srs.k_tc = srs_ul_cfg_ded_r10->tx_comb;
ue_ul_cfg.ul_cfg.srs.n_srs = srs_ul_cfg_ded_r10->cyclic_shift;
} else {
ue_ul_cfg.ul_cfg.srs.configured = false;
}
}
}
if (phys_cfg_ded_scell_r10->cqi_report_cfg_scell_v1250.is_present()) {
auto cqi_report_cfg_scell = phys_cfg_ded_scell_r10->cqi_report_cfg_scell_v1250.get();
// Enable/disable PDSCH 256QAM
ue_dl_cfg.pdsch_use_tbs_index_alt = cqi_report_cfg_scell->alt_cqi_table_r12_present;
} else {
// Assume there is no PDSCH 256QAM
ue_dl_cfg.pdsch_use_tbs_index_alt = false;
}
}
}
}
int cc_worker::read_ce_abs(float* ce_abs, uint32_t tx_antenna, uint32_t rx_antenna)
{
uint32_t i = 0;

97
srsue/src/phy/phy.cc
View File

@ -421,94 +421,63 @@ void phy::enable_pregen_signals(bool enable)
}
}
void phy::set_config(phy_interface_rrc_lte::phy_cfg_t* phy_cfg)
void phy::set_config(srslte::phy_cfg_t& config, uint32_t cc_idx, uint32_t earfcn, srslte_cell_t* cell_info)
{
if (is_initiated()) {
for (uint32_t i = 0; i < nof_workers; i++) {
workers[i]->set_pcell_config(phy_cfg);
}
if (!is_initiated()) {
fprintf(stderr, "Error calling set_config(): PHY not initialized\n");
return;
}
// Save PRACH configuration
prach_cfg.config_idx = phy_cfg->common.prach_cnfg.prach_cfg_info.prach_cfg_idx;
prach_cfg.root_seq_idx = phy_cfg->common.prach_cnfg.root_seq_idx;
prach_cfg.zero_corr_zone = phy_cfg->common.prach_cnfg.prach_cfg_info.zero_correlation_zone_cfg;
prach_cfg.freq_offset = phy_cfg->common.prach_cnfg.prach_cfg_info.prach_freq_offset;
prach_cfg.hs_flag = phy_cfg->common.prach_cnfg.prach_cfg_info.high_speed_flag;
}
void phy::set_config_scell(asn1::rrc::scell_to_add_mod_r10_s* scell_config)
{
// Enable CSI request extra bit
common.multiple_csi_request_enabled = true;
uint32_t cc_idx = scell_config->s_cell_idx_r10;
// Component carrier index zero should be reserved for PCell
if (cc_idx != 0 && cc_idx < args.nof_carriers) {
if (cc_idx < args.nof_carriers) {
carrier_map_t* m = &args.carrier_map[cc_idx];
srslte_cell_t cell = {};
uint32_t earfcn = 0;
// Initialise default parameters from primary cell
sfsync.get_current_cell(&cell, &earfcn);
// Parse identification
if (scell_config->cell_identif_r10_present) {
cell.id = scell_config->cell_identif_r10.pci_r10;
earfcn = scell_config->cell_identif_r10.dl_carrier_freq_r10;
}
// Parse radio resource
if (scell_config->rr_cfg_common_scell_r10_present) {
rr_cfg_common_scell_r10_s* rr_cfg = &scell_config->rr_cfg_common_scell_r10;
cell.frame_type = (rr_cfg->tdd_cfg_v1130.is_present()) ? SRSLTE_TDD : SRSLTE_FDD;
cell.nof_prb = rr_cfg->non_ul_cfg_r10.dl_bw_r10.to_number();
cell.nof_ports = rr_cfg->non_ul_cfg_r10.ant_info_common_r10.ant_ports_count.to_number();
cell.phich_length = (srslte_phich_length_t)rr_cfg->non_ul_cfg_r10.phich_cfg_r10.phich_dur.value;
cell.phich_resources = (srslte_phich_r_t)rr_cfg->non_ul_cfg_r10.phich_cfg_r10.phich_res.value;
}
// Send configuration to workers
for (uint32_t i = 0; i < nof_workers; i++) {
workers[i]->set_cell(cc_idx, cell);
workers[i]->set_scell_config(cc_idx, scell_config);
if (cell_info) {
workers[i]->set_cell(cc_idx, *cell_info);
}
workers[i]->set_config(cc_idx, config);
}
// If SCell does not share synchronism with PCell ...
if (m->radio_idx > 0) {
scell_sync.at(m->radio_idx - 1)->set_scell_cell(cc_idx, &cell, earfcn);
if (cc_idx == 0) {
prach_cfg = config.prach_cfg;
} else {
// Change frequency only if the earfcn was modified
if (common.scell_cfg[cc_idx].earfcn != earfcn) {
float dl_freq = srslte_band_fd(earfcn) * 1e6f;
float ul_freq = srslte_band_fu(srslte_band_ul_earfcn(earfcn)) * 1e6f;
for (uint32_t p = 0; p < common.args->nof_rx_ant; p++) {
radio->set_rx_freq(m->radio_idx, m->channel_idx + p, dl_freq);
radio->set_tx_freq(m->radio_idx, m->channel_idx + p, ul_freq);
// If SCell does not share synchronism with PCell ...
if (m->radio_idx > 0) {
scell_sync.at(m->radio_idx - 1)->set_scell_cell(cc_idx, cell_info, earfcn);
} else {
// Change frequency only if the earfcn was modified
if (common.scell_cfg[cc_idx].earfcn != earfcn) {
float dl_freq = srslte_band_fd(earfcn) * 1e6f;
float ul_freq = srslte_band_fu(srslte_band_ul_earfcn(earfcn)) * 1e6f;
for (uint32_t p = 0; p < common.args->nof_rx_ant; p++) {
radio->set_rx_freq(m->radio_idx, m->channel_idx + p, dl_freq);
radio->set_tx_freq(m->radio_idx, m->channel_idx + p, ul_freq);
}
}
}
// Store SCell earfcn and pci
common.scell_cfg[cc_idx].earfcn = earfcn;
common.scell_cfg[cc_idx].pci = cell_info->id;
common.scell_cfg[cc_idx].configured = true;
common.scell_cfg[cc_idx].enabled = false;
}
// Store SCell earfcn and pci
common.scell_cfg[cc_idx].earfcn = earfcn;
common.scell_cfg[cc_idx].pci = cell.id;
common.scell_cfg[cc_idx].configured = true;
common.scell_cfg[cc_idx].enabled = false;
} else {
log_h->console("Received SCell configuration for index %d but there are not enough CC workers available\n",
scell_config->s_cell_idx_r10);
log_h->console("Received SCell configuration for index %d but there are not enough CC workers available\n", cc_idx);
}
}
void phy::set_config_tdd(tdd_cfg_s* tdd)
void phy::set_config_tdd(srslte_tdd_config_t& tdd_config_)
{
tdd_config.sf_config = tdd->sf_assign.to_number();
tdd_config.ss_config = tdd->special_sf_patterns.to_number();
tdd_config.configured = true;
tdd_config = tdd_config_;
if (!tdd_config.configured) {
log_h->console("Setting TDD-config: %d, SS config: %d\n", tdd_config.sf_config, tdd_config.ss_config);
}
tdd_config.configured = true;
for (uint32_t i = 0; i < nof_workers; i++) {
workers[i]->set_tdd_config(tdd_config);

3
srsue/src/phy/phy_common.cc
View File

@ -715,9 +715,6 @@ void phy_common::reset()
is_first_of_burst[i] = true;
}
multiple_csi_request_enabled = false;
cif_enabled = false;
srs_request_enabled = false;
ZERO_OBJECT(pending_dl_ack);
ZERO_OBJECT(pending_dl_dai);
ZERO_OBJECT(pending_ul_ack);

24
srsue/src/phy/sf_worker.cc
View File

@ -74,7 +74,6 @@ sf_worker::sf_worker(uint32_t max_prb,
}
pthread_mutex_init(&mutex, NULL);
reset_();
}
sf_worker::~sf_worker()
@ -88,16 +87,11 @@ sf_worker::~sf_worker()
void sf_worker::reset()
{
pthread_mutex_lock(&mutex);
reset_();
pthread_mutex_unlock(&mutex);
}
void sf_worker::reset_()
{
rssi_read_cnt = 0;
for (uint32_t i = 0; i < cc_workers.size(); i++) {
cc_workers[i]->reset();
}
pthread_mutex_unlock(&mutex);
}
bool sf_worker::set_cell(uint32_t cc_idx, srslte_cell_t cell)
@ -185,22 +179,14 @@ void sf_worker::enable_pregen_signals(bool enabled)
}
}
void sf_worker::set_pcell_config(srsue::phy_interface_rrc_lte::phy_cfg_t* phy_cfg)
{
pthread_mutex_lock(&mutex);
Info("Setting PCell configuration for cc_worker=%d, cc=%d\n", get_id(), 0);
cc_workers[0]->set_pcell_config(phy_cfg);
pthread_mutex_unlock(&mutex);
}
void sf_worker::set_scell_config(uint32_t cc_idx, asn1::rrc::scell_to_add_mod_r10_s* scell_config)
void sf_worker::set_config(uint32_t cc_idx, srslte::phy_cfg_t& phy_cfg)
{
pthread_mutex_lock(&mutex);
if (cc_idx < cc_workers.size()) {
Info("Setting SCell configuration for cc_worker=%d, cc=%d\n", get_id(), cc_idx);
cc_workers[cc_idx]->set_scell_config(scell_config);
Info("Setting configuration for cc_worker=%d, cc=%d\n", get_id(), cc_idx);
cc_workers[cc_idx]->set_config(phy_cfg);
} else {
Error("Setting scell config for cc=%d; Not enough CC workers;\n", cc_idx);
Error("Setting config for cc=%d; Invalid cc_idx\n", cc_idx);
}
pthread_mutex_unlock(&mutex);
}

16
srsue/src/stack/mac/mac.cc
View File

@ -95,6 +95,10 @@ bool mac::init(phy_interface_mac_lte* phy, rlc_interface_mac* rlc, rrc_interface
reset();
// Set default MAC parameters
mac_cfg_t default_cfg = {};
set_config(default_cfg);
initialized = true;
return true;
@ -562,17 +566,17 @@ void mac::set_mbsfn_config(uint32_t nof_mbsfn_services)
void mac::set_config(mac_cfg_t& mac_cfg)
{
// Set configuration for each module in MAC
bsr_procedure.set_config(mac_cfg.get_bsr_cfg());
phr_procedure.set_config(mac_cfg.get_phr_cfg());
sr_procedure.set_config(mac_cfg.get_sr_cfg());
ra_procedure.set_config(mac_cfg.get_rach_cfg());
ul_harq_cfg = mac_cfg.get_harq_cfg();
bsr_procedure.set_config(mac_cfg.bsr_cfg);
phr_procedure.set_config(mac_cfg.phr_cfg);
sr_procedure.set_config(mac_cfg.sr_cfg);
ra_procedure.set_config(mac_cfg.rach_cfg);
ul_harq_cfg = mac_cfg.harq_cfg;
for (auto& i : ul_harq) {
if (i != nullptr) {
i->set_config(ul_harq_cfg);
}
}
setup_timers(mac_cfg.get_time_alignment_timer());
setup_timers(mac_cfg.time_alignment_timer);
}
void mac::setup_lcid(uint32_t lcid, uint32_t lcg, uint32_t priority, int PBR_x_tti, uint32_t BSD)

2
srsue/src/stack/mac/proc_bsr.cc
View File

@ -75,7 +75,7 @@ void bsr_proc::reset()
trigger_tti = 0;
}
void bsr_proc::set_config(srsue::mac_interface_rrc::bsr_cfg_t& bsr_cfg)
void bsr_proc::set_config(srslte::bsr_cfg_t& bsr_cfg)
{
pthread_mutex_lock(&mutex);

2
srsue/src/stack/mac/proc_phr.cc
View File

@ -58,7 +58,7 @@ void phr_proc::reset()
phr_is_triggered = false;
}
void phr_proc::set_config(srsue::mac_interface_rrc::phr_cfg_t& cfg)
void phr_proc::set_config(srslte::phr_cfg_t& cfg)
{
phr_cfg = cfg;

2
srsue/src/stack/mac/proc_ra.cc
View File

@ -91,7 +91,7 @@ void ra_proc::start_pcap(srslte::mac_pcap* pcap_)
}
/* Sets a new configuration. The configuration is applied by initialization() function */
void ra_proc::set_config(srsue::mac_interface_rrc::rach_cfg_t& rach_cfg)
void ra_proc::set_config(srslte::rach_cfg_t& rach_cfg)
{
std::unique_lock<std::mutex> ul(mutex);
new_cfg = rach_cfg;

2
srsue/src/stack/mac/proc_sr.cc
View File

@ -66,7 +66,7 @@ bool sr_proc::need_tx(uint32_t tti)
return false;
}
void sr_proc::set_config(srsue::mac_interface_rrc::sr_cfg_t& cfg)
void sr_proc::set_config(srslte::sr_cfg_t& cfg)
{
sr_cfg = cfg;
}

2
srsue/src/stack/mac/ul_harq.cc
View File

@ -77,7 +77,7 @@ void ul_harq_entity::reset_ndi()
}
}
void ul_harq_entity::set_config(srsue::mac_interface_rrc_common::ul_harq_cfg_t& harq_cfg)
void ul_harq_entity::set_config(srslte::ul_harq_cfg_t& harq_cfg)
{
this->harq_cfg = harq_cfg;
}

395
srsue/src/stack/rrc/rrc.cc
View File

@ -157,10 +157,8 @@ void rrc::init(phy_interface_rrc_lte* phy_,
pending_mob_reconf = false;
// Set default values for all layers
// Set default values for RRC. MAC and PHY are set to default themselves
set_rrc_default();
set_phy_default();
set_mac_default();
measurements.init(this);
@ -1274,7 +1272,7 @@ void rrc::ho_failed()
void rrc::con_reconfig_failed()
{
// Set previous PHY/MAC configuration
phy->set_config(&previous_phy_cfg);
phy->set_config(previous_phy_cfg);
mac->set_config(previous_mac_cfg);
// And restore current configs
@ -1595,7 +1593,10 @@ void rrc::handle_sib1()
// Set TDD Config
if (sib1->tdd_cfg_present) {
phy->set_config_tdd(&sib1->tdd_cfg);
srslte_tdd_config_t tdd_config;
tdd_config.sf_config = sib1->tdd_cfg.sf_assign.to_number();
tdd_config.ss_config = sib1->tdd_cfg.special_sf_patterns.to_number();
phy->set_config_tdd(tdd_config);
}
}
@ -1606,20 +1607,21 @@ void rrc::handle_sib2()
sib_type2_s* sib2 = serving_cell->sib2ptr();
// Apply RACH and timeAlginmentTimer configuration
current_mac_cfg.set_rach_cfg_common(sib2->rr_cfg_common.rach_cfg_common);
current_mac_cfg.set_time_alignment(sib2->time_align_timer_common);
set_mac_cfg_t_rach_cfg_common(&current_mac_cfg, sib2->rr_cfg_common.rach_cfg_common);
set_mac_cfg_t_time_alignment(&current_mac_cfg, sib2->time_align_timer_common);
mac->set_config(current_mac_cfg);
// Set MBSFN configs
phy->set_config_mbsfn_sib2(sib2);
// Apply PHY RR Config Common
current_phy_cfg.common.pdsch_cnfg = sib2->rr_cfg_common.pdsch_cfg_common;
current_phy_cfg.common.pusch_cnfg = sib2->rr_cfg_common.pusch_cfg_common;
current_phy_cfg.common.pucch_cnfg = sib2->rr_cfg_common.pucch_cfg_common;
current_phy_cfg.common.ul_pwr_ctrl = sib2->rr_cfg_common.ul_pwr_ctrl_common;
current_phy_cfg.common.prach_cnfg = sib2->rr_cfg_common.prach_cfg;
current_phy_cfg.common.srs_ul_cnfg = sib2->rr_cfg_common.srs_ul_cfg_common;
set_phy_cfg_t_common_pdsch(&current_phy_cfg, sib2->rr_cfg_common.pdsch_cfg_common);
set_phy_cfg_t_common_pusch(&current_phy_cfg, sib2->rr_cfg_common.pusch_cfg_common);
set_phy_cfg_t_common_pucch(&current_phy_cfg, sib2->rr_cfg_common.pucch_cfg_common);
set_phy_cfg_t_common_pwr_ctrl(&current_phy_cfg, sib2->rr_cfg_common.ul_pwr_ctrl_common);
set_phy_cfg_t_common_prach(
&current_phy_cfg, &sib2->rr_cfg_common.prach_cfg.prach_cfg_info, sib2->rr_cfg_common.prach_cfg.root_seq_idx);
set_phy_cfg_t_common_srs(&current_phy_cfg, sib2->rr_cfg_common.srs_ul_cfg_common);
// According to 3GPP 36.331 v12 UE-EUTRA-Capability field descriptions
// Allow 64QAM for:
@ -1627,19 +1629,19 @@ void rrc::handle_sib2()
// ue-CategoryUL 5 and 13 when enable64QAM (with suffix)
// enable64QAM-v1270 shall be ignored if enable64QAM (without suffix) is false
if (args.ue_category == 5 || (args.release >= 10 && args.ue_category == 8)) {
current_phy_cfg.common.rrc_enable_64qam = sib2->rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam;
set_phy_cfg_t_enable_64qam(&current_phy_cfg, sib2->rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam);
} else if (args.release >= 12 && sib2->rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam) {
if (args.ue_category_ul == 5 || args.ue_category_ul == 13) {
// ASN1 Generator simplifies enable64QAM-v1270 because it is an enumeration that is always true
current_phy_cfg.common.rrc_enable_64qam = sib2->rr_cfg_common.pusch_cfg_common_v1270.is_present();
set_phy_cfg_t_enable_64qam(&current_phy_cfg, sib2->rr_cfg_common.pusch_cfg_common_v1270.is_present());
} else {
current_phy_cfg.common.rrc_enable_64qam = false;
set_phy_cfg_t_enable_64qam(&current_phy_cfg, false);
}
} else {
current_phy_cfg.common.rrc_enable_64qam = false;
set_phy_cfg_t_enable_64qam(&current_phy_cfg, false);
}
phy->set_config(&current_phy_cfg);
phy->set_config(current_phy_cfg);
log_rr_config_common();
@ -2278,73 +2280,76 @@ void rrc::handle_ue_capability_enquiry(const asn1::rrc::ue_cap_enquiry_s& enquir
void rrc::log_rr_config_common()
{
rrc_log->info("Set RACH ConfigCommon: NofPreambles=%d, ResponseWindow=%d, ContentionResolutionTimer=%d ms\n",
current_mac_cfg.get_rach_cfg().nof_preambles,
current_mac_cfg.get_rach_cfg().responseWindowSize,
current_mac_cfg.get_rach_cfg().contentionResolutionTimer);
current_mac_cfg.rach_cfg.nof_preambles,
current_mac_cfg.rach_cfg.responseWindowSize,
current_mac_cfg.rach_cfg.contentionResolutionTimer);
rrc_log->info("Set PUSCH ConfigCommon: HopOffset=%d, RSGroup=%d, RSNcs=%d, N_sb=%d\n",
current_phy_cfg.common.pusch_cnfg.pusch_cfg_basic.pusch_hop_offset,
current_phy_cfg.common.pusch_cnfg.ul_ref_sigs_pusch.group_assign_pusch,
current_phy_cfg.common.pusch_cnfg.ul_ref_sigs_pusch.cyclic_shift,
current_phy_cfg.common.pusch_cnfg.pusch_cfg_basic.n_sb);
rrc_log->info("Set PUSCH ConfigCommon: P0_pusch=%f, DMRS cs=%d, delta_ss=%d, N_sb=%d\n",
current_phy_cfg.ul_cfg.power_ctrl.p0_ue_pusch,
current_phy_cfg.ul_cfg.dmrs.cyclic_shift,
current_phy_cfg.ul_cfg.dmrs.delta_ss,
current_phy_cfg.ul_cfg.hopping.n_sb);
rrc_log->info("Set PUCCH ConfigCommon: DeltaShift=%d, CyclicShift=%d, N1=%d, NRB=%d\n",
current_phy_cfg.common.pucch_cnfg.delta_pucch_shift.to_number(),
current_phy_cfg.common.pucch_cnfg.n_cs_an,
current_phy_cfg.common.pucch_cnfg.n1_pucch_an,
current_phy_cfg.common.pucch_cnfg.n_rb_cqi);
current_phy_cfg.ul_cfg.pucch.delta_pucch_shift,
current_phy_cfg.ul_cfg.pucch.N_cs,
current_phy_cfg.ul_cfg.pucch.n1_pucch_an_cs[0][0],
current_phy_cfg.ul_cfg.pucch.n_rb_2);
rrc_log->info("Set PRACH ConfigCommon: SeqIdx=%d, HS=%s, FreqOffset=%d, ZC=%d, ConfigIndex=%d\n",
current_phy_cfg.common.prach_cnfg.root_seq_idx,
current_phy_cfg.common.prach_cnfg.prach_cfg_info.high_speed_flag ? "yes" : "no",
current_phy_cfg.common.prach_cnfg.prach_cfg_info.prach_freq_offset,
current_phy_cfg.common.prach_cnfg.prach_cfg_info.zero_correlation_zone_cfg,
current_phy_cfg.common.prach_cnfg.prach_cfg_info.prach_cfg_idx);
current_phy_cfg.prach_cfg.root_seq_idx,
current_phy_cfg.prach_cfg.hs_flag ? "yes" : "no",
current_phy_cfg.prach_cfg.freq_offset,
current_phy_cfg.prach_cfg.zero_corr_zone,
current_phy_cfg.prach_cfg.config_idx);
if (current_phy_cfg.common.srs_ul_cnfg.type() == setup_e::setup) {
rrc_log->info("Set SRS ConfigCommon: BW-Configuration=%d, SF-Configuration=%d, ACKNACK=%s\n",
current_phy_cfg.common.srs_ul_cnfg.setup().srs_bw_cfg.to_number(),
current_phy_cfg.common.srs_ul_cnfg.setup().srs_sf_cfg.to_number(),
current_phy_cfg.common.srs_ul_cnfg.setup().ack_nack_srs_simul_tx ? "yes" : "no");
if (current_phy_cfg.ul_cfg.srs.configured) {
rrc_log->info("Set SRS ConfigCommon: BW-Configuration=%d, SF-Configuration=%d, Simult-ACKNACK=%s\n",
current_phy_cfg.ul_cfg.srs.bw_cfg,
current_phy_cfg.ul_cfg.srs.subframe_config,
current_phy_cfg.ul_cfg.srs.simul_ack ? "yes" : "no");
}
}
void rrc::apply_rr_config_common(rr_cfg_common_s* config, bool send_lower_layers)
{
if (config->rach_cfg_common_present) {
current_mac_cfg.set_rach_cfg_common(config->rach_cfg_common);
set_mac_cfg_t_rach_cfg_common(&current_mac_cfg, config->rach_cfg_common);
}
phy_interface_rrc_lte::phy_cfg_common_t* common = &current_phy_cfg.common;
if (config->prach_cfg.prach_cfg_info_present) {
common->prach_cnfg.prach_cfg_info = config->prach_cfg.prach_cfg_info;
set_phy_cfg_t_common_prach(&current_phy_cfg, &config->prach_cfg.prach_cfg_info, config->prach_cfg.root_seq_idx);
} else {
set_phy_cfg_t_common_prach(&current_phy_cfg, NULL, config->prach_cfg.root_seq_idx);
}
common->prach_cnfg.root_seq_idx = config->prach_cfg.root_seq_idx;
if (config->pdsch_cfg_common_present) {
common->pdsch_cnfg = config->pdsch_cfg_common;
set_phy_cfg_t_common_pdsch(&current_phy_cfg, config->pdsch_cfg_common);
}
common->pusch_cnfg = config->pusch_cfg_common;
set_phy_cfg_t_common_pusch(&current_phy_cfg, config->pusch_cfg_common);
if (config->phich_cfg_present) {
common->phich_cnfg = config->phich_cfg;
// TODO
}
if (config->pucch_cfg_common_present) {
common->pucch_cnfg = config->pucch_cfg_common;
set_phy_cfg_t_common_pucch(&current_phy_cfg, config->pucch_cfg_common);
}
if (config->srs_ul_cfg_common_present) {
common->srs_ul_cnfg = config->srs_ul_cfg_common;
set_phy_cfg_t_common_srs(&current_phy_cfg, config->srs_ul_cfg_common);
}
if (config->ul_pwr_ctrl_common_present) {
common->ul_pwr_ctrl = config->ul_pwr_ctrl_common;
set_phy_cfg_t_common_pwr_ctrl(&current_phy_cfg, config->ul_pwr_ctrl_common);
}
// TODO: p_max, antenna_info, tdd...
log_rr_config_common();
if (send_lower_layers) {
mac->set_config(current_mac_cfg);
phy->set_config(&current_phy_cfg);
phy->set_config(current_phy_cfg);
}
}
@ -2353,69 +2358,42 @@ void rrc::log_phy_config_dedicated()
if (!rrc_log) {
return;
}
phys_cfg_ded_s* current_cfg = &current_phy_cfg.dedicated;
if (current_cfg->pdsch_cfg_ded_present) {
rrc_log->info("Set PDSCH-Config p_a=%s\n", current_cfg->pdsch_cfg_ded.p_a.to_string().c_str());
if (current_phy_cfg.dl_cfg.cqi_report.periodic_configured) {
rrc_log->info("Set cqi-PUCCH-ResourceIndex=%d, cqi-pmi-ConfigIndex=%d, cqi-FormatIndicatorPeriodic=%d\n",
current_phy_cfg.ul_cfg.pucch.n_pucch_2,
current_phy_cfg.dl_cfg.cqi_report.pmi_idx,
current_phy_cfg.dl_cfg.cqi_report.periodic_mode);
}
if (current_phy_cfg.dl_cfg.cqi_report.aperiodic_configured) {
rrc_log->info("Set cqi-ReportModeAperiodic=%d\n", current_phy_cfg.dl_cfg.cqi_report.aperiodic_mode);
}
if (current_cfg->cqi_report_cfg_present) {
if (current_cfg->cqi_report_cfg.cqi_report_periodic_present and
current_cfg->cqi_report_cfg.cqi_report_periodic.type() == setup_e::setup) {
rrc_log->info(
"Set cqi-PUCCH-ResourceIndex=%d, cqi-pmi-ConfigIndex=%d, cqi-FormatIndicatorPeriodic=%s\n",
current_cfg->cqi_report_cfg.cqi_report_periodic.setup().cqi_pucch_res_idx,
current_cfg->cqi_report_cfg.cqi_report_periodic.setup().cqi_pmi_cfg_idx,
current_cfg->cqi_report_cfg.cqi_report_periodic.setup().cqi_format_ind_periodic.type().to_string().c_str());
}
if (current_cfg->cqi_report_cfg.cqi_report_mode_aperiodic_present) {
rrc_log->info("Set cqi-ReportModeAperiodic=%s\n",
current_cfg->cqi_report_cfg.cqi_report_mode_aperiodic.to_string().c_str());
}
}
if (current_cfg->sched_request_cfg_present and current_cfg->sched_request_cfg.type() == setup_e::setup) {
if (current_phy_cfg.ul_cfg.pucch.sr_configured) {
rrc_log->info("Set PHY config ded: SR-n_pucch=%d, SR-ConfigIndex=%d, SR-TransMax=%d\n",
current_cfg->sched_request_cfg.setup().sr_pucch_res_idx,
current_cfg->sched_request_cfg.setup().sr_cfg_idx,
current_cfg->sched_request_cfg.setup().dsr_trans_max.to_number());
current_phy_cfg.ul_cfg.pucch.n_pucch_sr,
current_phy_cfg.ul_cfg.pucch.I_sr,
current_mac_cfg.sr_cfg.dsr_transmax);
}
if (current_cfg->srs_ul_cfg_ded_present and current_cfg->srs_ul_cfg_ded.type() == setup_e::setup) {
rrc_log->info("Set PHY config ded: SRS-ConfigIndex=%d, SRS-bw=%s, SRS-Nrcc=%d, SRS-hop=%s, SRS-Ncs=%s\n",
current_cfg->srs_ul_cfg_ded.setup().srs_cfg_idx,
current_cfg->srs_ul_cfg_ded.setup().srs_bw.to_string().c_str(),
current_cfg->srs_ul_cfg_ded.setup().freq_domain_position,
current_cfg->srs_ul_cfg_ded.setup().srs_hop_bw.to_string().c_str(),
current_cfg->srs_ul_cfg_ded.setup().cyclic_shift.to_string().c_str());
if (current_phy_cfg.ul_cfg.srs.configured) {
rrc_log->info("Set PHY config ded: SRS-ConfigIndex=%d, SRS-bw=%d, SRS-Nrcc=%d, SRS-hop=%d, SRS-Ncs=%d\n",
current_phy_cfg.ul_cfg.srs.I_srs,
current_phy_cfg.ul_cfg.srs.bw_cfg,
current_phy_cfg.ul_cfg.srs.n_rrc,
current_phy_cfg.ul_cfg.srs.b_hop,
current_phy_cfg.ul_cfg.srs.n_srs);
}
}
// Apply default physical common
void rrc::set_phy_config_common_default()
// Apply default physical common and dedicated configuration
void rrc::set_phy_default()
{
// Get PUCCH config and reset
pucch_cfg_common_s* pucch_cnfg = &current_phy_cfg.common.pucch_cnfg;
*pucch_cnfg = {};
pucch_cnfg->delta_pucch_shift = pucch_cfg_common_s::delta_pucch_shift_opts::ds1;
// Get UL power control, reset and set defaults
ul_pwr_ctrl_common_s* ul_pwr_ctrl = &current_phy_cfg.common.ul_pwr_ctrl;
*ul_pwr_ctrl = {};
ul_pwr_ctrl->alpha.value = alpha_r12_opts::al0;
ul_pwr_ctrl->delta_flist_pucch.delta_f_pucch_format1.value =
delta_flist_pucch_s::delta_f_pucch_format1_opts::delta_f0;
ul_pwr_ctrl->delta_flist_pucch.delta_f_pucch_format1b.value =
delta_flist_pucch_s::delta_f_pucch_format1b_opts::delta_f1;
ul_pwr_ctrl->delta_flist_pucch.delta_f_pucch_format2.value =
delta_flist_pucch_s::delta_f_pucch_format2_opts::delta_f0;
ul_pwr_ctrl->delta_flist_pucch.delta_f_pucch_format2a.value =
delta_flist_pucch_s::delta_f_pucch_format2a_opts::delta_f0;
ul_pwr_ctrl->delta_flist_pucch.delta_f_pucch_format2b.value =
delta_flist_pucch_s::delta_f_pucch_format2b_opts::delta_f0;
current_phy_cfg.set_defaults_dedicated();
current_phy_cfg.set_defaults_common();
if (phy != nullptr) {
phy->set_config(&current_phy_cfg);
phy->set_config(current_phy_cfg);
} else {
rrc_log->info("RRC not initialized. Skipping default PHY config.\n");
}
@ -2424,62 +2402,10 @@ void rrc::set_phy_config_common_default()
// Apply default physical channel configs (9.2.4)
void rrc::set_phy_config_dedicated_default()
{
// Get current configuration
phys_cfg_ded_s* current_cfg = &current_phy_cfg.dedicated;
// Reset all present flags
*current_cfg = {};
// Set defaults
current_cfg->pdsch_cfg_ded_present = true;
current_cfg->pdsch_cfg_ded.p_a = pdsch_cfg_ded_s::p_a_e_::db0;
current_cfg->pucch_cfg_ded_present = true;
current_cfg->pucch_cfg_ded.tdd_ack_nack_feedback_mode_present = true;
current_cfg->pucch_cfg_ded.tdd_ack_nack_feedback_mode = pucch_cfg_ded_s::tdd_ack_nack_feedback_mode_e_::bundling;
current_cfg->pucch_cfg_ded.ack_nack_repeat.set(setup_e::release);
current_cfg->pusch_cfg_ded_present = true;
current_cfg->pusch_cfg_ded.beta_offset_ack_idx = 10;
current_cfg->pusch_cfg_ded.beta_offset_ri_idx = 12;
current_cfg->pusch_cfg_ded.beta_offset_cqi_idx = 15;
current_cfg->ul_pwr_ctrl_ded_present = true;
current_cfg->ul_pwr_ctrl_ded.p0_ue_pusch = 0;
current_cfg->ul_pwr_ctrl_ded.delta_mcs_enabled = ul_pwr_ctrl_ded_s::delta_mcs_enabled_e_::en0;
current_cfg->ul_pwr_ctrl_ded.accumulation_enabled = true;
current_cfg->ul_pwr_ctrl_ded.p0_ue_pucch = 0;
current_cfg->ul_pwr_ctrl_ded.p_srs_offset = 7;
current_cfg->ul_pwr_ctrl_ded.filt_coef_present = true;
current_cfg->ul_pwr_ctrl_ded.filt_coef = filt_coef_e::fc4;
current_cfg->tpc_pdcch_cfg_pucch_present = true;
current_cfg->tpc_pdcch_cfg_pucch.set(setup_e::release);
current_cfg->tpc_pdcch_cfg_pusch_present = true;
current_cfg->tpc_pdcch_cfg_pusch.set(setup_e::release);
current_cfg->cqi_report_cfg_present = true;
current_cfg->cqi_report_cfg.cqi_report_periodic_present = true;
current_cfg->cqi_report_cfg.cqi_report_periodic.set(setup_e::release);
current_cfg->srs_ul_cfg_ded_present = true;
current_cfg->srs_ul_cfg_ded.set(setup_e::release);
current_cfg->ant_info_present = true;
current_cfg->ant_info.set_explicit_value();
current_cfg->ant_info.explicit_value().tx_mode = ant_info_ded_s::tx_mode_e_::tm1;
current_cfg->ant_info.explicit_value().codebook_subset_restrict_present = false;
current_cfg->ant_info.explicit_value().ue_tx_ant_sel.set(setup_e::release);
current_cfg->sched_request_cfg_present = true;
current_cfg->sched_request_cfg.set(setup_e::release);
log_phy_config_dedicated();
current_phy_cfg.set_defaults_dedicated();
if (phy != nullptr) {
phy->set_config(&current_phy_cfg);
phy->set_config(current_phy_cfg);
} else {
rrc_log->info("RRC not initialized. Skipping default PHY config.\n");
}
@ -2488,82 +2414,47 @@ void rrc::set_phy_config_dedicated_default()
// Apply provided PHY config
void rrc::apply_phy_config_dedicated(const phys_cfg_ded_s& phy_cnfg)
{
// Get current configuration
phys_cfg_ded_s* current_cfg = &current_phy_cfg.dedicated;
if (phy_cnfg.pucch_cfg_ded_present) {
current_cfg->pucch_cfg_ded_present = true;
current_cfg->pucch_cfg_ded = phy_cnfg.pucch_cfg_ded;
}
current_cfg->cqi_report_cfg_pcell_v1250 = phy_cnfg.cqi_report_cfg_pcell_v1250;
current_cfg->pucch_cfg_ded_v1020 = phy_cnfg.pucch_cfg_ded_v1020;
if (phy_cnfg.pusch_cfg_ded_present) {
current_cfg->pusch_cfg_ded_present = true;
current_cfg->pusch_cfg_ded = phy_cnfg.pusch_cfg_ded;
}
if (phy_cnfg.ul_pwr_ctrl_ded_present) {
current_cfg->ul_pwr_ctrl_ded_present = true;
current_cfg->ul_pwr_ctrl_ded = phy_cnfg.ul_pwr_ctrl_ded;
}
if (phy_cnfg.ul_pwr_ctrl_ded.filt_coef_present) {
current_cfg->ul_pwr_ctrl_ded.filt_coef_present = true;
current_cfg->ul_pwr_ctrl_ded.filt_coef = phy_cnfg.ul_pwr_ctrl_ded.filt_coef;
}
if (phy_cnfg.tpc_pdcch_cfg_pucch_present) {
current_cfg->tpc_pdcch_cfg_pucch_present = true;
current_cfg->tpc_pdcch_cfg_pucch = phy_cnfg.tpc_pdcch_cfg_pucch;
}
if (phy_cnfg.tpc_pdcch_cfg_pusch_present) {
current_cfg->tpc_pdcch_cfg_pusch_present = true;
current_cfg->tpc_pdcch_cfg_pusch = phy_cnfg.tpc_pdcch_cfg_pusch;
}
if (phy_cnfg.cqi_report_cfg_present) {
current_cfg->cqi_report_cfg_present = true;
if (phy_cnfg.cqi_report_cfg.cqi_report_periodic_present) {
current_cfg->cqi_report_cfg.cqi_report_periodic_present = true;
current_cfg->cqi_report_cfg.cqi_report_periodic = phy_cnfg.cqi_report_cfg.cqi_report_periodic;
}
if (phy_cnfg.cqi_report_cfg.cqi_report_mode_aperiodic_present) {
current_cfg->cqi_report_cfg.cqi_report_mode_aperiodic_present = true;
current_cfg->cqi_report_cfg.cqi_report_mode_aperiodic = phy_cnfg.cqi_report_cfg.cqi_report_mode_aperiodic;
}
current_cfg->cqi_report_cfg.nom_pdsch_rs_epre_offset = phy_cnfg.cqi_report_cfg.nom_pdsch_rs_epre_offset;
}
if (phy_cnfg.srs_ul_cfg_ded_present) {
current_cfg->srs_ul_cfg_ded_present = true;
current_cfg->srs_ul_cfg_ded = phy_cnfg.srs_ul_cfg_ded;
}
if (phy_cnfg.ant_info_present) {
current_cfg->ant_info_present = true;
current_cfg->ant_info = phy_cnfg.ant_info;
}
if (phy_cnfg.sched_request_cfg_present) {
current_cfg->sched_request_cfg_present = true;
current_cfg->sched_request_cfg = phy_cnfg.sched_request_cfg;
}
if (phy_cnfg.pdsch_cfg_ded_present) {
current_cfg->pdsch_cfg_ded_present = true;
current_cfg->pdsch_cfg_ded = phy_cnfg.pdsch_cfg_ded;
}
set_phy_cfg_t_dedicated_cfg(&current_phy_cfg, phy_cnfg);
log_phy_config_dedicated();
if (phy != nullptr) {
phy->set_config(&current_phy_cfg);
phy->set_config(current_phy_cfg);
} else {
rrc_log->info("RRC not initialized. Skipping PHY config.\n");
}
}
void rrc::apply_phy_scell_config(const asn1::rrc::scell_to_add_mod_r10_s* scell_config)
{
srslte_cell_t scell = {};
uint32_t earfcn = 0;
// Initialise default parameters from primary cell
phy->get_current_cell(&scell, &earfcn);
// Parse identification
if (scell_config->cell_identif_r10_present) {
scell.id = scell_config->cell_identif_r10.pci_r10;
earfcn = scell_config->cell_identif_r10.dl_carrier_freq_r10;
}
// Parse radio resource
if (scell_config->rr_cfg_common_scell_r10_present) {
const rr_cfg_common_scell_r10_s* rr_cfg = &scell_config->rr_cfg_common_scell_r10;
scell.frame_type = (rr_cfg->tdd_cfg_v1130.is_present()) ? SRSLTE_TDD : SRSLTE_FDD;
scell.nof_prb = rr_cfg->non_ul_cfg_r10.dl_bw_r10.to_number();
scell.nof_ports = rr_cfg->non_ul_cfg_r10.ant_info_common_r10.ant_ports_count.to_number();
scell.phich_length = (srslte_phich_length_t)rr_cfg->non_ul_cfg_r10.phich_cfg_r10.phich_dur.value;
scell.phich_resources = (srslte_phich_r_t)rr_cfg->non_ul_cfg_r10.phich_cfg_r10.phich_res.value;
}
// Initialize scell config with pcell cfg
srslte::phy_cfg_t scell_phy_cfg = current_phy_cfg;
set_phy_cfg_t_scell_config(&scell_phy_cfg, scell_config);
if (phy != nullptr) {
phy->set_config(scell_phy_cfg, scell_config->s_cell_idx_r10, earfcn, &scell);
} else {
rrc_log->info("RRC not initialized. Skipping PHY config.\n");
}
@ -2572,14 +2463,14 @@ void rrc::apply_phy_config_dedicated(const phys_cfg_ded_s& phy_cnfg)
void rrc::log_mac_config_dedicated()
{
rrc_log->info("Set MAC main config: harq-MaxReTX=%d, bsr-TimerReTX=%d, bsr-TimerPeriodic=%d\n",
current_mac_cfg.get_harq_cfg().max_harq_msg3_tx,
current_mac_cfg.get_bsr_cfg().retx_timer,
current_mac_cfg.get_bsr_cfg().periodic_timer);
if (current_mac_cfg.get_phr_cfg().enabled) {
current_mac_cfg.harq_cfg.max_harq_msg3_tx,
current_mac_cfg.bsr_cfg.retx_timer,
current_mac_cfg.bsr_cfg.periodic_timer);
if (current_mac_cfg.phr_cfg.enabled) {
rrc_log->info("Set MAC PHR config: periodicPHR-Timer=%d, prohibitPHR-Timer=%d, dl-PathlossChange=%d\n",
current_mac_cfg.get_phr_cfg().periodic_timer,
current_mac_cfg.get_phr_cfg().prohibit_timer,
current_mac_cfg.get_phr_cfg().db_pathloss_change);
current_mac_cfg.phr_cfg.periodic_timer,
current_mac_cfg.phr_cfg.prohibit_timer,
current_mac_cfg.phr_cfg.db_pathloss_change);
}
}
@ -2592,31 +2483,25 @@ void rrc::apply_mac_config_dedicated_default()
log_mac_config_dedicated();
}
void rrc::apply_mac_config_dedicated_explicit(mac_main_cfg_s mac_cnfg)
{
current_mac_cfg.set_mac_main_cfg(mac_cnfg);
mac->set_config(current_mac_cfg);
log_mac_config_dedicated();
}
bool rrc::apply_rr_config_dedicated(rr_cfg_ded_s* cnfg)
{
if (cnfg->phys_cfg_ded_present) {
apply_phy_config_dedicated(cnfg->phys_cfg_ded);
// Apply SR configuration to MAC
if (cnfg->phys_cfg_ded.sched_request_cfg_present) {
current_mac_cfg.set_sched_request_cfg(cnfg->phys_cfg_ded.sched_request_cfg);
set_mac_cfg_t_sched_request_cfg(&current_mac_cfg, cnfg->phys_cfg_ded.sched_request_cfg);
}
}
if (cnfg->mac_main_cfg_present) {
if (cnfg->mac_main_cfg.type() == rr_cfg_ded_s::mac_main_cfg_c_::types::default_value) {
apply_mac_config_dedicated_default();
current_mac_cfg.set_mac_main_cfg_default();
} else {
apply_mac_config_dedicated_explicit(cnfg->mac_main_cfg.explicit_value());
set_mac_cfg_t_main_cfg(&current_mac_cfg, cnfg->mac_main_cfg.explicit_value());
}
mac->set_config(current_mac_cfg);
} else if (cnfg->phys_cfg_ded.sched_request_cfg_present) {
// If MAC-main not set but SR config is set, use directly mac->set_config to update confi
// If MAC-main not set but SR config is set, use directly mac->set_config to update config
mac->set_config(current_mac_cfg);
log_mac_config_dedicated();
}
@ -2694,7 +2579,7 @@ void rrc::apply_scell_config(asn1::rrc::rrc_conn_recfg_r8_ies_s* reconfig_r8)
mac->reconfiguration(scell_config->s_cell_idx_r10, true);
// Call phy reconfiguration
phy->set_config_scell(scell_config);
apply_phy_scell_config(scell_config);
}
}
@ -2921,22 +2806,10 @@ void rrc::add_mrb(uint32_t lcid, uint32_t port)
// PHY CONFIG DEDICATED Defaults (3GPP 36.331 v10 9.2.4)
void rrc::set_phy_default_pucch_srs()
{
// FIXME: Check 5.3.13 again, there are some fields that are not reset
// Set defaults to CQI, SRS and SR
current_phy_cfg.dedicated.cqi_report_cfg_present = false;
current_phy_cfg.dedicated.srs_ul_cfg_ded_present = false;
current_phy_cfg.dedicated.sched_request_cfg_present = false;
rrc_log->info("Setting default PHY config dedicated\n");
set_phy_config_dedicated_default();
}
void rrc::set_phy_default()
{
set_phy_config_common_default();
set_phy_config_dedicated_default();
}
void rrc::set_mac_default() {
apply_mac_config_dedicated_default();
}

5
srsue/test/mac_test.cc
View File

@ -19,6 +19,7 @@
*
*/
#include "srslte/asn1/rrc_asn1_utils.h"
#include "srslte/common/log_filter.h"
#include "srslte/common/mac_pcap.h"
#include "srslte/interfaces/ue_interfaces.h"
@ -1344,8 +1345,8 @@ int mac_random_access_test()
// Configure MAC
mac mac(&mac_log);
mac.init(&phy, &rlc, &rrc, &timers);
mac_interface_rrc::mac_cfg_t mac_cfg;
mac_cfg.set_rach_cfg_common(rach_cfg);
srslte::mac_cfg_t mac_cfg;
set_mac_cfg_t_rach_cfg_common(&mac_cfg, rach_cfg);
mac.set_config(mac_cfg);
// generate config for LCIDs in different LCGs than CCCH