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osmo-small-hardware
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116 Commits

Author SHA1 Message Date
Harald Welte 3d507d68ef sfp-breakout: X1 pin 5 missing connection to VCC_3V3 
Due to an overisght, pin 5 of the X1 header was missing the intended
connection to the 3V3 plane.  Let's fix this.  No routing changes on the
PCB required, as this simply connects the VCC plane layer to the
through-hole.
 2018-09-05 12:38:19 +02:00
Martin Schramm 157dfbf79f sfp: add part numbers for SFP conn and cage 2018-08-30 17:37:36 +02:00
Martin Schramm 2c9fc33df4 mvuart: align JP2 in 0.1' grid with JP3 (solves OSM#3037) 2018-08-23 20:41:26 +02:00
Harald Welte ad2df019cb sfp-{breakout,experimenter}: Commit GERBER exports 2018-08-21 19:47:28 +02:00
Harald Welte 86f788b33e sfp: Use minimum clearance of 0.25mm as 0.15mm is needlessly tight in this board 2018-08-21 19:46:57 +02:00
Martin Schramm 74b053d521 sfp: remove unneeded layer in brd + sch 2018-08-17 21:37:47 +02:00
Martin Schramm 7ca3444a52 sfp: add LOS, TX_FAULT LEDs + add more supply pinheader on both PCBs 2018-08-17 21:33:19 +02:00
Martin Schramm ee9af12fb6 spf: revise both SFP designs (OSM#3313/OSM#3314) 2018-08-17 19:14:25 +02:00
Martin Schramm e1af031d54 sfp: commit simple SFP breakout (OSM#3313) 2018-06-19 20:25:57 +02:00
Martin Schramm 47b1cc901e sfp: add license to sch 2018-06-19 18:57:24 +02:00
Martin Schramm e24141d5c0 sfp: commit first proposal for PCB w/ LVDS xcvr (adresses OSM#3314) 2018-06-19 18:13:58 +02:00
Martin Schramm 351b418019 sfp: add Eagle libs for SN65LVDS1 and SN65LVDT2 (single line LVDS rcv/drv) 2018-06-08 22:37:16 +02:00
Martin Schramm d429b75341 sfp: add Eagle lib for SN65LVDS180 LVDS diff line xcvr 2018-06-07 17:26:44 +02:00
Martin Schramm b3ba2a28b8 sfp.lbr: review tnt's SFP lib, refine 2018-06-06 21:42:01 +02:00
Martin Schramm 757356b035 mv-uart.brd: add signal names of JP2,JP3,JP5 in bottom silk screen 
solves OSM#2387
 2018-05-18 22:54:37 +02:00
Harald Welte 4e58d03412 mv-uart: annotate individual pins in brd and generate mv-uart-pinout.pdf 2017-07-22 10:44:51 +02:00
Harald Welte 251847b561 mpcie-breakout: add v3 pictures 2017-05-24 02:45:36 +02:00
Harald Welte 5d7d725c13 e1-tap: Add BOM attributes 2017-05-07 18:31:11 +02:00
Harald Welte 7a142572a1 import e1-tap design files 
This is a project started in 2012 to have an easy-to-use E1/T1 tap.
 2017-05-07 18:07:50 +02:00
Harald Welte 1e942e6ae4 mpcie-breakout: update schematics + placement PDF with v3 2017-04-04 14:43:53 +02:00
Harald Welte fe19750d59 mpcie-breakout: update .mnt/.mnb files with v3 pcb 2017-04-04 14:39:12 +02:00
Harald Welte 6d45c43dc9 mpcie-breakout: move PCB specs to pcb subdirectory where they belong 2017-03-25 01:56:28 +01:00
Harald Welte 00d9e6923b import PCB and stencil specs for v3 2017-03-25 01:45:55 +01:00
Harald Welte 2c15563524 mpcie-breakout: update BOM 2017-03-23 21:56:10 +01:00
Harald Welte c0c8bd5d2f mpcie-breakout: Restore link for M1 (mPCIe mounting clamp) 2017-03-23 21:54:32 +01:00
Harald Welte 972c8a0cb8 mpcie-breakout: Change to vertical SMA jacks 2017-03-23 21:49:04 +01:00
Harald Welte eb08c68a3e mpcie-breakout: rounding of pads 2017-03-23 21:34:09 +01:00
Harald Welte 8d11394ffa mpcie-breakout: DRC changes 2017-03-23 21:18:35 +01:00
Harald Welte 5704c5bdc9 mpcie-breakout: disable tPlace layer 2017-03-23 21:16:26 +01:00
Harald Welte 724e3f879e mpcie-breakout: USB_VBUS second parallel via to reduce impedance 2017-03-23 21:04:14 +01:00
Harald Welte c7db59d408 mpcie-breakout: Digikey part numbers for U.FL and SMA 2017-03-23 20:51:53 +01:00
Harald Welte d86d7286d1 mcie-breakout: Align bLabels, more vias, cosmetics 2017-03-23 20:46:23 +01:00
Harald Welte b496b068aa mpcie-breakout: Add third U.FL-SMA group 2017-03-23 20:25:13 +01:00
Harald Welte 623924050d mpcie-breakout: Enlarge to 70x70mm, add SMA, U.FL and Mounting Holes 2017-03-23 17:24:01 +01:00
Harald Welte 9b5d540b1f mv-uart: Fix 'board doesn't enumerate if JP4 is closed" issue 
Make sure the LDO is always powered up, so the CP2105 internal and
external !RESET pull-ups are towards an active VIO voltage, rather than
one that is switched off by !SUSPEND and thus keeps the CP2105 in reset.

Closes: #1870 (https://osmocom.org/issues/1870)
 2016-12-05 19:42:27 +01:00
Harald Welte 2093ba575d add PCBA photographs 2016-11-25 17:05:33 +01:00
Harald Welte 50c018de16 mpcie-breakoud: Add pdf renderings of schematics 2016-10-28 16:19:52 +02:00
Harald Welte 05e5237337 add mnb/mt files for mv-uart and mpcie-breakout 2016-10-28 16:19:36 +02:00
Harald Welte cf99c3f3cf mpcie-breakout: mark C4 as POPULATED=FALSE 2016-10-28 16:06:59 +02:00
Harald Welte db16b1529f mv-uart: Add schematics + placement as PDF 2016-10-28 15:58:45 +02:00
Harald Welte 304e6f53ff mv-uart: Add digikey attributes for various 2.54mm hedaers 2016-10-28 15:56:18 +02:00
Harald Welte 9a742af2cf add PCB panel images for mv-uart and mpcie-breakout 2016-10-28 15:36:55 +02:00
Harald Welte c70006a70c mpcie-breakout: Change '1' marker of JP4 and avoid silk-screen overlap 2016-10-27 20:09:19 +02:00
Harald Welte 0427388990 mpcie-breakout: fix DRC violations (clearance) 2016-10-27 19:53:11 +02:00
Harald Welte 9eb09df373 mpcie-breakout: Add series LED for LED_WWAN 2016-10-27 19:49:06 +02:00
Harald Welte ab542cd1af mpcie-breakout: Fix R4 (0603, not 0201 part) 2016-10-27 19:41:37 +02:00
Harald Welte 7001d5fb4f mpcie-breakout: change 100uF caps from 1210 to 1206, reducing height 
The current 100uF caps are too high at 2.9mm.  They touch the shielding
can of Quectel EC-20 modules, for exampel.  Let's use 1206 packaged
versions at 1.6mm instead.  Also, add two more, for safety.
 2016-10-27 19:35:03 +02:00
Harald Welte 746eda7f13 mv-uart: Use SP6T flash *without* OFF position 2016-10-27 17:56:24 +02:00
Harald Welte 07cf79c97a mpci-breakout: Add BOM attributes + export BOM 2016-10-10 17:56:57 +02:00
Harald Welte dc5f8d5611 add .gitignore 2016-10-10 17:34:01 +02:00