Harald Welte
ff2d7b03e0
clock-gen: Minor changes; final version as ordered
...
* move DC jack to extend beyond PCB edge into front panel
* harmonize component variants (10n only 0402, 4.7u only 0805)
* add "sysmocom" as manufacturer name (WEEE requirement)
2019-01-27 18:17:36 +01:00
Harald Welte
51315a16ff
clock-gen: Cosmetic changes
2019-01-27 18:02:10 +01:00
Harald Welte
c82c71b3c0
clock-gen: finish routing of PCB layout
2019-01-27 17:00:46 +01:00
Harald Welte
73acd67b00
clock-gen: Connect EEPROM WP to GND to disable write-protect
2019-01-26 21:21:47 +01:00
Harald Welte
69aea8bd5c
clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing
2019-01-26 20:57:42 +01:00
Harald Welte
40b61a84c9
clock-generator: Most of the layout
...
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper.
2019-01-23 19:50:30 +01:00
Harald Welte
ef5f4655c8
clock-generator: More schematics work; initial placement/grouping
...
* add I2C EEPROM
* start board design file
* group parts to their respective "main part"
* define TC-2030 pinout
2019-01-23 00:13:00 +01:00
Harald Welte
63b23976a7
clock-generator: More work on schematics (USB, UART, ESD)
2019-01-21 22:43:27 +01:00
Harald Welte
bf89576eff
initial check-in of upcoming clock-generator board
2019-01-16 22:13:42 +01:00
Harald Welte