Martin Schramm
abdefdccdb
clock-generator: upd ext'd BOM attributes and update v2 eBOM
2020-07-07 17:38:32 +02:00
Harald Welte
617288296f
clock-generator: Fix VDD connection of TC2050 SWD connector
...
Closes: OS#4431
2020-03-01 19:42:20 +01:00
Martin Schramm
7d09b416a2
clock-gen: increase I2C PU's to 4k7
...
Although the SI5153 datasheet mentions the I2C PUs as ">=1k", this
appears to be unusually strong for no obvious reason, and we don't
have high data rates there... changed them to more reasonable 4k7.
2020-02-07 20:00:44 +01:00
Martin Schramm
44e584624a
clock-gen: update ATSAMD21's BOM attributes (solves OS#4387)
2020-01-31 18:19:20 +01:00
Martin Schramm
895c6d3dde
clock-generator: exchange mini-USB foorprint (solves OS#4386)
...
... and purge unneeded layers
2020-01-30 18:03:26 +01:00
Martin Schramm
e2cdc91a3a
<osmo-clock-gen: add more TVS for exposed signals, clean up and finish
2019-06-19 19:10:50 +02:00
Martin Schramm
436048290a
osmo-clock-gen: capacitive coupling for XA input needed - added 100n
...
This was a remark by tnt, thanks.
2019-06-19 19:10:50 +02:00
Martin Schramm
c3f627affe
clock-generator: compacting + place MTA100 header (solves OSM#4050)
2019-06-19 19:10:50 +02:00
Martin Schramm
425699d67a
clock-generator: changes adressing OSM#4050
...
A shouded UEXT would need much space; no room for an MTA100 yet... tbd
2019-06-19 19:10:50 +02:00
Martin Schramm
4cd9ee1bd7
clock-generator: insert changes discussed so far for v2
...
* selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC)
* use SAMD21 instead of SAMD11
* bring some GPIO on pin header
* use GCLK_IO4 (PA10) to feed XA of PLL
2019-06-19 19:10:50 +02:00
Martin Schramm
e1714e7432
clock-generator: add tracking LDO, make PCB four layer
2019-06-19 19:10:50 +02:00
Harald Welte
cdaf319147
WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21
...
Closes: OS#3856
2019-06-19 19:10:50 +02:00
Harald Welte
bbbd83c9dd
clock-gen: Add BOM information + PDF exports of schematics
2019-01-28 12:38:59 +01:00
Harald Welte
ff2d7b03e0
clock-gen: Minor changes; final version as ordered
...
* move DC jack to extend beyond PCB edge into front panel
* harmonize component variants (10n only 0402, 4.7u only 0805)
* add "sysmocom" as manufacturer name (WEEE requirement)
2019-01-27 18:17:36 +01:00
Harald Welte
51315a16ff
clock-gen: Cosmetic changes
2019-01-27 18:02:10 +01:00
Harald Welte
c82c71b3c0
clock-gen: finish routing of PCB layout
2019-01-27 17:00:46 +01:00
Harald Welte
73acd67b00
clock-gen: Connect EEPROM WP to GND to disable write-protect
2019-01-26 21:21:47 +01:00
Harald Welte
69aea8bd5c
clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing
2019-01-26 20:57:42 +01:00
Harald Welte
40b61a84c9
clock-generator: Most of the layout
...
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper.
2019-01-23 19:50:30 +01:00
Harald Welte
ef5f4655c8
clock-generator: More schematics work; initial placement/grouping
...
* add I2C EEPROM
* start board design file
* group parts to their respective "main part"
* define TC-2030 pinout
2019-01-23 00:13:00 +01:00
Harald Welte
63b23976a7
clock-generator: More work on schematics (USB, UART, ESD)
2019-01-21 22:43:27 +01:00
Harald Welte
bf89576eff
initial check-in of upcoming clock-generator board
2019-01-16 22:13:42 +01:00
Martin Schramm
Harald Welte