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341 Commits

Author SHA1 Message Date
Martin Schramm 436048290a osmo-clock-gen: capacitive coupling for XA input needed - added 100n 
This was a remark by tnt, thanks.
 2019-06-19 19:10:50 +02:00
Martin Schramm c3f627affe clock-generator: compacting + place MTA100 header (solves OSM#4050) 2019-06-19 19:10:50 +02:00
Martin Schramm 425699d67a clock-generator: changes adressing OSM#4050 
A shouded UEXT would need much space; no room for an MTA100 yet... tbd
 2019-06-19 19:10:50 +02:00
Martin Schramm 4cd9ee1bd7 clock-generator: insert changes discussed so far for v2 
* selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC)
* use SAMD21 instead of SAMD11
* bring some GPIO on pin header
* use GCLK_IO4 (PA10) to feed XA of PLL
 2019-06-19 19:10:50 +02:00
Martin Schramm e1714e7432 clock-generator: add tracking LDO, make PCB four layer 2019-06-19 19:10:50 +02:00
Harald Welte cdaf319147 WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21 
Closes: OS#3856
 2019-06-19 19:10:50 +02:00
Martin Schramm 85fc4063bb sfp-*: add OSHW logo, fill ext'd attribs for BOM 2019-05-09 18:33:33 +02:00
Martin Schramm 89cbce6ffb sfp: update BOMs for both breakout and experimenter PCBs 2019-05-08 20:33:46 +02:00
Harald Welte f37aa06c2a clock-converter: Export BOM 2019-02-14 22:06:36 +01:00
Harald Welte 22ad1c0a54 clock-converter: Add attributes with digikey links 2019-02-14 22:06:22 +01:00
Harald Welte 6d4dd1bead Clock converter for low phase noise sine -> square conversion 2019-02-02 11:50:41 +01:00
Harald Welte bbbd83c9dd clock-gen: Add BOM information + PDF exports of schematics 2019-01-28 12:38:59 +01:00
Harald Welte 0240e5c8c9 clock-gen: Update gpio spreadsheet with all assignments 
The assignments have been chosen to be nearly identical to the
SAMD11-XPRO board.
 2019-01-27 19:17:06 +01:00
Harald Welte fcc91db897 Merge branch 'laforge/clock-gen' 2019-01-27 18:24:51 +01:00
Harald Welte ff2d7b03e0 clock-gen: Minor changes; final version as ordered 
* move DC jack to extend beyond PCB edge into front panel
* harmonize component variants (10n only 0402, 4.7u only 0805)
* add "sysmocom" as manufacturer name (WEEE requirement)
 2019-01-27 18:17:36 +01:00
Harald Welte 51315a16ff clock-gen: Cosmetic changes 2019-01-27 18:02:10 +01:00
Harald Welte c82c71b3c0 clock-gen: finish routing of PCB layout 2019-01-27 17:00:46 +01:00
Harald Welte 73acd67b00 clock-gen: Connect EEPROM WP to GND to disable write-protect 2019-01-26 21:21:47 +01:00
Harald Welte 69aea8bd5c clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing 2019-01-26 20:57:42 +01:00
Harald Welte 40b61a84c9 clock-generator: Most of the layout 
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper.
 2019-01-23 19:50:30 +01:00
Harald Welte ef5f4655c8 clock-generator: More schematics work; initial placement/grouping 
* add I2C EEPROM
* start board design file
* group parts to their respective "main part"
* define TC-2030 pinout
 2019-01-23 00:13:00 +01:00
Harald Welte 63b23976a7 clock-generator: More work on schematics (USB, UART, ESD) 2019-01-21 22:43:27 +01:00
Harald Welte bf89576eff initial check-in of upcoming clock-generator board 2019-01-16 22:13:42 +01:00
Martin Schramm 680384cd6d SFP: publish experimenter and breakout schematicss as pdf 2019-01-08 16:39:11 +01:00
Harald Welte 29cf4f0514 add SFP multi-source agreement to give context to the boards 2018-10-06 21:15:17 +02:00
Harald Welte 3d507d68ef sfp-breakout: X1 pin 5 missing connection to VCC_3V3 
Due to an overisght, pin 5 of the X1 header was missing the intended
connection to the 3V3 plane.  Let's fix this.  No routing changes on the
PCB required, as this simply connects the VCC plane layer to the
through-hole.
 2018-09-05 12:38:19 +02:00
Martin Schramm 157dfbf79f sfp: add part numbers for SFP conn and cage 2018-08-30 17:37:36 +02:00
Martin Schramm 2c9fc33df4 mvuart: align JP2 in 0.1' grid with JP3 (solves OSM#3037) 2018-08-23 20:41:26 +02:00
Harald Welte ad2df019cb sfp-{breakout,experimenter}: Commit GERBER exports 2018-08-21 19:47:28 +02:00
Harald Welte 86f788b33e sfp: Use minimum clearance of 0.25mm as 0.15mm is needlessly tight in this board 2018-08-21 19:46:57 +02:00
Martin Schramm 74b053d521 sfp: remove unneeded layer in brd + sch 2018-08-17 21:37:47 +02:00
Martin Schramm 7ca3444a52 sfp: add LOS, TX_FAULT LEDs + add more supply pinheader on both PCBs 2018-08-17 21:33:19 +02:00
Martin Schramm ee9af12fb6 spf: revise both SFP designs (OSM#3313/OSM#3314) 2018-08-17 19:14:25 +02:00
Martin Schramm e1af031d54 sfp: commit simple SFP breakout (OSM#3313) 2018-06-19 20:25:57 +02:00
Martin Schramm 47b1cc901e sfp: add license to sch 2018-06-19 18:57:24 +02:00
Martin Schramm e24141d5c0 sfp: commit first proposal for PCB w/ LVDS xcvr (adresses OSM#3314) 2018-06-19 18:13:58 +02:00
Martin Schramm 351b418019 sfp: add Eagle libs for SN65LVDS1 and SN65LVDT2 (single line LVDS rcv/drv) 2018-06-08 22:37:16 +02:00
Martin Schramm d429b75341 sfp: add Eagle lib for SN65LVDS180 LVDS diff line xcvr 2018-06-07 17:26:44 +02:00
Martin Schramm b3ba2a28b8 sfp.lbr: review tnt's SFP lib, refine 2018-06-06 21:42:01 +02:00
Martin Schramm 757356b035 mv-uart.brd: add signal names of JP2,JP3,JP5 in bottom silk screen 
solves OSM#2387
 2018-05-18 22:54:37 +02:00
Harald Welte 4e58d03412 mv-uart: annotate individual pins in brd and generate mv-uart-pinout.pdf 2017-07-22 10:44:51 +02:00
Harald Welte 251847b561 mpcie-breakout: add v3 pictures 2017-05-24 02:45:36 +02:00
Harald Welte 5d7d725c13 e1-tap: Add BOM attributes 2017-05-07 18:31:11 +02:00
Harald Welte 7a142572a1 import e1-tap design files 
This is a project started in 2012 to have an easy-to-use E1/T1 tap.
 2017-05-07 18:07:50 +02:00
Harald Welte 1e942e6ae4 mpcie-breakout: update schematics + placement PDF with v3 2017-04-04 14:43:53 +02:00
Harald Welte fe19750d59 mpcie-breakout: update .mnt/.mnb files with v3 pcb 2017-04-04 14:39:12 +02:00
Harald Welte 6d45c43dc9 mpcie-breakout: move PCB specs to pcb subdirectory where they belong 2017-03-25 01:56:28 +01:00
Harald Welte 00d9e6923b import PCB and stencil specs for v3 2017-03-25 01:45:55 +01:00
Harald Welte 2c15563524 mpcie-breakout: update BOM 2017-03-23 21:56:10 +01:00
Harald Welte c0c8bd5d2f mpcie-breakout: Restore link for M1 (mPCIe mounting clamp) 2017-03-23 21:54:32 +01:00