Commit Graph

6 Commits

Author SHA1 Message Date
Harald Welte 953376a0c5 WIP: plutosdr-revb-extclk: support switching back to original 40MHz XO 2023-08-11 13:56:30 +02:00
Harald Welte fbae9bd476 plutosdr-revb-extclk: Fix capacitor footprints
* Always use _0603 and not 0603 (oversized)
* 1uF can be 0603, only 10uF should be 0805

Related: OS#5892
2023-07-02 12:55:54 +02:00
Harald Welte dbd53d6df5 plutosdr-revb-extclk: don't shut-down LTC via SD1/SD2
In the original PlutoSDR RevC or higher, there's a BSS138 FET
that [optionally] pulls low the SD1/SD2 pins in order to activate
the external clock input.

In this circuit, we don't have GPIO control but permanently enable
the LTC.

Related: OS#5892
2023-07-02 12:55:54 +02:00
Harald Welte 69dc3c912b [cosmetic] plutosdr-revb-extclk: Route last missing airwire inside pad
Related: OS#5892
2023-07-02 12:55:54 +02:00
Harald Welte 25624c5fa7 new X.21 "jumper box" design
DB-15 male + female connector with rows of pin headers to use jumper
wires to connect signals in any desired combination/permutation.
2023-03-04 13:58:54 +01:00
Harald Welte 0e6eb31ec7 New design: plutosdr-revb-extclk
This is a small circuit board containing the "external clock ref input"
circuitry that was added to PlutoSDR RevD.  It can be used to
upgrade/rework RevB boards with the same clock input as the later RevD.

Related: OS#5892
2023-02-12 17:32:32 +01:00