integrate picolibc and its stdio
This commit is contained in:
parent
77eda9fcb7
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8bcec75693
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@ -0,0 +1,4 @@
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#pragma once
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#include <stdint.h>
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void iob_init(uint32_t usart);
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#pragma once
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int watchdog_init(void);
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void watchdog_fini(void);
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void watchdog_refresh(void);
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#include <stdio.h>
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#include <libopencm3/cm3/scb.h>
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#include <libopencm3/cm3/nvic.h>
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#ifndef STM32F1
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#include <libopencm3/stm32/syscfg.h>
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#endif
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struct hardfault_args {
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unsigned long r0;
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unsigned long r1;
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unsigned long r2;
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unsigned long r3;
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unsigned long r12;
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unsigned long lr;
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unsigned long pc;
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unsigned long psr;
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};
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extern void hard_fault_handler_c(struct hardfault_args *args);
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__attribute__((naked))
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void hard_fault_handler(void)
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{
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__asm( ".syntax unified\n"
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"movs r0, #4 \n"
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"mov r1, lr \n"
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"tst r0, r1 \n"
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"beq _MSP \n"
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"mrs r0, psp \n"
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"b _CHAND \n"
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"_MSP: \n"
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"mrs r0, msp \n"
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"_CHAND: \n"
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"b hard_fault_handler_c\n"
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".syntax divided\n");
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}
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void hard_fault_handler_c(struct hardfault_args *args)
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{
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//usart_stop(1, 0);
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fprintf(stderr, "HARDFAULT\r\n");
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fprintf(stderr, "R0=%08lx, R1=%08lx, R2=%08lx, R3=%08lx, R12=%08lx\r\n",
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args->r0, args->r1, args->r2, args->r3, args->r12);
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fprintf(stderr, "LR[R14]=%08lx, PC[R15]=%08lx, PSR=%08lx\r\n",
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args->lr, args->pc, args->psr);
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/* we better reset the CPU to avoid getting stuck in some state */
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scb_reset_system();
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}
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void nmi_handler(void)
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{
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/* We better do a reset in case we receive a NMI */
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fprintf(stderr, "NMI\r\n");
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#ifdef SYSCFG_CFGR2
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if (SYSCFG_CFGR2 & 0x10) {
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fprintf(stderr, "PARITY\r\n");
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SYSCFG_CFGR2 = 0x10;
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}
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#endif
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scb_reset_system();
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}
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#include <stdio.h>
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#include <sys/cdefs.h>
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#include <libopencm3/stm32/usart.h>
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#include <libcommon/iob.h>
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/* picolibc iob implementation for blocking I/O on USART */
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static uint32_t stdio_usart;
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void iob_init(uint32_t usart)
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{
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stdio_usart = usart;
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}
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static int my_putc(char c, FILE *file)
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{
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(void) file;
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usart_send_blocking(stdio_usart, c);
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return c;
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}
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static int my_getc(FILE *file)
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{
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(void) file;
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return usart_recv_blocking(stdio_usart);
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}
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static int my_flush(FILE *file)
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{
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(void) file;
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return 0;
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}
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static FILE __stdio = FDEV_SETUP_STREAM(my_putc, my_getc, my_flush, _FDEV_SETUP_RW);
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FILE *const __iob[3] = { &__stdio, &__stdio, &__stdio };
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#include <stdio.h>
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#include <sys/cdefs.h>
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/usart.h>
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#include <libcommon/iob.h>
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#include <librfn/ringbuf.h>
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/* picolibc iob implementation for non-blocking I/O on USART via ring-buffer */
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static uint32_t stdio_usart;
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static uint8_t outbuf[1024];
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static ringbuf_t outring = RINGBUF_VAR_INIT(outbuf, sizeof(outbuf));
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static uint8_t inbuf[256];
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static ringbuf_t inring = RINGBUF_VAR_INIT(inbuf, sizeof(inbuf));
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void iob_init(uint32_t usart)
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{
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cm3_assert(usart == USART2);
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stdio_usart = usart;
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nvic_enable_irq(NVIC_USART2_IRQ);
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/* Enable RX non-empty interrupt */
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USART_CR1(stdio_usart) |= USART_CR1_RXNEIE;
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}
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/* FIXME: this obviously doesn't work with iob_init() getting passed a dynamic UART */
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void usart2_isr(void)
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{
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if ((USART_CR1(stdio_usart) & USART_CR1_RXNEIE) &&
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(USART_SR(stdio_usart) & USART_SR_RXNE)) {
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uint16_t c = usart_recv(stdio_usart);
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ringbuf_put(&inring, c);
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}
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if ((USART_CR1(stdio_usart) & USART_CR1_TXEIE) &&
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(USART_SR(stdio_usart) & USART_SR_TXE)) {
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int data = ringbuf_get(&outring);
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if (data == -1) {
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USART_CR1(stdio_usart) &= ~USART_CR1_TXEIE;
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} else {
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usart_send(stdio_usart, data);
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}
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}
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}
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/* buffered output to stdout */
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static int my_stdout_putc(char c, FILE *file)
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{
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(void) file;
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cm3_assert(stdio_usart);
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ringbuf_put(&outring, c);
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USART_CR1(stdio_usart) |= USART_CR1_TXEIE;
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return c;
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}
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/* unbuffered, blocking output to stderr (e.g. for assert, fault handlers, ...) */
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static int my_stderr_putc(char c, FILE *file)
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{
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(void) file;
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cm3_assert(stdio_usart);
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usart_send_blocking(stdio_usart, c);
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return c;
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}
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static int my_stdin_getc(FILE *file)
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{
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(void) file;
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int data = ringbuf_get(&inring);
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if (data == -1)
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return EOF;
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else
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return data;
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}
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static int my_stdout_flush(FILE *file)
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{
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(void) file;
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do { } while (!ringbuf_empty(&outring));
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return 0;
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}
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static FILE __stdin = FDEV_SETUP_STREAM(NULL, my_stdin_getc, NULL, _FDEV_SETUP_READ);
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static FILE __stdout = FDEV_SETUP_STREAM(my_stdout_putc, NULL, my_stdout_flush, _FDEV_SETUP_WRITE);
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static FILE __stderr = FDEV_SETUP_STREAM(my_stderr_putc, NULL, NULL, _FDEV_SETUP_WRITE);
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FILE *const __iob[3] = { &__stdin, &__stdout, &__stderr };
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#include <sys/types.h>
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#include <signal.h>
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#include <unistd.h>
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#include <errno.h>
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pid_t getpid(void) { return 1; }
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int kill(pid_t pid, int sig) { if (pid == 1) _exit(sig << 8); errno = ESRCH; return -1; }
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/wwdg.h>
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#include <libcommon/watchdog.h>
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void watchdog_refresh(void)
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{
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/* set to the maximum a 7-bit counter supports */
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WWDG_CR = 0x7f;
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}
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#ifdef DEBUG_WATCHDOG
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void WWDG_IRQHandler(void)
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{
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WWDG_ClearFlag();
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/* instead of triggering a reset, we hang in this endless loop to wait
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* for openocd/gdb attach and investigation of the stack */
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watchdog_fini();
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printf("WWDG\r\n");
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while(1) {}
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}
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#endif
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void watchdog_fini(void)
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{
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/* documentation claims we cannot stop it. lol. */
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watchdog_refresh();
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rcc_periph_clock_disable(RCC_WWDG);
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}
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int watchdog_init(void)
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{
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#ifdef RCC_DBGMCU
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/* make sure the watchdog stops during JTAG stop */
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rcc_periph_clock_enable(RCC_DBGMCU);
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DBGMCU_CR |= DBGMCU_CR_WWDG_STOP
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#endif
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rcc_periph_clock_enable(RCC_WWDG);
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/* Set WWDG clock to (PCLK1/4096)/8 */
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/* At 8 MHz PCLK1 this is 244.14 Hz */
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WWDG_CFR = (WWDG_CFR & ~WWDG_CFR_WDGTB_LSB) | WWDG_CFR_WDGTB_CK_DIV8;
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#ifdef DEBUG_WATCHDOG
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NVIC_InitTypeDef nvic_init = {
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.NVIC_IRQChannelPriority = 0,
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.NVIC_IRQChannel = WWDG_IRQn,
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.NVIC_IRQChannelCmd = ENABLE,
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};
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WWDG_EnableIT();
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NVIC_Init(&nvic_init);
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#endif
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/* highest possible window value */
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WWDG_CFR = (WWDG_CFR & WWDG_CFR_WDGTB_LSB) | 0x7f;
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/* this means, that we have 0x80-0x40= 64 cycles of the 214.14Hz
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* watchdog clock tore-fresh the counter, before it reaches
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* 0x3F, at which point a reset will be issued to the CPU. If my
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* calculations are correct, this is 0.262 seconds, i.e.
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* refreshing every time the systick timer fires (and we return
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* to the main loop) should be sufficient. */
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WWDG_CR = WWDG_CR_WDGA | 0x7f;
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return 0;
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}
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vpath %.c $(LIBRFN_DIR)/librfn
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vpath %.c $(LIBRFN_DIR)/librfn/libopencm3
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CPPFLAGS += -DNDEBUG
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CPPFLAGS += -DCONFIG_CONSOLE_FROM_ISR=1
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#CPPFLAGS += -DNDEBUG
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#CPPFLAGS += -DCONFIG_CONSOLE_FROM_ISR=1
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CPPFLAGS += -I$(LIBRFN_DIR)/include
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BINARY = rfdsatt
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OBJS = attenuator.o board_rfdsatt_4ch.o
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LDSCRIPT = ./stm32f103-openblt.ld
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OOCD_INTERFACE ?= stlink-v2
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OOCD_TARGET ?= stm32f1x
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ARCH_FLAGS += --specs=/usr/lib/picolibc/arm-none-eabi/picolibc.specs
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LIBCOMMON_DIR = ../../libcommon
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CPPFLAGS += -I$(LIBCOMMON_DIR)/include
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vpath %.c $(LIBCOMMON_DIR)/src/
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OBJS += watchdog.o fault.o iob_stm32_nonblocking.o kill.o
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all: elf bin srec
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include ../../mk/librfn.mk
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include ../rules.mk
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/systick.h>
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#include <libcommon/iob.h>
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#include <stdio.h>
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#include "attenuator.h"
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#include "misc.h"
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extern const struct attenuator_cfg board_att_cfg;
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extern struct attenuator_state *board_att_st[];
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volatile uint32_t jiffies;
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void sys_tick_handler(void)
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rcc_periph_clock_enable(RCC_USART2);
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}
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static void i2c_setup(void)
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{
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rcc_periph_clock_enable(RCC_I2C1);
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gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
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GPIO_I2C1_SCL | GPIO_I2C1_SDA);
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/* disable before making config changes */
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i2c_peripheral_disable(I2C1);
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/* APB1 runs at 24 MHz */
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i2c_set_clock_frequency(I2C1, I2C_CR2_FREQ_24MHZ);
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/* 400 kHz fast mode I2C */
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//i2c_set_fast_mode(I2C1);
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//...
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i2c_peripheral_enable(I2C1);
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}
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static void usart_setup(void)
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{
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/* USART1: connected to debug header */
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/* Setup GPIO pin GPIO_USART1_TX. */
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gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX);
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/* Setup UART parameters. */
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usart_set_baudrate(USART1, 115200);
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usart_set_databits(USART1, 8);
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usart_set_mode(USART1, USART_MODE_TX);
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usart_set_parity(USART1, USART_PARITY_NONE);
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usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE);
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/* Finally enable the USART. */
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usart_enable(USART1);
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/* USART2: connected to 2.5mm stereo jack */
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/* Setup GPIO pin GPIO_USART2_TX. */
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gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX);
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/* Setup UART parameters. */
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usart_set_baudrate(USART2, 115200);
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usart_set_databits(USART2, 8);
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usart_set_mode(USART2, USART_MODE_TX);
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usart_set_parity(USART2, USART_PARITY_NONE);
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usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
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/* Finally enable the USART. */
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usart_enable(USART2);
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}
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int main(void)
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{
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int i, j = 0, c = 0;
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clock_setup();
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gpio_setup();
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usart_setup();
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iob_init(USART2);
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i2c_setup();
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attenuator_init(&board_att_cfg, board_att_st);
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/* Blink the LED (PB15) on the board with every transmitted byte. */
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while (1) {
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int i;
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gpio_toggle(GPIOB, GPIO15); /* LED on/off */
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usart_send_blocking(USART1, c + '0'); /* USART1: Send byte. */
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usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */
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c = (c == 9) ? 0 : c + 1; /* Increment c. */
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if ((j++ % 80) == 0) { /* Newline after line full. */
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usart_send_blocking(USART1, '\r');
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usart_send_blocking(USART1, '\n');
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usart_send_blocking(USART2, '\r');
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usart_send_blocking(USART2, '\n');
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}
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printf("Hello world\r\n");
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for (i = 0; i < 800000; i++) /* Wait a bit. */
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__asm__("nop");
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}
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