Remove unused firmware parts and convert to SAMD11 MCU
USB enumerates as: [ 9799.235446] usb 6-1.7: Product: osmo-clkgen [ 9799.235448] usb 6-1.7: Manufacturer: sysmocom GmbH [ 9799.235450] usb 6-1.7: SerialNumber: 123456 [ 9799.237866] hid-generic 0003:6666:6666.000F: hiddev0,hidraw4: USB HID v1.11 Device [sysmocom GmbH osmo-clkgen] on usb-0000:00:1d.0-1.7/input0
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@ -1,76 +0,0 @@
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/*
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* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*- Includes ----------------------------------------------------------------*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "samd21.h"
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#include "hal_gpio.h"
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#include "nvm_data.h"
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#include "dac.h"
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/*- Definitions -------------------------------------------------------------*/
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HAL_GPIO_PIN(ADC, A, 3)
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/*- Implementations ---------------------------------------------------------*/
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//-----------------------------------------------------------------------------
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void adc_init(void)
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{
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HAL_GPIO_ADC_in();
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HAL_GPIO_ADC_pmuxen(HAL_GPIO_PMUX_B);
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PM->APBCMASK.reg |= PM_APBCMASK_ADC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(ADC_GCLK_ID) |
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GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
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ADC->CTRLA.reg = ADC_CTRLA_SWRST;
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while (ADC->CTRLA.reg & ADC_CTRLA_SWRST);
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ADC->REFCTRL.reg = ADC_REFCTRL_REFSEL_INTVCC1 | ADC_REFCTRL_REFCOMP;
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ADC->CTRLB.reg = ADC_CTRLB_RESSEL_16BIT | ADC_CTRLB_PRESCALER_DIV32;
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ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_128;
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ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXPOS_PIN1 | ADC_INPUTCTRL_MUXNEG_GND |
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ADC_INPUTCTRL_GAIN_DIV2;
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ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(NVM_READ_CAL(ADC_BIASCAL)) |
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ADC_CALIB_LINEARITY_CAL(NVM_READ_CAL(ADC_LINEARITY));
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ADC->CTRLA.reg = ADC_CTRLA_ENABLE;
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}
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//-----------------------------------------------------------------------------
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int adc_read(void)
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{
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ADC->SWTRIG.reg = ADC_SWTRIG_START;
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while (0 == (ADC->INTFLAG.reg & ADC_INTFLAG_RESRDY));
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return ADC->RESULT.reg;
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}
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@ -1,37 +0,0 @@
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/*
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* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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||||
* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ADC_H_
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#define _ADC_H_
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/*- Prototypes --------------------------------------------------------------*/
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void adc_init(void);
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int adc_read(void);
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#endif // _ADC_H_
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@ -1,65 +0,0 @@
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/*
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* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*- Includes ----------------------------------------------------------------*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "samd21.h"
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#include "hal_gpio.h"
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#include "dac.h"
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/*- Definitions -------------------------------------------------------------*/
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HAL_GPIO_PIN(DAC, A, 2)
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/*- Implementations ---------------------------------------------------------*/
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//-----------------------------------------------------------------------------
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void dac_init(void)
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{
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HAL_GPIO_DAC_out();
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HAL_GPIO_DAC_pmuxen(HAL_GPIO_PMUX_B);
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PM->APBCMASK.reg |= PM_APBCMASK_DAC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(DAC_GCLK_ID) |
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GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
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DAC->CTRLA.reg = DAC_CTRLA_SWRST;
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while (DAC->CTRLA.reg & DAC_CTRLA_SWRST);
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DAC->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL_AVCC;
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DAC->CTRLA.reg = DAC_CTRLA_ENABLE;
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}
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//-----------------------------------------------------------------------------
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void dac_write(int value)
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{
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DAC->DATA.reg = value;
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}
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@ -1,37 +0,0 @@
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/*
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* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
|
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DAC_H_
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#define _DAC_H_
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/*- Prototypes --------------------------------------------------------------*/
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void dac_init(void);
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void dac_write(int value);
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#endif // _DAC_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "samd21.h"
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#include "samd11.h"
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#include "debug.h"
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#include "hal_gpio.h"
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/*- Definitions -------------------------------------------------------------*/
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HAL_GPIO_PIN(UART_TX, A, 22)
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HAL_GPIO_PIN(UART_RX, A, 23)
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HAL_GPIO_PIN(UART_TX, A, 10)
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HAL_GPIO_PIN(UART_RX, A, 11)
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/*- Implementations ---------------------------------------------------------*/
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HAL_GPIO_UART_RX_in();
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HAL_GPIO_UART_RX_pmuxen(PORT_PMUX_PMUXE_C_Val);
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PM->APBCMASK.reg |= PM_APBCMASK_SERCOM3;
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PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(SERCOM3_GCLK_ID_CORE) |
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(SERCOM0_GCLK_ID_CORE) |
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GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
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SERCOM3->USART.CTRLA.reg =
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SERCOM0->USART.CTRLA.reg =
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SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE_USART_INT_CLK |
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SERCOM_USART_CTRLA_RXPO(1/*PAD1*/) | SERCOM_USART_CTRLA_TXPO(0/*PAD0*/);
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SERCOM_USART_CTRLA_RXPO(3/*PAD3*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/);
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SERCOM3->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN |
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SERCOM0->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN |
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SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/);
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SERCOM3->USART.BAUD.reg = (uint16_t)br;
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SERCOM0->USART.BAUD.reg = (uint16_t)br+1;
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SERCOM3->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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SERCOM0->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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}
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//-----------------------------------------------------------------------------
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void debug_putc(char c)
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{
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while (!(SERCOM3->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE));
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SERCOM3->USART.DATA.reg = c;
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while (!(SERCOM0->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE));
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SERCOM0->USART.DATA.reg = c;
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}
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//-----------------------------------------------------------------------------
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186
firmware/gpio.c
186
firmware/gpio.c
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/*
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* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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||||
*/
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/*- Includes ----------------------------------------------------------------*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "samd21.h"
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#include "hal_gpio.h"
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#include "gpio.h"
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/*- Definitions -------------------------------------------------------------*/
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#define GPIO_COUNT 8
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HAL_GPIO_PIN(0, B, 0);
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HAL_GPIO_PIN(1, B, 1);
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HAL_GPIO_PIN(2, B, 2);
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HAL_GPIO_PIN(3, B, 3);
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HAL_GPIO_PIN(4, B, 4);
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HAL_GPIO_PIN(5, B, 5);
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HAL_GPIO_PIN(6, B, 6);
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HAL_GPIO_PIN(7, B, 7);
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enum
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{
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GPIO_0_MSK = (1 << 0),
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GPIO_1_MSK = (1 << 1),
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GPIO_2_MSK = (1 << 2),
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GPIO_3_MSK = (1 << 3),
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GPIO_4_MSK = (1 << 4),
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GPIO_5_MSK = (1 << 5),
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GPIO_6_MSK = (1 << 6),
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GPIO_7_MSK = (1 << 7),
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};
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enum
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{
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GPIO_CONF_DISABLE = 1 << 0,
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GPIO_CONF_INPUT = 1 << 1,
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GPIO_CONF_OUTPUT = 1 << 2,
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GPIO_CONF_PULLUP = 1 << 3,
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GPIO_CONF_PULLDOWN = 1 << 4,
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GPIO_CONF_SET = 1 << 3, // Intentional overlap with PULLUP / PULLDOWN
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GPIO_CONF_CLR = 1 << 4,
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};
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/*- Variables ---------------------------------------------------------------*/
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static int gpio_config[GPIO_COUNT];
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/*- Implementations ---------------------------------------------------------*/
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//-----------------------------------------------------------------------------
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#define GEN_CONFIG_FN(i) \
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static void gpio_config_fn_##i(int conf) \
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{ \
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if (conf & GPIO_CONF_DISABLE) \
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{ \
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HAL_GPIO_##i##_in(); \
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HAL_GPIO_##i##_clr(); \
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HAL_GPIO_##i##_pullen(0); \
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} \
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else if (conf & GPIO_CONF_INPUT) \
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{ \
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HAL_GPIO_##i##_in(); \
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HAL_GPIO_##i##_pullen(conf & (GPIO_CONF_PULLUP | GPIO_CONF_PULLDOWN)); \
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HAL_GPIO_##i##_write(conf & GPIO_CONF_PULLUP); \
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} \
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else if (conf & GPIO_CONF_OUTPUT) \
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{ \
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HAL_GPIO_##i##_out(); \
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HAL_GPIO_##i##_pullen(0); \
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HAL_GPIO_##i##_write(conf & GPIO_CONF_SET); \
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} \
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gpio_config[i] = conf; \
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}
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//-----------------------------------------------------------------------------
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GEN_CONFIG_FN(0)
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GEN_CONFIG_FN(1)
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GEN_CONFIG_FN(2)
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GEN_CONFIG_FN(3)
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GEN_CONFIG_FN(4)
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GEN_CONFIG_FN(5)
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GEN_CONFIG_FN(6)
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GEN_CONFIG_FN(7)
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//-----------------------------------------------------------------------------
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void gpio_init(void)
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{
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for (int i = 0; i < GPIO_COUNT; i++)
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gpio_configure(i, GPIO_CONF_DISABLE);
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}
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//-----------------------------------------------------------------------------
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void gpio_configure(int index, int conf)
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{
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if (0 == index)
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gpio_config_fn_0(conf);
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else if (1 == index)
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gpio_config_fn_1(conf);
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else if (2 == index)
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gpio_config_fn_2(conf);
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else if (3 == index)
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gpio_config_fn_3(conf);
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else if (4 == index)
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gpio_config_fn_4(conf);
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else if (5 == index)
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gpio_config_fn_5(conf);
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else if (6 == index)
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gpio_config_fn_6(conf);
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else if (7 == index)
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gpio_config_fn_7(conf);
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}
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//-----------------------------------------------------------------------------
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int gpio_read(int index)
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{
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if (0 == index)
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return HAL_GPIO_0_read();
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else if (1 == index)
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return HAL_GPIO_1_read();
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else if (2 == index)
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return HAL_GPIO_2_read();
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else if (3 == index)
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return HAL_GPIO_3_read();
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else if (4 == index)
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return HAL_GPIO_4_read();
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else if (5 == index)
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return HAL_GPIO_5_read();
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else if (6 == index)
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return HAL_GPIO_6_read();
|
||||
else if (7 == index)
|
||||
return HAL_GPIO_7_read();
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
void gpio_write(int index, int value)
|
||||
{
|
||||
if (0 == (gpio_config[index] & GPIO_CONF_OUTPUT))
|
||||
return;
|
||||
|
||||
if (0 == index)
|
||||
HAL_GPIO_0_write(value);
|
||||
else if (1 == index)
|
||||
HAL_GPIO_1_write(value);
|
||||
else if (2 == index)
|
||||
HAL_GPIO_2_write(value);
|
||||
else if (3 == index)
|
||||
HAL_GPIO_3_write(value);
|
||||
else if (4 == index)
|
||||
HAL_GPIO_4_write(value);
|
||||
else if (5 == index)
|
||||
HAL_GPIO_5_write(value);
|
||||
else if (6 == index)
|
||||
HAL_GPIO_6_write(value);
|
||||
else if (7 == index)
|
||||
HAL_GPIO_7_write(value);
|
||||
}
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _GPIO_H_
|
||||
#define _GPIO_H_
|
||||
|
||||
/*- Includes ----------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/*- Prototypes --------------------------------------------------------------*/
|
||||
void gpio_init(void);
|
||||
void gpio_configure(int index, int conf);
|
||||
int gpio_read(int index);
|
||||
void gpio_write(int index, int value);
|
||||
|
||||
#endif // _GPIO_H_
|
||||
|
|
@ -50,19 +50,19 @@
|
|||
PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \
|
||||
(void)HAL_GPIO_##name##_set; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_clr(void) \
|
||||
{ \
|
||||
PORT->Group[HAL_GPIO_PORT##port].OUTCLR.reg = (1 << pin); \
|
||||
(void)HAL_GPIO_##name##_clr; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_toggle(void) \
|
||||
{ \
|
||||
PORT->Group[HAL_GPIO_PORT##port].OUTTGL.reg = (1 << pin); \
|
||||
(void)HAL_GPIO_##name##_toggle; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_write(int value) \
|
||||
{ \
|
||||
if (value) \
|
||||
|
@ -71,42 +71,41 @@
|
|||
PORT->Group[HAL_GPIO_PORT##port].OUTCLR.reg = (1 << pin); \
|
||||
(void)HAL_GPIO_##name##_write; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_in(void) \
|
||||
{ \
|
||||
PORT->Group[HAL_GPIO_PORT##port].DIRCLR.reg = (1 << pin); \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_INEN; \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PULLEN; \
|
||||
(void)HAL_GPIO_##name##_in; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_out(void) \
|
||||
{ \
|
||||
PORT->Group[HAL_GPIO_PORT##port].DIRSET.reg = (1 << pin); \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_INEN; \
|
||||
(void)HAL_GPIO_##name##_out; \
|
||||
} \
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_pullen(int state) \
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_pullup(void) \
|
||||
{ \
|
||||
if (state) \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PULLEN; \
|
||||
else \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PULLEN; \
|
||||
(void)HAL_GPIO_##name##_pullen; \
|
||||
PORT->Group[HAL_GPIO_PORT##port].OUTSET.reg = (1 << pin); \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PULLEN; \
|
||||
(void)HAL_GPIO_##name##_pullup; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline int HAL_GPIO_##name##_read(void) \
|
||||
{ \
|
||||
return (PORT->Group[HAL_GPIO_PORT##port].IN.reg & (1 << pin)) != 0; \
|
||||
(void)HAL_GPIO_##name##_read; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline int HAL_GPIO_##name##_state(void) \
|
||||
{ \
|
||||
return (PORT->Group[HAL_GPIO_PORT##port].DIR.reg & (1 << pin)) != 0; \
|
||||
(void)HAL_GPIO_##name##_state; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_pmuxen(int mux) \
|
||||
{ \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg |= PORT_PINCFG_PMUXEN; \
|
||||
|
@ -116,7 +115,7 @@
|
|||
PORT->Group[HAL_GPIO_PORT##port].PMUX[pin>>1].bit.PMUXE = mux; \
|
||||
(void)HAL_GPIO_##name##_pmuxen; \
|
||||
} \
|
||||
\
|
||||
\
|
||||
static inline void HAL_GPIO_##name##_pmuxdis(void) \
|
||||
{ \
|
||||
PORT->Group[HAL_GPIO_PORT##port].PINCFG[pin].reg &= ~PORT_PINCFG_PMUXEN; \
|
||||
|
|
|
@ -1,231 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*- Includes ----------------------------------------------------------------*/
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "samd21.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "i2c_master.h"
|
||||
|
||||
/*- Definitions -------------------------------------------------------------*/
|
||||
HAL_GPIO_PIN(SDA, A, 8);
|
||||
HAL_GPIO_PIN(SCL, A, 9);
|
||||
#define I2C_SERCOM SERCOM2
|
||||
#define I2C_SERCOM_PMUX PORT_PMUX_PMUXE_D_Val
|
||||
#define I2C_SERCOM_GCLK_ID SERCOM2_GCLK_ID_CORE
|
||||
#define I2C_SERCOM_CLK_GEN 0
|
||||
#define I2C_SERCOM_APBCMASK PM_APBCMASK_SERCOM2
|
||||
|
||||
#define T_RISE 215e-9 // Depends on the board, actually
|
||||
|
||||
enum
|
||||
{
|
||||
I2C_TRANSFER_WRITE = 0,
|
||||
I2C_TRANSFER_READ = 1,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
I2C_PINS_SDA = (1 << 0),
|
||||
I2C_PINS_SCL = (1 << 1),
|
||||
};
|
||||
|
||||
/*- Implementations ---------------------------------------------------------*/
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
int i2c_init(int freq)
|
||||
{
|
||||
int baud = ((float)F_CPU / freq - (float)F_CPU * T_RISE - 10.0) / 2.0;
|
||||
|
||||
if (baud < 0)
|
||||
baud = 0;
|
||||
else if (baud > 255)
|
||||
baud = 255;
|
||||
|
||||
freq = (float)F_CPU / (2.0 * (5.0 + baud) + (float)F_CPU * T_RISE);
|
||||
|
||||
PM->APBCMASK.reg |= I2C_SERCOM_APBCMASK;
|
||||
|
||||
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(I2C_SERCOM_GCLK_ID) |
|
||||
GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(I2C_SERCOM_CLK_GEN);
|
||||
|
||||
I2C_SERCOM->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
|
||||
while (I2C_SERCOM->I2CM.CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST);
|
||||
|
||||
I2C_SERCOM->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
|
||||
while (I2C_SERCOM->I2CM.SYNCBUSY.reg);
|
||||
|
||||
I2C_SERCOM->I2CM.BAUD.reg = SERCOM_I2CM_BAUD_BAUD(baud);
|
||||
while (I2C_SERCOM->I2CM.SYNCBUSY.reg);
|
||||
|
||||
I2C_SERCOM->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_ENABLE |
|
||||
SERCOM_I2CM_CTRLA_MODE_I2C_MASTER |
|
||||
SERCOM_I2CM_CTRLA_SDAHOLD(3);
|
||||
while (I2C_SERCOM->I2CM.SYNCBUSY.reg);
|
||||
|
||||
I2C_SERCOM->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(1);
|
||||
|
||||
HAL_GPIO_SDA_in();
|
||||
HAL_GPIO_SDA_clr();
|
||||
HAL_GPIO_SDA_pmuxen(I2C_SERCOM_PMUX);
|
||||
|
||||
HAL_GPIO_SCL_in();
|
||||
HAL_GPIO_SCL_clr();
|
||||
HAL_GPIO_SCL_pmuxen(I2C_SERCOM_PMUX);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
bool i2c_start(int addr)
|
||||
{
|
||||
I2C_SERCOM->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
|
||||
|
||||
I2C_SERCOM->I2CM.ADDR.reg = addr;
|
||||
|
||||
while (0 == (I2C_SERCOM->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
|
||||
0 == (I2C_SERCOM->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB));
|
||||
|
||||
if (I2C_SERCOM->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK ||
|
||||
I2C_SERCOM->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR)
|
||||
{
|
||||
I2C_SERCOM->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
bool i2c_stop(void)
|
||||
{
|
||||
if ((I2C_SERCOM->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) ||
|
||||
(I2C_SERCOM->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB))
|
||||
{
|
||||
I2C_SERCOM->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
bool i2c_read_byte(uint8_t *byte, bool last)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
int flags = I2C_SERCOM->I2CM.INTFLAG.reg;
|
||||
|
||||
if (flags & SERCOM_I2CM_INTFLAG_SB)
|
||||
break;
|
||||
|
||||
if (flags & (SERCOM_I2CM_INTFLAG_MB | SERCOM_I2CM_INTFLAG_ERROR))
|
||||
return false;
|
||||
}
|
||||
|
||||
if (last)
|
||||
I2C_SERCOM->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT | SERCOM_I2CM_CTRLB_CMD(3);
|
||||
else
|
||||
I2C_SERCOM->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
|
||||
|
||||
*byte = I2C_SERCOM->I2CM.DATA.reg;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
bool i2c_write_byte(uint8_t byte)
|
||||
{
|
||||
I2C_SERCOM->I2CM.DATA.reg = byte;
|
||||
|
||||
while (1)
|
||||
{
|
||||
int flags = I2C_SERCOM->I2CM.INTFLAG.reg;
|
||||
|
||||
if (flags & SERCOM_I2CM_INTFLAG_MB)
|
||||
break;
|
||||
|
||||
if (flags & (SERCOM_I2CM_INTFLAG_SB | SERCOM_I2CM_INTFLAG_ERROR))
|
||||
return false;
|
||||
}
|
||||
|
||||
if (I2C_SERCOM->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
|
||||
{
|
||||
I2C_SERCOM->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
bool i2c_busy(int addr)
|
||||
{
|
||||
bool busy;
|
||||
|
||||
I2C_SERCOM->I2CM.ADDR.reg = addr | I2C_TRANSFER_WRITE;
|
||||
|
||||
while (0 == (I2C_SERCOM->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB));
|
||||
|
||||
busy = (0 != (I2C_SERCOM->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK));
|
||||
|
||||
I2C_SERCOM->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
|
||||
|
||||
return busy;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
void i2c_pins(int mask, int value)
|
||||
{
|
||||
if (mask & I2C_PINS_SDA)
|
||||
{
|
||||
HAL_GPIO_SDA_out();
|
||||
HAL_GPIO_SDA_write(value & I2C_PINS_SDA);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_GPIO_SDA_in();
|
||||
HAL_GPIO_SDA_clr();
|
||||
}
|
||||
|
||||
if (mask & I2C_PINS_SCL)
|
||||
{
|
||||
HAL_GPIO_SCL_out();
|
||||
HAL_GPIO_SCL_write(value & I2C_PINS_SCL);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_GPIO_SCL_in();
|
||||
HAL_GPIO_SCL_clr();
|
||||
}
|
||||
|
||||
HAL_GPIO_SDA_pmuxdis();
|
||||
HAL_GPIO_SCL_pmuxdis();
|
||||
}
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Alex Taradov <alex@taradov.com>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _I2C_MASTER_H_
|
||||
#define _I2C_MASTER_H_
|
||||
|
||||
/*- Includes ----------------------------------------------------------------*/
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/*- Prototypes --------------------------------------------------------------*/
|
||||
int i2c_init(int freq);
|
||||
bool i2c_start(int addr);
|
||||
bool i2c_stop(void);
|
||||
bool i2c_read_byte(uint8_t *byte, bool last);
|
||||
bool i2c_write_byte(uint8_t byte);
|
||||
bool i2c_busy(int addr);
|
||||
void i2c_pins(int mask, int value);
|
||||
|
||||
#endif // _I2C_MASTER_H_
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for AC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC_COMPONENT_
|
||||
#define _SAMD21_AC_COMPONENT_
|
||||
#ifndef _SAMD11_AC_COMPONENT_
|
||||
#define _SAMD11_AC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_AC Analog Comparators */
|
||||
/** \addtogroup SAMD11_AC Analog Comparators */
|
||||
/*@{*/
|
||||
|
||||
#define AC_U2205
|
||||
#define REV_AC 0x112
|
||||
#define REV_AC 0x111
|
||||
|
||||
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -79,7 +76,7 @@ typedef union {
|
|||
#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos)
|
||||
#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
|
||||
#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
|
||||
#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
|
||||
#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
|
||||
#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
|
||||
#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos)
|
||||
#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */
|
||||
|
@ -109,7 +106,7 @@ typedef union {
|
|||
#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
|
||||
#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
|
||||
#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos)
|
||||
#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
|
||||
#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
|
||||
#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
|
||||
|
@ -146,19 +143,19 @@ typedef union {
|
|||
#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
|
||||
#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
|
||||
#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos)
|
||||
#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
|
||||
#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
|
||||
#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
|
||||
#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
|
||||
#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
|
||||
#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos)
|
||||
#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
|
||||
#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
|
||||
#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
|
||||
#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
|
||||
#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
|
||||
#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
|
||||
#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
|
||||
#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos)
|
||||
#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
|
||||
#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
|
||||
#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
|
||||
|
@ -190,12 +187,12 @@ typedef union {
|
|||
#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
|
||||
#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
|
||||
#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos)
|
||||
#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
|
||||
#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
|
||||
#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
|
||||
#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
|
||||
#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
|
||||
#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos)
|
||||
#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
|
||||
#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
|
||||
#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
|
||||
|
@ -227,29 +224,29 @@ typedef union {
|
|||
#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
|
||||
#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
|
||||
#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos)
|
||||
#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
|
||||
#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
|
||||
#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
|
||||
#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
|
||||
#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
|
||||
#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos)
|
||||
#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
|
||||
#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
|
||||
#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
|
||||
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN0:1; /*!< bit: 4 Window 0 */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
|
||||
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
|
||||
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
|
||||
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
|
||||
uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint8_t WIN:1; /*!< bit: 4 Window x */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
|
||||
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint8_t WIN:1; /*!< bit: 4 Window x */
|
||||
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AC_INTFLAG_Type;
|
||||
|
@ -264,12 +261,12 @@ typedef union {
|
|||
#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
|
||||
#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
|
||||
#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos)
|
||||
#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
|
||||
#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
|
||||
#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
|
||||
#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
|
||||
#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
|
||||
#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos)
|
||||
#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
|
||||
#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
|
||||
#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
|
||||
|
@ -299,10 +296,10 @@ typedef union {
|
|||
#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
|
||||
#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
|
||||
#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos)
|
||||
#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
|
||||
#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
|
||||
#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
|
||||
#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos)
|
||||
#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
|
||||
#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
|
||||
#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */
|
||||
#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */
|
||||
#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */
|
||||
|
@ -337,7 +334,7 @@ typedef union {
|
|||
#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
|
||||
#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
|
||||
#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos)
|
||||
#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
|
||||
#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
|
||||
#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
|
||||
#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
|
||||
#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */
|
||||
|
@ -369,10 +366,10 @@ typedef union {
|
|||
#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
|
||||
#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
|
||||
#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos)
|
||||
#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
|
||||
#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
|
||||
#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
|
||||
#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos)
|
||||
#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
|
||||
#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
|
||||
#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */
|
||||
#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */
|
||||
#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */
|
||||
|
@ -400,7 +397,7 @@ typedef union {
|
|||
#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
|
||||
#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
|
||||
#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
|
||||
#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
|
||||
#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */
|
||||
#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
|
||||
#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */
|
||||
|
@ -446,14 +443,14 @@ typedef union {
|
|||
#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos)
|
||||
#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
|
||||
#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
|
||||
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
|
||||
#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */
|
||||
#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */
|
||||
#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
|
||||
#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
|
||||
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
|
||||
#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
|
||||
#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
|
||||
#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
|
||||
|
@ -464,7 +461,7 @@ typedef union {
|
|||
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
|
||||
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
|
||||
#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
|
@ -483,7 +480,7 @@ typedef union {
|
|||
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
|
||||
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
|
||||
#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
|
@ -496,7 +493,7 @@ typedef union {
|
|||
#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos)
|
||||
#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
|
||||
#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
|
||||
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
|
||||
#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
|
||||
|
@ -507,7 +504,7 @@ typedef union {
|
|||
#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
|
||||
#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
|
||||
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
|
||||
#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */
|
||||
#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
|
||||
#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
|
||||
|
@ -532,7 +529,7 @@ typedef union {
|
|||
|
||||
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
|
||||
#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos)
|
||||
#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
|
||||
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
|
||||
#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */
|
||||
|
||||
/** \brief AC hardware registers */
|
||||
|
@ -559,4 +556,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_AC_COMPONENT_ */
|
||||
#endif /* _SAMD11_AC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for ADC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_COMPONENT_
|
||||
#define _SAMD21_ADC_COMPONENT_
|
||||
#ifndef _SAMD11_ADC_COMPONENT_
|
||||
#define _SAMD11_ADC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR ADC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_ADC Analog Digital Converter */
|
||||
/** \addtogroup SAMD11_ADC Analog Digital Converter */
|
||||
/*@{*/
|
||||
|
||||
#define ADC_U2204
|
||||
|
@ -97,7 +94,7 @@ typedef union {
|
|||
|
||||
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
|
||||
#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
|
||||
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
|
||||
#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
|
||||
|
@ -129,7 +126,7 @@ typedef union {
|
|||
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
|
||||
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
|
||||
|
@ -154,7 +151,7 @@ typedef union {
|
|||
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
|
||||
#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
|
||||
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
|
||||
#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
|
||||
|
@ -173,7 +170,7 @@ typedef union {
|
|||
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
|
||||
#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
|
||||
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
|
||||
#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
|
||||
|
@ -206,7 +203,7 @@ typedef union {
|
|||
#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
|
||||
#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
|
||||
#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
|
||||
#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
|
||||
#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
|
||||
#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
|
||||
#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
|
||||
|
@ -217,7 +214,7 @@ typedef union {
|
|||
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
|
||||
#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
|
||||
#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
|
||||
#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
|
||||
|
@ -252,7 +249,7 @@ typedef union {
|
|||
|
||||
#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
|
||||
#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
|
||||
#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
|
||||
#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
|
||||
#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
|
||||
#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
|
||||
|
@ -308,7 +305,7 @@ typedef union {
|
|||
|
||||
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
|
||||
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
|
@ -361,7 +358,7 @@ typedef union {
|
|||
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
|
||||
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
|
@ -384,13 +381,13 @@ typedef union {
|
|||
#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
|
||||
#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
|
||||
#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
|
||||
#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
|
||||
#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
|
||||
#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
|
||||
#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
|
||||
#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
|
||||
#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
|
||||
|
@ -489,13 +486,13 @@ typedef union {
|
|||
|
||||
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
|
||||
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
|
||||
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
|
||||
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
|
||||
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTFLAG_Type;
|
||||
|
@ -547,7 +544,7 @@ typedef union {
|
|||
|
||||
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
|
||||
#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
|
||||
#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
|
||||
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
|
||||
#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
|
||||
|
@ -565,7 +562,7 @@ typedef union {
|
|||
|
||||
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
|
||||
#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
|
||||
#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
|
||||
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
|
||||
#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
|
||||
|
@ -583,7 +580,7 @@ typedef union {
|
|||
|
||||
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
|
||||
#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
|
||||
#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
|
||||
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
|
||||
#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
|
||||
|
||||
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
|
||||
|
@ -602,7 +599,7 @@ typedef union {
|
|||
|
||||
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
|
||||
#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
|
||||
#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
|
||||
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
|
||||
#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
|
||||
|
@ -621,7 +618,7 @@ typedef union {
|
|||
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
|
||||
#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
|
||||
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
|
||||
#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
|
||||
|
@ -641,10 +638,10 @@ typedef union {
|
|||
|
||||
#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
|
||||
#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
|
||||
#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
|
||||
#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
|
||||
#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
|
||||
#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
|
||||
#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
|
||||
#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
|
||||
#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
|
||||
|
||||
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
|
||||
|
@ -699,4 +696,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_ADC_COMPONENT_ */
|
||||
#endif /* _SAMD11_ADC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for DAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_COMPONENT_
|
||||
#define _SAMD21_DAC_COMPONENT_
|
||||
#ifndef _SAMD11_DAC_COMPONENT_
|
||||
#define _SAMD11_DAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DAC Digital Analog Converter */
|
||||
/** \addtogroup SAMD11_DAC Digital Analog Converter */
|
||||
/*@{*/
|
||||
|
||||
#define DAC_U2214
|
||||
|
@ -111,7 +108,7 @@ typedef union {
|
|||
#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos)
|
||||
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
|
||||
#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
|
||||
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
|
||||
#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */
|
||||
#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */
|
||||
#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */
|
||||
|
@ -191,12 +188,12 @@ typedef union {
|
|||
|
||||
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
__I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
__I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTFLAG_Type;
|
||||
|
@ -246,7 +243,7 @@ typedef union {
|
|||
|
||||
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
|
||||
#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos)
|
||||
#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
|
||||
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
|
||||
#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */
|
||||
|
||||
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
|
||||
|
@ -264,7 +261,7 @@ typedef union {
|
|||
|
||||
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
|
||||
#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
|
||||
#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
|
||||
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
|
||||
#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */
|
||||
|
||||
/** \brief DAC hardware registers */
|
||||
|
@ -286,4 +283,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DAC_COMPONENT_ */
|
||||
#endif /* _SAMD11_DAC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for DMAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DMAC_COMPONENT_
|
||||
#define _SAMD21_DMAC_COMPONENT_
|
||||
#ifndef _SAMD11_DMAC_COMPONENT_
|
||||
#define _SAMD11_DMAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DMAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
|
||||
/** \addtogroup SAMD11_DMAC Direct Memory Access Controller */
|
||||
/*@{*/
|
||||
|
||||
#define DMAC_U2223
|
||||
#define REV_DMAC 0x110
|
||||
#define REV_DMAC 0x100
|
||||
|
||||
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -98,7 +95,7 @@ typedef union {
|
|||
#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
|
||||
#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
|
||||
#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
|
||||
#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
|
||||
#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
|
||||
#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
|
||||
|
||||
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
|
||||
|
@ -120,7 +117,7 @@ typedef union {
|
|||
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) Byte bus access */
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) Half-word bus access */
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) Word bus access */
|
||||
|
@ -129,14 +126,14 @@ typedef union {
|
|||
#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
|
||||
#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
|
||||
#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
|
||||
#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
|
||||
#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
|
||||
#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
|
||||
#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
|
||||
#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
|
||||
#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
|
||||
#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
|
||||
#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
|
||||
#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
|
||||
|
@ -158,7 +155,7 @@ typedef union {
|
|||
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
|
||||
#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
|
||||
|
||||
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
|
||||
|
@ -176,7 +173,7 @@ typedef union {
|
|||
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
|
||||
#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
|
||||
|
||||
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
|
||||
|
@ -236,7 +233,7 @@ typedef union {
|
|||
|
||||
#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
|
||||
#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
|
||||
#define DMAC_QOSCTRL_WRBQOS(value) ((DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)))
|
||||
#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
|
||||
#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
|
||||
#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
|
||||
#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
|
||||
|
@ -247,7 +244,7 @@ typedef union {
|
|||
#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
|
||||
#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
|
||||
#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
|
||||
#define DMAC_QOSCTRL_FQOS(value) ((DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)))
|
||||
#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
|
||||
#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
|
||||
#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
|
||||
#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
|
||||
|
@ -258,7 +255,7 @@ typedef union {
|
|||
#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
|
||||
#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
|
||||
#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
|
||||
#define DMAC_QOSCTRL_DQOS(value) ((DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)))
|
||||
#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
|
||||
#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
|
||||
#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
|
||||
#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
|
||||
|
@ -279,17 +276,11 @@ typedef union {
|
|||
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
|
||||
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
|
||||
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
|
||||
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
|
||||
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
|
||||
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
|
||||
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
|
||||
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
|
||||
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t SWTRIG:6; /*!< bit: 0.. 5 Channel x Software Trigger */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DMAC_SWTRIGCTRL_Type;
|
||||
|
@ -310,38 +301,26 @@ typedef union {
|
|||
#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
|
||||
#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0x3Ful << DMAC_SWTRIGCTRL_SWTRIG_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
|
||||
#define DMAC_SWTRIGCTRL_MASK 0x0000003Ful /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
|
||||
|
||||
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
|
||||
uint32_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
uint32_t LVLPRI0:3; /*!< bit: 0.. 2 Level 0 Channel Priority Number */
|
||||
uint32_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
|
||||
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
|
||||
uint32_t :3; /*!< bit: 12..14 Reserved */
|
||||
uint32_t LVLPRI1:3; /*!< bit: 8..10 Level 1 Channel Priority Number */
|
||||
uint32_t :4; /*!< bit: 11..14 Reserved */
|
||||
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
|
||||
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
|
||||
uint32_t :3; /*!< bit: 20..22 Reserved */
|
||||
uint32_t LVLPRI2:3; /*!< bit: 16..18 Level 2 Channel Priority Number */
|
||||
uint32_t :4; /*!< bit: 19..22 Reserved */
|
||||
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
|
||||
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
|
||||
uint32_t :3; /*!< bit: 28..30 Reserved */
|
||||
uint32_t LVLPRI3:3; /*!< bit: 24..26 Level 3 Channel Priority Number */
|
||||
uint32_t :4; /*!< bit: 27..30 Reserved */
|
||||
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
|
@ -352,33 +331,33 @@ typedef union {
|
|||
#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
|
||||
|
||||
#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI0_Msk (0x7ul << DMAC_PRICTRL0_LVLPRI0_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI1_Msk (0x7ul << DMAC_PRICTRL0_LVLPRI1_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI2_Msk (0x7ul << DMAC_PRICTRL0_LVLPRI2_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI3_Msk (0x7ul << DMAC_PRICTRL0_LVLPRI3_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
|
||||
#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
|
||||
#define DMAC_PRICTRL0_MASK 0x87878787ul /**< \brief (DMAC_PRICTRL0) MASK Register */
|
||||
|
||||
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
|
||||
uint16_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint16_t ID:3; /*!< bit: 0.. 2 Channel ID */
|
||||
uint16_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
|
||||
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
|
||||
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
|
||||
|
@ -395,8 +374,8 @@ typedef union {
|
|||
#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
|
||||
|
||||
#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
|
||||
#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
|
||||
#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
|
||||
#define DMAC_INTPEND_ID_Msk (0x7ul << DMAC_INTPEND_ID_Pos)
|
||||
#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
|
||||
#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
|
||||
#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
|
||||
#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
|
||||
|
@ -409,7 +388,7 @@ typedef union {
|
|||
#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos)
|
||||
#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
|
||||
#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos)
|
||||
#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */
|
||||
#define DMAC_INTPEND_MASK 0xE707ul /**< \brief (DMAC_INTPEND) MASK Register */
|
||||
|
||||
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -421,17 +400,11 @@ typedef union {
|
|||
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
|
||||
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
|
||||
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
|
||||
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
|
||||
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
|
||||
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
|
||||
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
|
||||
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
|
||||
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t CHINT:6; /*!< bit: 0.. 5 Channel x Pending Interrupt */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DMAC_INTSTATUS_Type;
|
||||
|
@ -452,22 +425,10 @@ typedef union {
|
|||
#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
|
||||
#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
|
||||
#define DMAC_INTSTATUS_CHINT_Msk (0x3Ful << DMAC_INTSTATUS_CHINT_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
|
||||
#define DMAC_INTSTATUS_MASK 0x0000003Ful /**< \brief (DMAC_INTSTATUS) MASK Register */
|
||||
|
||||
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -479,17 +440,11 @@ typedef union {
|
|||
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
|
||||
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
|
||||
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
|
||||
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
|
||||
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
|
||||
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
|
||||
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
|
||||
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
|
||||
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t BUSYCH:6; /*!< bit: 0.. 5 Busy Channel x */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DMAC_BUSYCH_Type;
|
||||
|
@ -510,22 +465,10 @@ typedef union {
|
|||
#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
|
||||
#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
|
||||
#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
|
||||
#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
|
||||
#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
|
||||
#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
|
||||
#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
|
||||
#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
|
||||
#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
|
||||
#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
|
||||
#define DMAC_BUSYCH_BUSYCH_Msk (0x3Ful << DMAC_BUSYCH_BUSYCH_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
|
||||
#define DMAC_BUSYCH_MASK 0x0000003Ful /**< \brief (DMAC_BUSYCH) MASK Register */
|
||||
|
||||
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -537,17 +480,11 @@ typedef union {
|
|||
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
|
||||
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
|
||||
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
|
||||
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
|
||||
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
|
||||
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
|
||||
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
|
||||
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
|
||||
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
uint32_t PENDCH:6; /*!< bit: 0.. 5 Pending Channel x */
|
||||
uint32_t :26; /*!< bit: 6..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DMAC_PENDCH_Type;
|
||||
|
@ -568,22 +505,10 @@ typedef union {
|
|||
#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
|
||||
#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
|
||||
#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
|
||||
#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
|
||||
#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
|
||||
#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
|
||||
#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
|
||||
#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
|
||||
#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
|
||||
#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
|
||||
#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
|
||||
#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
|
||||
#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
|
||||
#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
|
||||
#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
|
||||
#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
|
||||
#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
|
||||
#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
|
||||
#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
|
||||
#define DMAC_PENDCH_PENDCH_Msk (0x3Ful << DMAC_PENDCH_PENDCH_Pos)
|
||||
#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
|
||||
#define DMAC_PENDCH_MASK 0x0000003Ful /**< \brief (DMAC_PENDCH) MASK Register */
|
||||
|
||||
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -620,15 +545,15 @@ typedef union {
|
|||
#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
|
||||
#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
|
||||
#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
|
||||
#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
|
||||
#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
|
||||
#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
|
||||
#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
|
||||
#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
|
||||
#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
|
||||
#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
|
||||
#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
|
||||
#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
|
||||
#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
|
||||
#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
|
||||
#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
|
||||
#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
|
||||
|
||||
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
|
||||
|
@ -646,7 +571,7 @@ typedef union {
|
|||
|
||||
#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
|
||||
#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
|
||||
#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
|
||||
#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
|
||||
#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
|
||||
|
@ -664,15 +589,15 @@ typedef union {
|
|||
|
||||
#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
|
||||
#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
|
||||
#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
|
||||
#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
|
||||
#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint8_t ID:3; /*!< bit: 0.. 2 Channel ID */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DMAC_CHID_Type;
|
||||
|
@ -682,9 +607,9 @@ typedef union {
|
|||
#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */
|
||||
|
||||
#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
|
||||
#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
|
||||
#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
|
||||
#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
|
||||
#define DMAC_CHID_ID_Msk (0x7ul << DMAC_CHID_ID_Pos)
|
||||
#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
|
||||
#define DMAC_CHID_MASK 0x07ul /**< \brief (DMAC_CHID) MASK Register */
|
||||
|
||||
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -716,8 +641,8 @@ typedef union {
|
|||
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
|
||||
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
|
||||
uint32_t :1; /*!< bit: 7 Reserved */
|
||||
uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
|
||||
uint32_t :8; /*!< bit: 14..21 Reserved */
|
||||
uint32_t TRIGSRC:5; /*!< bit: 8..12 Peripheral Trigger Source */
|
||||
uint32_t :9; /*!< bit: 13..21 Reserved */
|
||||
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
|
||||
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
|
||||
uint32_t :6; /*!< bit: 26..31 Reserved */
|
||||
|
@ -731,7 +656,7 @@ typedef union {
|
|||
|
||||
#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
|
||||
#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
|
||||
#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
|
||||
#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
|
||||
#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
|
||||
#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
|
||||
#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
|
||||
|
@ -752,23 +677,15 @@ typedef union {
|
|||
#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
|
||||
#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
|
||||
#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
|
||||
#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
|
||||
#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
|
||||
#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
|
||||
#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
|
||||
#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
|
||||
#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
|
||||
#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
|
||||
#define DMAC_CHCTRLB_TRIGSRC_Msk (0x1Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
|
||||
#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
|
||||
#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
|
||||
#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
|
||||
#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
|
||||
#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
|
||||
#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
|
||||
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
|
||||
|
@ -777,14 +694,14 @@ typedef union {
|
|||
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
|
||||
#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
|
||||
#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
|
||||
#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
|
||||
#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
|
||||
#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
|
||||
#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
|
||||
#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
|
||||
#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
|
||||
#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
|
||||
#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
|
||||
#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
|
||||
#define DMAC_CHCTRLB_MASK 0x03C01F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
|
||||
|
||||
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -836,12 +753,12 @@ typedef union {
|
|||
|
||||
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t TERR:1; /*!< bit: 0 Transfer Error */
|
||||
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
|
||||
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
__I uint8_t TERR:1; /*!< bit: 0 Transfer Error */
|
||||
__I uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
|
||||
__I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DMAC_CHINTFLAG_Type;
|
||||
|
@ -906,7 +823,7 @@ typedef union {
|
|||
#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
|
||||
#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
|
||||
#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
|
||||
#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
|
||||
#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
|
||||
#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
|
||||
#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
|
||||
#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
|
||||
|
@ -915,7 +832,7 @@ typedef union {
|
|||
#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
||||
#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
|
||||
#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
|
||||
#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
|
||||
#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
|
||||
#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) No action */
|
||||
#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
|
||||
#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
|
||||
|
@ -926,7 +843,7 @@ typedef union {
|
|||
#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
||||
#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
|
||||
#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
|
||||
#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
|
||||
#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
|
||||
#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit access */
|
||||
#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit access */
|
||||
#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit access */
|
||||
|
@ -945,7 +862,7 @@ typedef union {
|
|||
#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
|
||||
#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
|
||||
#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
|
||||
#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
|
||||
#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
|
||||
#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */
|
||||
|
@ -978,7 +895,7 @@ typedef union {
|
|||
|
||||
#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
|
||||
#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
|
||||
#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
|
||||
#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
|
||||
#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
|
||||
|
||||
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
|
||||
|
@ -995,7 +912,7 @@ typedef union {
|
|||
|
||||
#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
|
||||
#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
|
||||
#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
|
||||
#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
|
||||
#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
|
||||
|
@ -1012,7 +929,7 @@ typedef union {
|
|||
|
||||
#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
|
||||
#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
|
||||
#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
|
||||
#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
|
||||
#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
|
||||
|
@ -1029,7 +946,7 @@ typedef union {
|
|||
|
||||
#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
|
||||
#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
|
||||
#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
|
||||
#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
|
||||
#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
|
||||
|
||||
/** \brief DMAC APB hardware registers */
|
||||
|
@ -1085,4 +1002,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DMAC_COMPONENT_ */
|
||||
#endif /* _SAMD11_DMAC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for DSU
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_COMPONENT_
|
||||
#define _SAMD21_DSU_COMPONENT_
|
||||
#ifndef _SAMD11_DSU_COMPONENT_
|
||||
#define _SAMD11_DSU_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DSU */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DSU Device Service Unit */
|
||||
/** \addtogroup SAMD11_DSU Device Service Unit */
|
||||
/*@{*/
|
||||
|
||||
#define DSU_U2209
|
||||
#define REV_DSU 0x202
|
||||
#define REV_DSU 0x211
|
||||
|
||||
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -62,10 +59,12 @@ typedef union {
|
|||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :1; /*!< bit: 1 Reserved */
|
||||
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
|
||||
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
|
||||
uint8_t CE:1; /*!< bit: 4 Chip Erase */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */
|
||||
uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */
|
||||
uint8_t CE:1; /*!< bit: 4 Chip-Erase */
|
||||
uint8_t :1; /*!< bit: 5 Reserved */
|
||||
uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */
|
||||
uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DSU_CTRL_Type;
|
||||
|
@ -76,13 +75,17 @@ typedef union {
|
|||
|
||||
#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
|
||||
#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
|
||||
#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
|
||||
#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
|
||||
#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
|
||||
#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
|
||||
#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */
|
||||
#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
|
||||
#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
|
||||
#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */
|
||||
#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
|
||||
#define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
|
||||
#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */
|
||||
#define DSU_CTRL_ARR (0x1ul << DSU_CTRL_ARR_Pos)
|
||||
#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */
|
||||
#define DSU_CTRL_SMSA (0x1ul << DSU_CTRL_SMSA_Pos)
|
||||
#define DSU_CTRL_MASK 0xDDul /**< \brief (DSU_CTRL) MASK Register */
|
||||
|
||||
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -135,7 +138,7 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
|
||||
#define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
|
||||
#define DSU_STATUSB_RESETVALUE 0x00ul /**< \brief (DSU_STATUSB reset_value) Status B */
|
||||
|
||||
#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
|
||||
#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
|
||||
|
@ -147,7 +150,7 @@ typedef union {
|
|||
#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
|
||||
#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
|
||||
#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
|
||||
#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
|
||||
#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
|
||||
#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
|
||||
#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
|
||||
#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
|
||||
|
@ -156,7 +159,7 @@ typedef union {
|
|||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */
|
||||
uint32_t ADDR:30; /*!< bit: 2..31 Address */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
|
@ -166,10 +169,13 @@ typedef union {
|
|||
#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
|
||||
#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
|
||||
|
||||
#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */
|
||||
#define DSU_ADDR_AMOD_Msk (0x3ul << DSU_ADDR_AMOD_Pos)
|
||||
#define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
|
||||
#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
|
||||
#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
|
||||
#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
|
||||
#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
|
||||
#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
|
||||
#define DSU_ADDR_MASK 0xFFFFFFFFul /**< \brief (DSU_ADDR) MASK Register */
|
||||
|
||||
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -187,7 +193,7 @@ typedef union {
|
|||
|
||||
#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
|
||||
#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
|
||||
#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
|
||||
#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
|
||||
#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
|
||||
|
||||
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
|
||||
|
@ -205,7 +211,7 @@ typedef union {
|
|||
|
||||
#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
|
||||
#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
|
||||
#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
|
||||
#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
|
||||
#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
|
||||
|
||||
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
|
||||
|
@ -223,7 +229,7 @@ typedef union {
|
|||
|
||||
#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
|
||||
#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
|
||||
#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
|
||||
#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
|
||||
#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
|
||||
|
||||
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
|
||||
|
@ -231,11 +237,11 @@ typedef union {
|
|||
typedef union {
|
||||
struct {
|
||||
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
|
||||
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
|
||||
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
|
||||
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
|
||||
uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */
|
||||
uint32_t DIE:4; /*!< bit: 12..15 Die Number */
|
||||
uint32_t SERIES:6; /*!< bit: 16..21 Series */
|
||||
uint32_t :1; /*!< bit: 22 Reserved */
|
||||
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
|
||||
uint32_t FAMILY:5; /*!< bit: 23..27 Family */
|
||||
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
|
@ -246,24 +252,58 @@ typedef union {
|
|||
|
||||
#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
|
||||
#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
|
||||
#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
|
||||
#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
|
||||
#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
|
||||
#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */
|
||||
#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
|
||||
#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
|
||||
#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
|
||||
#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
|
||||
#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */
|
||||
#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
|
||||
#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
|
||||
#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
|
||||
#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
|
||||
#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */
|
||||
#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
|
||||
#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
|
||||
#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
|
||||
#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
|
||||
#define DSU_DID_SERIES_0_Val 0x0ul /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
|
||||
#define DSU_DID_SERIES_1_Val 0x1ul /**< \brief (DSU_DID) Cortex-M0+ processor, USB */
|
||||
#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos)
|
||||
#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos)
|
||||
#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */
|
||||
#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
|
||||
#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
|
||||
#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
|
||||
#define DSU_DID_FAMILY_0_Val 0x0ul /**< \brief (DSU_DID) General purpose microcontroller */
|
||||
#define DSU_DID_FAMILY_1_Val 0x1ul /**< \brief (DSU_DID) PicoPower */
|
||||
#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos)
|
||||
#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos)
|
||||
#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
|
||||
#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
|
||||
#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
|
||||
#define DSU_DID_PROCESSOR_0_Val 0x0ul /**< \brief (DSU_DID) Cortex-M0 */
|
||||
#define DSU_DID_PROCESSOR_1_Val 0x1ul /**< \brief (DSU_DID) Cortex-M0+ */
|
||||
#define DSU_DID_PROCESSOR_2_Val 0x2ul /**< \brief (DSU_DID) Cortex-M3 */
|
||||
#define DSU_DID_PROCESSOR_3_Val 0x3ul /**< \brief (DSU_DID) Cortex-M4 */
|
||||
#define DSU_DID_PROCESSOR_0 (DSU_DID_PROCESSOR_0_Val << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_PROCESSOR_1 (DSU_DID_PROCESSOR_1_Val << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_PROCESSOR_2 (DSU_DID_PROCESSOR_2_Val << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_PROCESSOR_3 (DSU_DID_PROCESSOR_3_Val << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
|
||||
|
||||
/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_DCFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */
|
||||
#define DSU_DCFG_RESETVALUE 0x00000000ul /**< \brief (DSU_DCFG reset_value) Device Configuration */
|
||||
|
||||
#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */
|
||||
#define DSU_DCFG_DCFG_Msk (0xFFFFFFFFul << DSU_DCFG_DCFG_Pos)
|
||||
#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
|
||||
#define DSU_DCFG_MASK 0xFFFFFFFFul /**< \brief (DSU_DCFG) MASK Register */
|
||||
|
||||
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
|
@ -278,7 +318,6 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
|
||||
#define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
|
||||
|
||||
#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
|
||||
#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
|
||||
|
@ -286,7 +325,7 @@ typedef union {
|
|||
#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
|
||||
#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
|
||||
#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
|
||||
#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
|
||||
#define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
|
||||
#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
|
||||
|
||||
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
|
||||
|
@ -304,7 +343,7 @@ typedef union {
|
|||
|
||||
#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
|
||||
#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
|
||||
#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
|
||||
#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
|
||||
#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
|
||||
|
||||
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
|
||||
|
@ -330,7 +369,7 @@ typedef union {
|
|||
typedef union {
|
||||
struct {
|
||||
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
|
||||
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
|
||||
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
|
@ -342,12 +381,42 @@ typedef union {
|
|||
|
||||
#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
|
||||
#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
|
||||
#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
|
||||
#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
|
||||
#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
|
||||
#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */
|
||||
#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
|
||||
#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
|
||||
#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
|
||||
#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
|
||||
|
||||
/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID5_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
|
||||
#define DSU_PID5_MASK 0x00000000ul /**< \brief (DSU_PID5) MASK Register */
|
||||
|
||||
/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID6_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
|
||||
#define DSU_PID6_MASK 0x00000000ul /**< \brief (DSU_PID6) MASK Register */
|
||||
|
||||
/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} DSU_PID7_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
|
||||
#define DSU_PID7_MASK 0x00000000ul /**< \brief (DSU_PID7) MASK Register */
|
||||
|
||||
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
|
@ -360,11 +429,11 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
|
||||
#define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
|
||||
#define DSU_PID0_RESETVALUE 0x00000000ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
|
||||
|
||||
#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
|
||||
#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
|
||||
#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
|
||||
#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
|
||||
#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
|
||||
|
||||
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
|
||||
|
@ -384,10 +453,10 @@ typedef union {
|
|||
|
||||
#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
|
||||
#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
|
||||
#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
|
||||
#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
|
||||
#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
|
||||
#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
|
||||
#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
|
||||
#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
|
||||
#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
|
||||
|
||||
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
|
||||
|
@ -408,12 +477,12 @@ typedef union {
|
|||
|
||||
#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
|
||||
#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
|
||||
#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
|
||||
#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
|
||||
#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
|
||||
#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
|
||||
#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
|
||||
#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
|
||||
#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
|
||||
#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
|
||||
#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
|
||||
|
||||
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
|
||||
|
@ -433,10 +502,10 @@ typedef union {
|
|||
|
||||
#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
|
||||
#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
|
||||
#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
|
||||
#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
|
||||
#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
|
||||
#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
|
||||
#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
|
||||
#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
|
||||
#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
|
||||
|
||||
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
|
||||
|
@ -451,11 +520,11 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
|
||||
#define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
|
||||
#define DSU_CID0_RESETVALUE 0x00000000ul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
|
||||
|
||||
#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
|
||||
#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
|
||||
#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
|
||||
#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
|
||||
#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
|
||||
|
||||
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
|
||||
|
@ -471,14 +540,14 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
|
||||
#define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
|
||||
#define DSU_CID1_RESETVALUE 0x00000000ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
|
||||
|
||||
#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
|
||||
#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
|
||||
#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
|
||||
#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
|
||||
#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
|
||||
#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
|
||||
#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
|
||||
#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
|
||||
#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
|
||||
|
||||
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
|
||||
|
@ -493,11 +562,11 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
|
||||
#define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
|
||||
#define DSU_CID2_RESETVALUE 0x00000000ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
|
||||
|
||||
#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
|
||||
#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
|
||||
#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
|
||||
#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
|
||||
#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
|
||||
|
||||
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
|
||||
|
@ -512,11 +581,11 @@ typedef union {
|
|||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
|
||||
#define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
|
||||
#define DSU_CID3_RESETVALUE 0x00000000ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
|
||||
|
||||
#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
|
||||
#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
|
||||
#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
|
||||
#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
|
||||
#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
|
||||
|
||||
/** \brief DSU hardware registers */
|
||||
|
@ -531,13 +600,17 @@ typedef struct {
|
|||
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
|
||||
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
|
||||
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
|
||||
RoReg8 Reserved2[0xFE4];
|
||||
RoReg8 Reserved2[0xD4];
|
||||
__IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
|
||||
RoReg8 Reserved3[0xF08];
|
||||
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
|
||||
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
|
||||
RoReg8 Reserved3[0xFC0];
|
||||
RoReg8 Reserved4[0xFC0];
|
||||
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
|
||||
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
|
||||
RoReg8 Reserved4[0xC];
|
||||
__I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */
|
||||
__I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */
|
||||
__I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */
|
||||
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
|
||||
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
|
||||
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
|
||||
|
@ -551,4 +624,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DSU_COMPONENT_ */
|
||||
#endif /* _SAMD11_DSU_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for EIC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_COMPONENT_
|
||||
#define _SAMD21_EIC_COMPONENT_
|
||||
#ifndef _SAMD11_EIC_COMPONENT_
|
||||
#define _SAMD11_EIC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EIC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_EIC External Interrupt Controller */
|
||||
/** \addtogroup SAMD11_EIC External Interrupt Controller */
|
||||
/*@{*/
|
||||
|
||||
#define EIC_U2217
|
||||
|
@ -112,7 +109,7 @@ typedef union {
|
|||
|
||||
#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
|
||||
#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
|
||||
#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
|
||||
#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
|
||||
#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
|
||||
#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
|
||||
|
@ -159,19 +156,11 @@ typedef union {
|
|||
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
|
||||
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
|
||||
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
|
||||
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
|
||||
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
|
||||
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
|
||||
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
|
||||
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
|
||||
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
|
||||
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
|
||||
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t EXTINTEO:8; /*!< bit: 0.. 7 External Interrupt x Event Output Enable */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_EVCTRL_Type;
|
||||
|
@ -196,26 +185,10 @@ typedef union {
|
|||
#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
|
||||
#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
|
||||
#define EIC_EVCTRL_EXTINTEO_Msk (0xFFul << EIC_EVCTRL_EXTINTEO_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
|
||||
#define EIC_EVCTRL_MASK 0x000000FFul /**< \brief (EIC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -229,19 +202,11 @@ typedef union {
|
|||
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
|
||||
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
|
||||
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
|
||||
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
|
||||
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
|
||||
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
|
||||
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
|
||||
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
|
||||
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
|
||||
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
|
||||
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t EXTINT:8; /*!< bit: 0.. 7 External Interrupt x Enable */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTENCLR_Type;
|
||||
|
@ -266,26 +231,10 @@ typedef union {
|
|||
#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
|
||||
#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
|
||||
#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
|
||||
#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
|
||||
#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
|
||||
#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
|
||||
#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
|
||||
#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
|
||||
#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
|
||||
#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
|
||||
#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
|
||||
#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
|
||||
#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
|
||||
#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
|
||||
#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
|
||||
#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
|
||||
#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
|
||||
#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
|
||||
#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
|
||||
#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
|
||||
#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
|
||||
#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
|
||||
#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
|
||||
#define EIC_INTENCLR_EXTINT_Msk (0xFFul << EIC_INTENCLR_EXTINT_Pos)
|
||||
#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
|
||||
#define EIC_INTENCLR_MASK 0x000000FFul /**< \brief (EIC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -299,19 +248,11 @@ typedef union {
|
|||
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
|
||||
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
|
||||
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
|
||||
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
|
||||
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
|
||||
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
|
||||
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
|
||||
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
|
||||
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
|
||||
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
|
||||
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t EXTINT:8; /*!< bit: 0.. 7 External Interrupt x Enable */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTENSET_Type;
|
||||
|
@ -336,52 +277,28 @@ typedef union {
|
|||
#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
|
||||
#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
|
||||
#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
|
||||
#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
|
||||
#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
|
||||
#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
|
||||
#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
|
||||
#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
|
||||
#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
|
||||
#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
|
||||
#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
|
||||
#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
|
||||
#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
|
||||
#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
|
||||
#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
|
||||
#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
|
||||
#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
|
||||
#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
|
||||
#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
|
||||
#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
|
||||
#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
|
||||
#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
|
||||
#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
|
||||
#define EIC_INTENSET_EXTINT_Msk (0xFFul << EIC_INTENSET_EXTINT_Pos)
|
||||
#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
|
||||
#define EIC_INTENSET_MASK 0x000000FFul /**< \brief (EIC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
|
||||
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
|
||||
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
|
||||
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
|
||||
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
|
||||
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
|
||||
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
|
||||
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
|
||||
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
|
||||
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
|
||||
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
|
||||
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
|
||||
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
|
||||
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
|
||||
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
|
||||
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
__I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
|
||||
__I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
|
||||
__I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
|
||||
__I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
|
||||
__I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
|
||||
__I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
|
||||
__I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
|
||||
__I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
|
||||
__I uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
__I uint32_t EXTINT:8; /*!< bit: 0.. 7 External Interrupt x */
|
||||
__I uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTFLAG_Type;
|
||||
|
@ -406,26 +323,10 @@ typedef union {
|
|||
#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
|
||||
#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
|
||||
#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
|
||||
#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
|
||||
#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
|
||||
#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
|
||||
#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
|
||||
#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
|
||||
#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
|
||||
#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
|
||||
#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
|
||||
#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
|
||||
#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
|
||||
#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
|
||||
#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
|
||||
#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
|
||||
#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
|
||||
#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
|
||||
#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
|
||||
#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
|
||||
#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
|
||||
#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
|
||||
#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
|
||||
#define EIC_INTFLAG_EXTINT_Msk (0xFFul << EIC_INTFLAG_EXTINT_Pos)
|
||||
#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
|
||||
#define EIC_INTFLAG_MASK 0x000000FFul /**< \brief (EIC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -439,19 +340,11 @@ typedef union {
|
|||
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
|
||||
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
|
||||
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
|
||||
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
|
||||
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
|
||||
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
|
||||
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
|
||||
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
|
||||
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
|
||||
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
|
||||
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
uint32_t WAKEUPEN:8; /*!< bit: 0.. 7 External Interrupt x Wake-up Enable */
|
||||
uint32_t :24; /*!< bit: 8..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_WAKEUP_Type;
|
||||
|
@ -476,26 +369,10 @@ typedef union {
|
|||
#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
|
||||
#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
|
||||
#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFul << EIC_WAKEUP_WAKEUPEN_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
|
||||
#define EIC_WAKEUP_MASK 0x000000FFul /**< \brief (EIC_WAKEUP) MASK Register */
|
||||
|
||||
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -527,7 +404,7 @@ typedef union {
|
|||
|
||||
#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
|
||||
#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
|
||||
#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
|
||||
#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
|
||||
#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
|
||||
|
@ -544,7 +421,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
|
||||
#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
|
||||
#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
|
||||
#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
|
||||
#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -561,7 +438,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
|
||||
#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
|
||||
#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
|
||||
#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
|
||||
#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -578,7 +455,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
|
||||
#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
|
||||
#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
|
||||
#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
|
||||
#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -595,7 +472,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
|
||||
#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
|
||||
#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
|
||||
#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
|
||||
#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -612,7 +489,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
|
||||
#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
|
||||
#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
|
||||
#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
|
||||
#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -629,7 +506,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
|
||||
#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
|
||||
#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
|
||||
#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
|
||||
#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -646,7 +523,7 @@ typedef union {
|
|||
#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
|
||||
#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
|
||||
#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
|
||||
#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
|
||||
#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
@ -675,10 +552,10 @@ typedef struct {
|
|||
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
|
||||
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
|
||||
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
|
||||
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
|
||||
__IO EIC_CONFIG_Type CONFIG[1]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
|
||||
} Eic;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_EIC_COMPONENT_ */
|
||||
#endif /* _SAMD11_EIC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_COMPONENT_
|
||||
#define _SAMD21_EVSYS_COMPONENT_
|
||||
#ifndef _SAMD11_EVSYS_COMPONENT_
|
||||
#define _SAMD11_EVSYS_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR EVSYS */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_EVSYS Event System Interface */
|
||||
/** \addtogroup SAMD11_EVSYS Event System Interface */
|
||||
/*@{*/
|
||||
|
||||
#define EVSYS_U2208
|
||||
|
@ -82,12 +79,12 @@ typedef union {
|
|||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t CHANNEL:3; /*!< bit: 0.. 2 Channel Selection */
|
||||
uint32_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
|
||||
uint32_t :7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t EVGEN:6; /*!< bit: 16..21 Event Generator Selection */
|
||||
uint32_t :2; /*!< bit: 22..23 Reserved */
|
||||
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
|
||||
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
|
@ -100,16 +97,16 @@ typedef union {
|
|||
#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
|
||||
|
||||
#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
|
||||
#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
|
||||
#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
|
||||
#define EVSYS_CHANNEL_CHANNEL_Msk (0x7ul << EVSYS_CHANNEL_CHANNEL_Pos)
|
||||
#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
|
||||
#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
|
||||
#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
|
||||
#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
|
||||
#define EVSYS_CHANNEL_EVGEN_Msk (0x3Ful << EVSYS_CHANNEL_EVGEN_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
|
||||
#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
|
||||
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
|
||||
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
|
||||
|
@ -118,7 +115,7 @@ typedef union {
|
|||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
|
||||
#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
|
||||
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
|
||||
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
|
@ -127,7 +124,7 @@ typedef union {
|
|||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
|
||||
#define EVSYS_CHANNEL_MASK 0x0F3F0107ul /**< \brief (EVSYS_CHANNEL) MASK Register */
|
||||
|
||||
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -135,8 +132,8 @@ typedef union {
|
|||
struct {
|
||||
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
|
||||
uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
|
||||
uint16_t :3; /*!< bit: 13..15 Reserved */
|
||||
uint16_t CHANNEL:4; /*!< bit: 8..11 Channel Event Selection */
|
||||
uint16_t :4; /*!< bit: 12..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} EVSYS_USER_Type;
|
||||
|
@ -147,13 +144,13 @@ typedef union {
|
|||
|
||||
#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
|
||||
#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
|
||||
#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
|
||||
#define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
|
||||
#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
|
||||
#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
|
||||
#define EVSYS_USER_CHANNEL_Msk (0xFul << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
|
||||
#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
|
||||
#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
|
||||
#define EVSYS_USER_MASK 0x0F1Ful /**< \brief (EVSYS_USER) MASK Register */
|
||||
|
||||
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -165,41 +162,27 @@ typedef union {
|
|||
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
|
||||
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
|
||||
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
|
||||
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
|
||||
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
|
||||
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
|
||||
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
|
||||
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
|
||||
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
|
||||
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
|
||||
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
|
||||
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
|
||||
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
|
||||
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
|
||||
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
|
||||
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
|
||||
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
|
||||
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
|
||||
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
|
||||
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
|
||||
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
uint32_t USRRDY:6; /*!< bit: 0.. 5 Channel x User Ready */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t CHBUSY:6; /*!< bit: 8..13 Channel x Busy */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_CHSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
|
||||
#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
|
||||
#define EVSYS_CHSTATUS_RESETVALUE 0x0000003Ful /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
|
||||
|
||||
#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
|
||||
|
@ -213,13 +196,9 @@ typedef union {
|
|||
#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
|
||||
#define EVSYS_CHSTATUS_USRRDY_Msk (0x3Ful << EVSYS_CHSTATUS_USRRDY_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
|
||||
|
@ -232,36 +211,10 @@ typedef union {
|
|||
#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
|
||||
#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
|
||||
#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
|
||||
#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Msk (0x3Ful << EVSYS_CHSTATUS_CHBUSY_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
|
||||
#define EVSYS_CHSTATUS_MASK 0x00003F3Ful /**< \brief (EVSYS_CHSTATUS) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -273,34 +226,20 @@ typedef union {
|
|||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
uint32_t OVR:6; /*!< bit: 0.. 5 Channel x Overrun Interrupt Enable */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t EVD:6; /*!< bit: 8..13 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTENCLR_Type;
|
||||
|
@ -321,13 +260,9 @@ typedef union {
|
|||
#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
|
||||
#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
|
||||
#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
|
||||
#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
|
||||
#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
|
||||
#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
|
||||
#define EVSYS_INTENCLR_OVR_Msk (0x3Ful << EVSYS_INTENCLR_OVR_Pos)
|
||||
#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
|
||||
#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
|
||||
#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
|
||||
|
@ -340,36 +275,10 @@ typedef union {
|
|||
#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
|
||||
#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
|
||||
#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
|
||||
#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
|
||||
#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
|
||||
#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
|
||||
#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
|
||||
#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
|
||||
#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
|
||||
#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
|
||||
#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
|
||||
#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
|
||||
#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
|
||||
#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
|
||||
#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
|
||||
#define EVSYS_INTENCLR_EVD_Msk (0x3Ful << EVSYS_INTENCLR_EVD_Pos)
|
||||
#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
|
||||
#define EVSYS_INTENCLR_MASK 0x00003F3Ful /**< \brief (EVSYS_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -381,34 +290,20 @@ typedef union {
|
|||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
uint32_t OVR:6; /*!< bit: 0.. 5 Channel x Overrun Interrupt Enable */
|
||||
uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint32_t EVD:6; /*!< bit: 8..13 Channel x Event Detection Interrupt Enable */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTENSET_Type;
|
||||
|
@ -429,13 +324,9 @@ typedef union {
|
|||
#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
|
||||
#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
|
||||
#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
|
||||
#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
|
||||
#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
|
||||
#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
|
||||
#define EVSYS_INTENSET_OVR_Msk (0x3Ful << EVSYS_INTENSET_OVR_Pos)
|
||||
#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
|
||||
#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
|
||||
#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
|
||||
|
@ -448,75 +339,35 @@ typedef union {
|
|||
#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
|
||||
#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
|
||||
#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
|
||||
#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
|
||||
#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
|
||||
#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
|
||||
#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
|
||||
#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
|
||||
#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
|
||||
#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
|
||||
#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
|
||||
#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
|
||||
#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
|
||||
#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
|
||||
#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
|
||||
#define EVSYS_INTENSET_EVD_Msk (0x3Ful << EVSYS_INTENSET_EVD_Pos)
|
||||
#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
|
||||
#define EVSYS_INTENSET_MASK 0x00003F3Ful /**< \brief (EVSYS_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
||||
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
||||
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
||||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
||||
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
||||
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
||||
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
||||
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
||||
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
||||
__I uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
||||
__I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
||||
__I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
||||
__I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
||||
__I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
||||
__I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
|
||||
__I uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
__I uint32_t OVR:6; /*!< bit: 0.. 5 Channel x Overrun */
|
||||
__I uint32_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint32_t EVD:6; /*!< bit: 8..13 Channel x Event Detection */
|
||||
__I uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTFLAG_Type;
|
||||
|
@ -537,13 +388,9 @@ typedef union {
|
|||
#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
|
||||
#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
|
||||
#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
|
||||
#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
|
||||
#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
|
||||
#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
|
||||
#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
|
||||
#define EVSYS_INTFLAG_OVR_Msk (0x3Ful << EVSYS_INTFLAG_OVR_Pos)
|
||||
#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
|
||||
#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
|
||||
#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
|
||||
|
@ -556,36 +403,10 @@ typedef union {
|
|||
#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
|
||||
#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
|
||||
#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
|
||||
#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
|
||||
#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
|
||||
#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
|
||||
#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
|
||||
#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
|
||||
#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
|
||||
#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
|
||||
#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
|
||||
#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
|
||||
#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
|
||||
#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
|
||||
#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
|
||||
#define EVSYS_INTFLAG_EVD_Msk (0x3Ful << EVSYS_INTFLAG_EVD_Pos)
|
||||
#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
|
||||
#define EVSYS_INTFLAG_MASK 0x00003F3Ful /**< \brief (EVSYS_INTFLAG) MASK Register */
|
||||
|
||||
/** \brief EVSYS hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -604,4 +425,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_EVSYS_COMPONENT_ */
|
||||
#endif /* _SAMD11_EVSYS_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for GCLK
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_COMPONENT_
|
||||
#define _SAMD21_GCLK_COMPONENT_
|
||||
#ifndef _SAMD11_GCLK_COMPONENT_
|
||||
#define _SAMD11_GCLK_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR GCLK */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_GCLK Generic Clock Generator */
|
||||
/** \addtogroup SAMD11_GCLK Generic Clock Generator */
|
||||
/*@{*/
|
||||
|
||||
#define GCLK_U2102
|
||||
|
@ -112,7 +109,7 @@ typedef union {
|
|||
|
||||
#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
|
||||
#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
|
||||
#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
|
||||
#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */
|
||||
|
@ -126,30 +123,17 @@ typedef union {
|
|||
#define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
|
||||
#define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */
|
||||
#define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */
|
||||
#define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */
|
||||
#define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */
|
||||
#define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0xDul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0xEul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0xFul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x10ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
|
||||
#define GCLK_CLKCTRL_ID_TCC0_Val 0x11ul /**< \brief (GCLK_CLKCTRL) TCC0 */
|
||||
#define GCLK_CLKCTRL_ID_TC1_TC2_Val 0x12ul /**< \brief (GCLK_CLKCTRL) TC1_TC2 */
|
||||
#define GCLK_CLKCTRL_ID_ADC_Val 0x13ul /**< \brief (GCLK_CLKCTRL) ADC */
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x14ul /**< \brief (GCLK_CLKCTRL) AC_DIG */
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x15ul /**< \brief (GCLK_CLKCTRL) AC_ANA */
|
||||
#define GCLK_CLKCTRL_ID_DAC_Val 0x16ul /**< \brief (GCLK_CLKCTRL) DAC */
|
||||
#define GCLK_CLKCTRL_ID_PTC_Val 0x17ul /**< \brief (GCLK_CLKCTRL) PTC */
|
||||
#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
|
@ -163,33 +147,20 @@ typedef union {
|
|||
#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC0 (GCLK_CLKCTRL_ID_TCC0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC1_TC2 (GCLK_CLKCTRL_ID_TC1_TC2_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
|
||||
#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
|
||||
#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
|
||||
|
@ -237,10 +208,10 @@ typedef union {
|
|||
|
||||
#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
|
||||
#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos)
|
||||
#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
|
||||
#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
|
||||
#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
|
||||
#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
|
||||
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
|
||||
#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
|
||||
|
@ -291,10 +262,10 @@ typedef union {
|
|||
|
||||
#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
|
||||
#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos)
|
||||
#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
|
||||
#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
|
||||
#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
|
||||
#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos)
|
||||
#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
|
||||
#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
|
||||
#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
|
||||
|
||||
/** \brief GCLK hardware registers */
|
||||
|
@ -310,4 +281,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_GCLK_COMPONENT_ */
|
||||
#endif /* _SAMD11_GCLK_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for HMATRIXB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_HMATRIXB_COMPONENT_
|
||||
#define _SAMD21_HMATRIXB_COMPONENT_
|
||||
#ifndef _SAMD11_HMATRIXB_COMPONENT_
|
||||
#define _SAMD11_HMATRIXB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR HMATRIXB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
|
||||
/** \addtogroup SAMD11_HMATRIXB HSB Matrix */
|
||||
/*@{*/
|
||||
|
||||
#define HMATRIXB_I7638
|
||||
|
@ -59,6 +56,16 @@
|
|||
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t M0PR:4; /*!< bit: 0.. 3 Master 0 Priority */
|
||||
uint32_t M1PR:4; /*!< bit: 4.. 7 Master 1 Priority */
|
||||
uint32_t M2PR:4; /*!< bit: 8..11 Master 2 Priority */
|
||||
uint32_t M3PR:4; /*!< bit: 12..15 Master 3 Priority */
|
||||
uint32_t M4PR:4; /*!< bit: 16..19 Master 4 Priority */
|
||||
uint32_t M5PR:4; /*!< bit: 20..23 Master 5 Priority */
|
||||
uint32_t M6PR:4; /*!< bit: 24..27 Master 6 Priority */
|
||||
uint32_t M7PR:4; /*!< bit: 28..31 Master 7 Priority */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_PRAS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
@ -66,11 +73,45 @@ typedef union {
|
|||
#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
|
||||
#define HMATRIXB_PRAS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
|
||||
|
||||
#define HMATRIXB_PRAS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
|
||||
#define HMATRIXB_PRAS_M0PR_Pos 0 /**< \brief (HMATRIXB_PRAS) Master 0 Priority */
|
||||
#define HMATRIXB_PRAS_M0PR_Msk (0xFul << HMATRIXB_PRAS_M0PR_Pos)
|
||||
#define HMATRIXB_PRAS_M0PR(value) (HMATRIXB_PRAS_M0PR_Msk & ((value) << HMATRIXB_PRAS_M0PR_Pos))
|
||||
#define HMATRIXB_PRAS_M1PR_Pos 4 /**< \brief (HMATRIXB_PRAS) Master 1 Priority */
|
||||
#define HMATRIXB_PRAS_M1PR_Msk (0xFul << HMATRIXB_PRAS_M1PR_Pos)
|
||||
#define HMATRIXB_PRAS_M1PR(value) (HMATRIXB_PRAS_M1PR_Msk & ((value) << HMATRIXB_PRAS_M1PR_Pos))
|
||||
#define HMATRIXB_PRAS_M2PR_Pos 8 /**< \brief (HMATRIXB_PRAS) Master 2 Priority */
|
||||
#define HMATRIXB_PRAS_M2PR_Msk (0xFul << HMATRIXB_PRAS_M2PR_Pos)
|
||||
#define HMATRIXB_PRAS_M2PR(value) (HMATRIXB_PRAS_M2PR_Msk & ((value) << HMATRIXB_PRAS_M2PR_Pos))
|
||||
#define HMATRIXB_PRAS_M3PR_Pos 12 /**< \brief (HMATRIXB_PRAS) Master 3 Priority */
|
||||
#define HMATRIXB_PRAS_M3PR_Msk (0xFul << HMATRIXB_PRAS_M3PR_Pos)
|
||||
#define HMATRIXB_PRAS_M3PR(value) (HMATRIXB_PRAS_M3PR_Msk & ((value) << HMATRIXB_PRAS_M3PR_Pos))
|
||||
#define HMATRIXB_PRAS_M4PR_Pos 16 /**< \brief (HMATRIXB_PRAS) Master 4 Priority */
|
||||
#define HMATRIXB_PRAS_M4PR_Msk (0xFul << HMATRIXB_PRAS_M4PR_Pos)
|
||||
#define HMATRIXB_PRAS_M4PR(value) (HMATRIXB_PRAS_M4PR_Msk & ((value) << HMATRIXB_PRAS_M4PR_Pos))
|
||||
#define HMATRIXB_PRAS_M5PR_Pos 20 /**< \brief (HMATRIXB_PRAS) Master 5 Priority */
|
||||
#define HMATRIXB_PRAS_M5PR_Msk (0xFul << HMATRIXB_PRAS_M5PR_Pos)
|
||||
#define HMATRIXB_PRAS_M5PR(value) (HMATRIXB_PRAS_M5PR_Msk & ((value) << HMATRIXB_PRAS_M5PR_Pos))
|
||||
#define HMATRIXB_PRAS_M6PR_Pos 24 /**< \brief (HMATRIXB_PRAS) Master 6 Priority */
|
||||
#define HMATRIXB_PRAS_M6PR_Msk (0xFul << HMATRIXB_PRAS_M6PR_Pos)
|
||||
#define HMATRIXB_PRAS_M6PR(value) (HMATRIXB_PRAS_M6PR_Msk & ((value) << HMATRIXB_PRAS_M6PR_Pos))
|
||||
#define HMATRIXB_PRAS_M7PR_Pos 28 /**< \brief (HMATRIXB_PRAS) Master 7 Priority */
|
||||
#define HMATRIXB_PRAS_M7PR_Msk (0xFul << HMATRIXB_PRAS_M7PR_Pos)
|
||||
#define HMATRIXB_PRAS_M7PR(value) (HMATRIXB_PRAS_M7PR_Msk & ((value) << HMATRIXB_PRAS_M7PR_Pos))
|
||||
#define HMATRIXB_PRAS_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_PRAS) MASK Register */
|
||||
|
||||
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t M8PR:4; /*!< bit: 0.. 3 Master 8 Priority */
|
||||
uint32_t M9PR:4; /*!< bit: 4.. 7 Master 9 Priority */
|
||||
uint32_t M10PR:4; /*!< bit: 8..11 Master 10 Priority */
|
||||
uint32_t M11PR:4; /*!< bit: 12..15 Master 11 Priority */
|
||||
uint32_t M12PR:4; /*!< bit: 16..19 Master 12 Priority */
|
||||
uint32_t M13PR:4; /*!< bit: 20..23 Master 13 Priority */
|
||||
uint32_t M14PR:4; /*!< bit: 24..27 Master 14 Priority */
|
||||
uint32_t M15PR:4; /*!< bit: 28..31 Master 15 Priority */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_PRBS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
@ -78,7 +119,31 @@ typedef union {
|
|||
#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
|
||||
#define HMATRIXB_PRBS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
|
||||
|
||||
#define HMATRIXB_PRBS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
|
||||
#define HMATRIXB_PRBS_M8PR_Pos 0 /**< \brief (HMATRIXB_PRBS) Master 8 Priority */
|
||||
#define HMATRIXB_PRBS_M8PR_Msk (0xFul << HMATRIXB_PRBS_M8PR_Pos)
|
||||
#define HMATRIXB_PRBS_M8PR(value) (HMATRIXB_PRBS_M8PR_Msk & ((value) << HMATRIXB_PRBS_M8PR_Pos))
|
||||
#define HMATRIXB_PRBS_M9PR_Pos 4 /**< \brief (HMATRIXB_PRBS) Master 9 Priority */
|
||||
#define HMATRIXB_PRBS_M9PR_Msk (0xFul << HMATRIXB_PRBS_M9PR_Pos)
|
||||
#define HMATRIXB_PRBS_M9PR(value) (HMATRIXB_PRBS_M9PR_Msk & ((value) << HMATRIXB_PRBS_M9PR_Pos))
|
||||
#define HMATRIXB_PRBS_M10PR_Pos 8 /**< \brief (HMATRIXB_PRBS) Master 10 Priority */
|
||||
#define HMATRIXB_PRBS_M10PR_Msk (0xFul << HMATRIXB_PRBS_M10PR_Pos)
|
||||
#define HMATRIXB_PRBS_M10PR(value) (HMATRIXB_PRBS_M10PR_Msk & ((value) << HMATRIXB_PRBS_M10PR_Pos))
|
||||
#define HMATRIXB_PRBS_M11PR_Pos 12 /**< \brief (HMATRIXB_PRBS) Master 11 Priority */
|
||||
#define HMATRIXB_PRBS_M11PR_Msk (0xFul << HMATRIXB_PRBS_M11PR_Pos)
|
||||
#define HMATRIXB_PRBS_M11PR(value) (HMATRIXB_PRBS_M11PR_Msk & ((value) << HMATRIXB_PRBS_M11PR_Pos))
|
||||
#define HMATRIXB_PRBS_M12PR_Pos 16 /**< \brief (HMATRIXB_PRBS) Master 12 Priority */
|
||||
#define HMATRIXB_PRBS_M12PR_Msk (0xFul << HMATRIXB_PRBS_M12PR_Pos)
|
||||
#define HMATRIXB_PRBS_M12PR(value) (HMATRIXB_PRBS_M12PR_Msk & ((value) << HMATRIXB_PRBS_M12PR_Pos))
|
||||
#define HMATRIXB_PRBS_M13PR_Pos 20 /**< \brief (HMATRIXB_PRBS) Master 13 Priority */
|
||||
#define HMATRIXB_PRBS_M13PR_Msk (0xFul << HMATRIXB_PRBS_M13PR_Pos)
|
||||
#define HMATRIXB_PRBS_M13PR(value) (HMATRIXB_PRBS_M13PR_Msk & ((value) << HMATRIXB_PRBS_M13PR_Pos))
|
||||
#define HMATRIXB_PRBS_M14PR_Pos 24 /**< \brief (HMATRIXB_PRBS) Master 14 Priority */
|
||||
#define HMATRIXB_PRBS_M14PR_Msk (0xFul << HMATRIXB_PRBS_M14PR_Pos)
|
||||
#define HMATRIXB_PRBS_M14PR(value) (HMATRIXB_PRBS_M14PR_Msk & ((value) << HMATRIXB_PRBS_M14PR_Pos))
|
||||
#define HMATRIXB_PRBS_M15PR_Pos 28 /**< \brief (HMATRIXB_PRBS) Master 15 Priority */
|
||||
#define HMATRIXB_PRBS_M15PR_Msk (0xFul << HMATRIXB_PRBS_M15PR_Pos)
|
||||
#define HMATRIXB_PRBS_M15PR(value) (HMATRIXB_PRBS_M15PR_Msk & ((value) << HMATRIXB_PRBS_M15PR_Pos))
|
||||
#define HMATRIXB_PRBS_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_PRBS) MASK Register */
|
||||
|
||||
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -95,7 +160,7 @@ typedef union {
|
|||
|
||||
#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
|
||||
#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
|
||||
#define HMATRIXB_SFR_SFR(value) ((HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)))
|
||||
#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
|
||||
#define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
|
||||
|
||||
/** \brief HmatrixbPrs hardware registers */
|
||||
|
@ -118,4 +183,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
|
||||
#endif /* _SAMD11_HMATRIXB_COMPONENT_ */
|
||||
|
|
|
@ -1,642 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for I2S
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_I2S_COMPONENT_
|
||||
#define _SAMD21_I2S_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR I2S */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
|
||||
/*@{*/
|
||||
|
||||
#define I2S_U2224
|
||||
#define REV_I2S 0x110
|
||||
|
||||
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
|
||||
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
|
||||
uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
|
||||
uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
|
||||
uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} I2S_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
|
||||
#define I2S_CTRLA_RESETVALUE 0x00ul /**< \brief (I2S_CTRLA reset_value) Control A */
|
||||
|
||||
#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
|
||||
#define I2S_CTRLA_SWRST (0x1ul << I2S_CTRLA_SWRST_Pos)
|
||||
#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
|
||||
#define I2S_CTRLA_ENABLE (0x1ul << I2S_CTRLA_ENABLE_Pos)
|
||||
#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
|
||||
#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
|
||||
#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
|
||||
#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
|
||||
#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
|
||||
#define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos)
|
||||
#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
|
||||
#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
|
||||
#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
|
||||
#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
|
||||
#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
|
||||
#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
|
||||
#define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos)
|
||||
#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
|
||||
#define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */
|
||||
|
||||
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
|
||||
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
|
||||
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
|
||||
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
|
||||
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
|
||||
uint32_t :2; /*!< bit: 9..10 Reserved */
|
||||
uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
|
||||
uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
|
||||
uint32_t :3; /*!< bit: 13..15 Reserved */
|
||||
uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
|
||||
uint32_t :1; /*!< bit: 17 Reserved */
|
||||
uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
|
||||
uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
|
||||
uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
|
||||
uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
|
||||
uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
|
||||
uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} I2S_CLKCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
|
||||
#define I2S_CLKCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
|
||||
|
||||
#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
|
||||
#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3ul /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
|
||||
#define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
|
||||
#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
|
||||
#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
|
||||
#define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
|
||||
#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
|
||||
#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
|
||||
#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
|
||||
#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
|
||||
#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3ul /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
|
||||
#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
|
||||
#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
|
||||
#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
|
||||
#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
|
||||
#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
|
||||
#define I2S_CLKCTRL_BITDELAY (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
|
||||
#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0ul /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
|
||||
#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1ul /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
|
||||
#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
|
||||
#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
|
||||
#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
|
||||
#define I2S_CLKCTRL_FSSEL (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
|
||||
#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
|
||||
#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
|
||||
#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
|
||||
#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
|
||||
#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
|
||||
#define I2S_CLKCTRL_FSINV (0x1ul << I2S_CLKCTRL_FSINV_Pos)
|
||||
#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
|
||||
#define I2S_CLKCTRL_SCKSEL (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
|
||||
#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
|
||||
#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
|
||||
#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
|
||||
#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
|
||||
#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
|
||||
#define I2S_CLKCTRL_MCKSEL (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
|
||||
#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0ul /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
|
||||
#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
|
||||
#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
|
||||
#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
|
||||
#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
|
||||
#define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
|
||||
#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
|
||||
#define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
|
||||
#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
|
||||
#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
|
||||
#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
|
||||
#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
|
||||
#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
|
||||
#define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
|
||||
#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
|
||||
#define I2S_CLKCTRL_SCKOUTINV (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
|
||||
#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
|
||||
#define I2S_CLKCTRL_MCKOUTINV (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
|
||||
#define I2S_CLKCTRL_MASK 0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
|
||||
|
||||
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
|
||||
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
|
||||
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
|
||||
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
|
||||
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} I2S_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define I2S_INTENCLR_RESETVALUE 0x0000ul /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
|
||||
#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
|
||||
#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos)
|
||||
#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
|
||||
#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
|
||||
#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
|
||||
#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos)
|
||||
#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
|
||||
#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
|
||||
#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
|
||||
#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos)
|
||||
#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
|
||||
#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
|
||||
#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
|
||||
#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos)
|
||||
#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
|
||||
#define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
|
||||
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
|
||||
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
|
||||
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
|
||||
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} I2S_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
|
||||
#define I2S_INTENSET_RESETVALUE 0x0000ul /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
|
||||
#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
|
||||
#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
|
||||
#define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos)
|
||||
#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
|
||||
#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
|
||||
#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
|
||||
#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
|
||||
#define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos)
|
||||
#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
|
||||
#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
|
||||
#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
|
||||
#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
|
||||
#define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos)
|
||||
#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
|
||||
#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
|
||||
#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
|
||||
#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
|
||||
#define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos)
|
||||
#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
|
||||
#define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */
|
||||
|
||||
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
|
||||
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
|
||||
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
|
||||
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
|
||||
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} I2S_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define I2S_INTFLAG_RESETVALUE 0x0000ul /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
|
||||
#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
|
||||
#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
|
||||
#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
|
||||
#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
|
||||
#define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos)
|
||||
#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
|
||||
#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
|
||||
#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
|
||||
#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
|
||||
#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
|
||||
#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
|
||||
#define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos)
|
||||
#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
|
||||
#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
|
||||
#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
|
||||
#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
|
||||
#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
|
||||
#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
|
||||
#define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos)
|
||||
#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
|
||||
#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
|
||||
#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
|
||||
#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
|
||||
#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
|
||||
#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
|
||||
#define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos)
|
||||
#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
|
||||
#define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
|
||||
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
|
||||
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
|
||||
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
|
||||
uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
|
||||
uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
|
||||
uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
|
||||
uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
|
||||
uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
|
||||
uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} I2S_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
|
||||
#define I2S_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
|
||||
|
||||
#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SWRST (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
|
||||
#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_ENABLE (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
|
||||
#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
|
||||
#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
|
||||
#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
|
||||
#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
|
||||
#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
|
||||
#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
|
||||
#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
|
||||
#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
|
||||
#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
|
||||
#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
|
||||
#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
|
||||
#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
|
||||
#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
|
||||
#define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos)
|
||||
#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
|
||||
#define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
|
||||
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
|
||||
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
|
||||
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
|
||||
uint32_t :1; /*!< bit: 6 Reserved */
|
||||
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
|
||||
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
|
||||
uint32_t :1; /*!< bit: 11 Reserved */
|
||||
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
|
||||
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
|
||||
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
|
||||
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
|
||||
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
|
||||
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
|
||||
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
|
||||
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
|
||||
uint32_t :5; /*!< bit: 27..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
|
||||
uint32_t :8; /*!< bit: 24..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} I2S_SERCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
|
||||
#define I2S_SERCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
|
||||
|
||||
#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
|
||||
#define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos)
|
||||
#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
|
||||
#define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */
|
||||
#define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */
|
||||
#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
|
||||
#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
|
||||
#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
|
||||
#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
|
||||
#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
|
||||
#define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
|
||||
#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
|
||||
#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
|
||||
#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
|
||||
#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
|
||||
#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
|
||||
#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
|
||||
#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
|
||||
#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
|
||||
#define I2S_SERCTRL_TXSAME (0x1ul << I2S_SERCTRL_TXSAME_Pos)
|
||||
#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
|
||||
#define I2S_SERCTRL_TXSAME_SAME_Val 0x1ul /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
|
||||
#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
|
||||
#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
|
||||
#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
|
||||
#define I2S_SERCTRL_CLKSEL (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
|
||||
#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0ul /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
|
||||
#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1ul /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
|
||||
#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
|
||||
#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
|
||||
#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
|
||||
#define I2S_SERCTRL_SLOTADJ (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
|
||||
#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
|
||||
#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
|
||||
#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
|
||||
#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
|
||||
#define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
|
||||
#define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_18_Val 0x3ul /**< \brief (I2S_SERCTRL) 18 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_16_Val 0x4ul /**< \brief (I2S_SERCTRL) 16 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_16C_Val 0x5ul /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
|
||||
#define I2S_SERCTRL_DATASIZE_8_Val 0x6ul /**< \brief (I2S_SERCTRL) 8 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_8C_Val 0x7ul /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
|
||||
#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
|
||||
#define I2S_SERCTRL_WORDADJ (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
|
||||
#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
|
||||
#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
|
||||
#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
|
||||
#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
|
||||
#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
|
||||
#define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos)
|
||||
#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
|
||||
#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */
|
||||
#define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */
|
||||
#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
|
||||
#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3ul /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
|
||||
#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
|
||||
#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
|
||||
#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
|
||||
#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
|
||||
#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
|
||||
#define I2S_SERCTRL_BITREV (0x1ul << I2S_SERCTRL_BITREV_Pos)
|
||||
#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0ul /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
|
||||
#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1ul /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
|
||||
#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
|
||||
#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
|
||||
#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
|
||||
#define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos)
|
||||
#define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */
|
||||
#define I2S_SERCTRL_MONO_MONO_Val 0x1ul /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
|
||||
#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
|
||||
#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
|
||||
#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
|
||||
#define I2S_SERCTRL_DMA (0x1ul << I2S_SERCTRL_DMA_Pos)
|
||||
#define I2S_SERCTRL_DMA_SINGLE_Val 0x0ul /**< \brief (I2S_SERCTRL) Single DMA channel */
|
||||
#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1ul /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
|
||||
#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
|
||||
#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
|
||||
#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
|
||||
#define I2S_SERCTRL_RXLOOP (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
|
||||
#define I2S_SERCTRL_MASK 0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
|
||||
|
||||
/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} I2S_DATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
|
||||
#define I2S_DATA_RESETVALUE 0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
|
||||
|
||||
#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
|
||||
#define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
|
||||
#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
|
||||
#define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
|
||||
|
||||
/** \brief I2S hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
|
||||
RoReg8 Reserved1[0x3];
|
||||
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
|
||||
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
|
||||
RoReg8 Reserved3[0x2];
|
||||
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
|
||||
RoReg8 Reserved4[0x2];
|
||||
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
|
||||
RoReg8 Reserved5[0x6];
|
||||
__IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
|
||||
RoReg8 Reserved6[0x8];
|
||||
__IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
|
||||
} I2s;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_I2S_COMPONENT_ */
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for MTB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_COMPONENT_
|
||||
#define _SAMD21_MTB_COMPONENT_
|
||||
#ifndef _SAMD11_MTB_COMPONENT_
|
||||
#define _SAMD11_MTB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR MTB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
|
||||
/** \addtogroup SAMD11_MTB Cortex-M0+ Micro-Trace Buffer */
|
||||
/*@{*/
|
||||
|
||||
#define MTB_U2002
|
||||
|
@ -74,7 +71,7 @@ typedef union {
|
|||
#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
|
||||
#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
|
||||
#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
|
||||
#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
|
||||
#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
|
||||
#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
|
||||
|
||||
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
|
||||
|
@ -99,7 +96,7 @@ typedef union {
|
|||
|
||||
#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
|
||||
#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
|
||||
#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
|
||||
#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
|
||||
#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
|
||||
#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
|
||||
#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
|
||||
|
@ -136,7 +133,7 @@ typedef union {
|
|||
#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
|
||||
#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
|
||||
#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
|
||||
#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
|
||||
#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
|
||||
#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
|
||||
|
||||
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
|
||||
|
@ -396,4 +393,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_MTB_COMPONENT_ */
|
||||
#endif /* _SAMD11_MTB_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_NVMCTRL_COMPONENT_
|
||||
#define _SAMD21_NVMCTRL_COMPONENT_
|
||||
#ifndef _SAMD11_NVMCTRL_COMPONENT_
|
||||
#define _SAMD11_NVMCTRL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR NVMCTRL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
|
||||
/** \addtogroup SAMD11_NVMCTRL Non-Volatile Memory Controller */
|
||||
/*@{*/
|
||||
|
||||
#define NVMCTRL_U2207
|
||||
#define REV_NVMCTRL 0x201
|
||||
#define REV_NVMCTRL 0x107
|
||||
|
||||
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -73,30 +70,26 @@ typedef union {
|
|||
|
||||
#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
|
||||
#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
|
||||
#define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
|
||||
#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
|
||||
#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
|
||||
#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
|
||||
#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */
|
||||
#define NVMCTRL_CTRLA_CMD_RWWEEER_Val 0x1Aul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_RWWEEWP_Val 0x1Cul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
|
||||
#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
|
||||
#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
|
||||
#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
|
||||
#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
|
||||
#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
|
||||
#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
|
@ -106,7 +99,7 @@ typedef union {
|
|||
#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
|
||||
#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
|
||||
#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
|
||||
#define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
|
||||
#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
|
||||
#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
|
||||
#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
|
||||
|
@ -134,7 +127,7 @@ typedef union {
|
|||
|
||||
#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
|
||||
#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
|
||||
#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
|
||||
#define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
|
||||
#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
|
||||
#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
|
||||
#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
|
||||
|
@ -145,7 +138,7 @@ typedef union {
|
|||
#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
|
||||
|
@ -154,7 +147,7 @@ typedef union {
|
|||
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
|
||||
#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
|
||||
#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
|
||||
#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
|
||||
#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
|
||||
#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
|
||||
#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
|
||||
#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
|
||||
|
@ -171,8 +164,7 @@ typedef union {
|
|||
struct {
|
||||
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
|
||||
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
|
||||
uint32_t :1; /*!< bit: 19 Reserved */
|
||||
uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
|
||||
uint32_t :13; /*!< bit: 19..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} NVMCTRL_PARAM_Type;
|
||||
|
@ -183,10 +175,10 @@ typedef union {
|
|||
|
||||
#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
|
||||
#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
|
||||
#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
|
||||
#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
|
||||
#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
|
||||
#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
|
||||
#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
|
||||
#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
|
||||
#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
|
||||
#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
|
||||
#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
|
||||
|
@ -203,10 +195,7 @@ typedef union {
|
|||
#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
|
||||
#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
|
||||
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
|
||||
#define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
|
||||
#define NVMCTRL_PARAM_RWWEEP_Msk (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
|
||||
#define NVMCTRL_PARAM_RWWEEP(value) ((NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos)))
|
||||
#define NVMCTRL_PARAM_MASK 0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
|
||||
#define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
|
||||
|
||||
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -252,11 +241,11 @@ typedef union {
|
|||
|
||||
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t READY:1; /*!< bit: 0 NVM Ready */
|
||||
uint8_t ERROR:1; /*!< bit: 1 Error */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
__I uint8_t READY:1; /*!< bit: 0 NVM Ready */
|
||||
__I uint8_t ERROR:1; /*!< bit: 1 Error */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} NVMCTRL_INTFLAG_Type;
|
||||
|
@ -321,7 +310,7 @@ typedef union {
|
|||
|
||||
#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
|
||||
#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
|
||||
#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
|
||||
#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
|
||||
#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
|
||||
|
||||
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
|
||||
|
@ -338,7 +327,7 @@ typedef union {
|
|||
|
||||
#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
|
||||
#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
|
||||
#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
|
||||
#define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
|
||||
#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
|
||||
|
||||
/** \brief NVMCTRL APB hardware registers */
|
||||
|
@ -380,27 +369,27 @@ typedef struct {
|
|||
#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
|
||||
#define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
|
||||
#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
|
||||
#define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
|
||||
|
||||
#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
|
||||
#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
|
||||
#define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
|
||||
#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
|
||||
#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
|
||||
|
||||
#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
|
||||
#define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
|
||||
#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
|
||||
#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
|
||||
|
||||
#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
|
||||
#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
|
||||
#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)))
|
||||
#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
|
||||
|
||||
#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
|
||||
#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
|
||||
#define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)))
|
||||
#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
|
||||
|
||||
#define FUSES_BOD33_EN_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
|
||||
|
@ -413,135 +402,106 @@ typedef struct {
|
|||
#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
|
||||
#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
|
||||
#define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)))
|
||||
#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
|
||||
|
||||
#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
|
||||
#define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
|
||||
#define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
|
||||
#define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)))
|
||||
#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
|
||||
|
||||
#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
|
||||
#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
|
||||
#define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos)))
|
||||
#define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
|
||||
|
||||
#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
|
||||
#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
|
||||
#define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)))
|
||||
#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
|
||||
|
||||
#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
|
||||
#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
|
||||
#define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)))
|
||||
#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
|
||||
|
||||
#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
|
||||
#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
|
||||
#define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)))
|
||||
#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
|
||||
|
||||
#define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
|
||||
#define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
|
||||
#define FUSES_OSC32K_CAL(value) ((FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos)))
|
||||
#define FUSES_OSC32K_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define FUSES_OSC32K_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
|
||||
#define FUSES_OSC32K_Msk (0x7Ful << FUSES_OSC32K_Pos)
|
||||
#define FUSES_OSC32K(value) (FUSES_OSC32K_Msk & ((value) << FUSES_OSC32K_Pos))
|
||||
|
||||
#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
|
||||
#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
|
||||
#define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos)))
|
||||
#define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
|
||||
|
||||
#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
|
||||
#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
|
||||
#define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)))
|
||||
#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
|
||||
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)))
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
|
||||
|
||||
#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
|
||||
#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
|
||||
#define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)))
|
||||
#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
|
||||
#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
|
||||
#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
|
||||
#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
|
||||
#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
|
||||
|
||||
/* Compatible definition for previous driver (begin 1) */
|
||||
#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
|
||||
#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
|
||||
#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
|
||||
#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
|
||||
#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
|
||||
/* Compatible definition for previous driver (end 1) */
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
|
||||
#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
|
||||
#define NVMCTRL_FUSES_NVMP_Msk (0x1FFFul << NVMCTRL_FUSES_NVMP_Pos)
|
||||
#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
|
||||
#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
|
||||
#define NVMCTRL_FUSES_NVMP(value) (NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
|
||||
#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
|
||||
#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
|
||||
#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
|
||||
#define NVMCTRL_FUSES_NVM_LOCK(value) (NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
|
||||
#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
|
||||
#define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
|
||||
#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
|
||||
#define NVMCTRL_FUSES_PSZ(value) (NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_RWWEEP_ADDR (NVMCTRL_OTP1 + 4)
|
||||
#define NVMCTRL_FUSES_RWWEEP_Pos 0 /**< \brief (NVMCTRL_OTP1) RWW EEPROM */
|
||||
#define NVMCTRL_FUSES_RWWEEP_Msk (0xFFul << NVMCTRL_FUSES_RWWEEP_Pos)
|
||||
#define NVMCTRL_FUSES_RWWEEP(value) ((NVMCTRL_FUSES_RWWEEP_Msk & ((value) << NVMCTRL_FUSES_RWWEEP_Pos)))
|
||||
/* Compatible definition for previous driver (begin 1) */
|
||||
#define SYSCTRL_FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER
|
||||
#define SYSCTRL_FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */
|
||||
#define SYSCTRL_FUSES_BOD12USERLEVEL_Msk (0x1Fu << SYSCTRL_FUSES_BOD12USERLEVEL_Pos)
|
||||
#define SYSCTRL_FUSES_BOD12USERLEVEL(value) ((SYSCTRL_FUSES_BOD12USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD12USERLEVEL_Pos)))
|
||||
|
||||
/* Compatible definition for previous driver (begin 2) */
|
||||
#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
|
||||
#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
|
||||
#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
|
||||
#define SYSCTRL_FUSES_BOD12_ACTION_ADDR NVMCTRL_USER
|
||||
#define SYSCTRL_FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */
|
||||
#define SYSCTRL_FUSES_BOD12_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD12_ACTION_Pos)
|
||||
#define SYSCTRL_FUSES_BOD12_ACTION(value) ((SYSCTRL_FUSES_BOD12_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD12_ACTION_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
|
||||
#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
|
||||
#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
|
||||
#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
|
||||
#define SYSCTRL_FUSES_BOD12_EN_ADDR NVMCTRL_USER
|
||||
#define SYSCTRL_FUSES_BOD12_EN_Pos 22 /**< \brief (NVMCTRL_USER) BOD12 Enable */
|
||||
#define SYSCTRL_FUSES_BOD12_EN_Msk (0x1u << SYSCTRL_FUSES_BOD12_EN_Pos)
|
||||
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
|
||||
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
|
||||
#define SYSCTRL_FUSES_BOD12_HYST_ADDR (NVMCTRL_USER + 4)
|
||||
#define SYSCTRL_FUSES_BOD12_HYST_Pos 9 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
|
||||
#define SYSCTRL_FUSES_BOD12_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD12_HYST_Pos)
|
||||
|
||||
#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
|
||||
#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
|
||||
|
@ -561,31 +521,31 @@ typedef struct {
|
|||
#define SYSCTRL_FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
|
||||
#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
|
||||
|
||||
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
|
||||
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
|
||||
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
|
||||
#define SYSCTRL_FUSES_OSC32K_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define SYSCTRL_FUSES_OSC32K_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
|
||||
#define SYSCTRL_FUSES_OSC32K_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_Pos)
|
||||
#define SYSCTRL_FUSES_OSC32K(value) ((SYSCTRL_FUSES_OSC32K_Msk & ((value) << SYSCTRL_FUSES_OSC32K_Pos)))
|
||||
|
||||
#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
|
||||
#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
|
||||
#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
|
||||
#define SYSCTRL_FUSES_ULPVREG_ADDR NVMCTRL_OTP4
|
||||
#define SYSCTRL_FUSES_ULPVREG_Pos 0 /**< \brief (NVMCTRL_OTP4) ULP Regulator Fallback Mode */
|
||||
#define SYSCTRL_FUSES_ULPVREG_Msk (0x7u << SYSCTRL_FUSES_ULPVREG_Pos)
|
||||
#define SYSCTRL_FUSES_ULPVREG(value) ((SYSCTRL_FUSES_ULPVREG_Msk & ((value) << SYSCTRL_FUSES_ULPVREG_Pos)))
|
||||
/* Compatible definition for previous driver (end 2) */
|
||||
|
||||
#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
|
||||
#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
|
||||
#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)))
|
||||
#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
|
||||
|
||||
#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
|
||||
#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
|
||||
#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)))
|
||||
#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
|
||||
|
||||
#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
|
||||
#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
|
||||
#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)))
|
||||
#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
|
||||
|
||||
#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
|
||||
#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
|
||||
|
@ -598,12 +558,12 @@ typedef struct {
|
|||
#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
|
||||
#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
|
||||
#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
|
||||
#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
|
||||
#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
|
||||
|
||||
#define WDT_FUSES_PER_ADDR NVMCTRL_USER
|
||||
#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
|
||||
#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
|
||||
#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
|
||||
#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
|
||||
|
||||
#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
|
||||
#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
|
||||
|
@ -616,8 +576,8 @@ typedef struct {
|
|||
#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
|
||||
#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
|
||||
#define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
|
||||
#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
|
||||
#define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
|
||||
#endif /* _SAMD11_NVMCTRL_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC_COMPONENT_
|
||||
#define _SAMD21_PAC_COMPONENT_
|
||||
#ifndef _SAMD11_PAC_COMPONENT_
|
||||
#define _SAMD11_PAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PAC Peripheral Access Controller */
|
||||
/** \addtogroup SAMD11_PAC Peripheral Access Controller */
|
||||
/*@{*/
|
||||
|
||||
#define PAC_U2211
|
||||
|
@ -72,7 +69,7 @@ typedef union {
|
|||
|
||||
#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
|
||||
#define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
|
||||
#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))
|
||||
#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
|
||||
#define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
|
||||
|
||||
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
|
||||
|
@ -91,7 +88,7 @@ typedef union {
|
|||
|
||||
#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
|
||||
#define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
|
||||
#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))
|
||||
#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
|
||||
#define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
|
||||
|
||||
/** \brief PAC hardware registers */
|
||||
|
@ -104,4 +101,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PAC_COMPONENT_ */
|
||||
#endif /* _SAMD11_PAC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PM
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PM_COMPONENT_
|
||||
#define _SAMD21_PM_COMPONENT_
|
||||
#ifndef _SAMD11_PM_COMPONENT_
|
||||
#define _SAMD11_PM_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PM */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PM Power Manager */
|
||||
/** \addtogroup SAMD11_PM Power Manager */
|
||||
/*@{*/
|
||||
|
||||
#define PM_U2206
|
||||
|
@ -59,6 +56,13 @@
|
|||
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint8_t CFDEN:1; /*!< bit: 2 Clock Failure Detector Enable */
|
||||
uint8_t :1; /*!< bit: 3 Reserved */
|
||||
uint8_t BKUPCLK:1; /*!< bit: 4 Backup Clock Select */
|
||||
uint8_t :3; /*!< bit: 5.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PM_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
@ -66,7 +70,11 @@ typedef union {
|
|||
#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
|
||||
#define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */
|
||||
|
||||
#define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */
|
||||
#define PM_CTRL_CFDEN_Pos 2 /**< \brief (PM_CTRL) Clock Failure Detector Enable */
|
||||
#define PM_CTRL_CFDEN (0x1ul << PM_CTRL_CFDEN_Pos)
|
||||
#define PM_CTRL_BKUPCLK_Pos 4 /**< \brief (PM_CTRL) Backup Clock Select */
|
||||
#define PM_CTRL_BKUPCLK (0x1ul << PM_CTRL_BKUPCLK_Pos)
|
||||
#define PM_CTRL_MASK 0x14ul /**< \brief (PM_CTRL) MASK Register */
|
||||
|
||||
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -84,7 +92,7 @@ typedef union {
|
|||
|
||||
#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
|
||||
#define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
|
||||
#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
|
||||
#define PM_SLEEP_IDLE(value) (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
|
||||
#define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
|
||||
#define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
|
||||
#define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
|
||||
|
@ -127,7 +135,7 @@ typedef union {
|
|||
|
||||
#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
|
||||
#define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
|
||||
#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
|
||||
#define PM_CPUSEL_CPUDIV(value) (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
|
||||
#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
|
||||
#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
|
||||
#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
|
||||
|
@ -162,7 +170,7 @@ typedef union {
|
|||
|
||||
#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
|
||||
#define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
|
||||
#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
|
||||
#define PM_APBASEL_APBADIV(value) (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
|
||||
#define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
|
||||
#define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
|
||||
#define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
|
||||
|
@ -197,7 +205,7 @@ typedef union {
|
|||
|
||||
#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
|
||||
#define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
|
||||
#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
|
||||
#define PM_APBBSEL_APBBDIV(value) (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
|
||||
#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
|
||||
#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
|
||||
#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
|
||||
|
@ -232,7 +240,7 @@ typedef union {
|
|||
|
||||
#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
|
||||
#define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
|
||||
#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
|
||||
#define PM_APBCSEL_APBCDIV(value) (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
|
||||
#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
|
||||
#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
|
||||
#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
|
||||
|
@ -368,32 +376,21 @@ typedef union {
|
|||
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
|
||||
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
|
||||
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
|
||||
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
|
||||
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
|
||||
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
|
||||
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
|
||||
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
|
||||
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
|
||||
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
|
||||
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
|
||||
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
|
||||
uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
|
||||
uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
|
||||
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
|
||||
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
|
||||
uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
|
||||
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
|
||||
uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
|
||||
uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
|
||||
uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
|
||||
uint32_t :9; /*!< bit: 23..31 Reserved */
|
||||
uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Clock Enable */
|
||||
uint32_t TC1_:1; /*!< bit: 6 TC1 APB Clock Enable */
|
||||
uint32_t TC2_:1; /*!< bit: 7 TC2 APB Clock Enable */
|
||||
uint32_t ADC_:1; /*!< bit: 8 ADC APB Clock Enable */
|
||||
uint32_t AC_:1; /*!< bit: 9 AC APB Clock Enable */
|
||||
uint32_t DAC_:1; /*!< bit: 10 DAC APB Clock Enable */
|
||||
uint32_t PTC_:1; /*!< bit: 11 PTC APB Clock Enable */
|
||||
uint32_t :20; /*!< bit: 12..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PM_APBCMASK_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
|
||||
#define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
|
||||
#define PM_APBCMASK_RESETVALUE 0x00000100ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
|
||||
|
||||
#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
|
||||
#define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos)
|
||||
|
@ -405,50 +402,29 @@ typedef union {
|
|||
#define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos)
|
||||
#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
|
||||
#define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos)
|
||||
#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
|
||||
#define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos)
|
||||
#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
|
||||
#define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos)
|
||||
#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
|
||||
#define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos)
|
||||
#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
|
||||
#define PM_APBCMASK_TCC0_Pos 5 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
|
||||
#define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos)
|
||||
#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
|
||||
#define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos)
|
||||
#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
|
||||
#define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos)
|
||||
#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos)
|
||||
#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos)
|
||||
#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos)
|
||||
#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos)
|
||||
#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos)
|
||||
#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
|
||||
#define PM_APBCMASK_TC1_Pos 6 /**< \brief (PM_APBCMASK) TC1 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC1 (0x1ul << PM_APBCMASK_TC1_Pos)
|
||||
#define PM_APBCMASK_TC2_Pos 7 /**< \brief (PM_APBCMASK) TC2 APB Clock Enable */
|
||||
#define PM_APBCMASK_TC2 (0x1ul << PM_APBCMASK_TC2_Pos)
|
||||
#define PM_APBCMASK_ADC_Pos 8 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
|
||||
#define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos)
|
||||
#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
|
||||
#define PM_APBCMASK_AC_Pos 9 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
|
||||
#define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos)
|
||||
#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
|
||||
#define PM_APBCMASK_DAC_Pos 10 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
|
||||
#define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos)
|
||||
#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
|
||||
#define PM_APBCMASK_PTC_Pos 11 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
|
||||
#define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos)
|
||||
#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
|
||||
#define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos)
|
||||
#define PM_APBCMASK_AC1_Pos 21 /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
|
||||
#define PM_APBCMASK_AC1 (0x1ul << PM_APBCMASK_AC1_Pos)
|
||||
#define PM_APBCMASK_LINCTRL_Pos 22 /**< \brief (PM_APBCMASK) LINCTRL APB Clock Enable */
|
||||
#define PM_APBCMASK_LINCTRL (0x1ul << PM_APBCMASK_LINCTRL_Pos)
|
||||
#define PM_APBCMASK_MASK 0x007FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
|
||||
#define PM_APBCMASK_MASK 0x00000FFFul /**< \brief (PM_APBCMASK) MASK Register */
|
||||
|
||||
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PM_INTENCLR_Type;
|
||||
|
@ -459,14 +435,17 @@ typedef union {
|
|||
|
||||
#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
|
||||
#define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos)
|
||||
#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */
|
||||
#define PM_INTENCLR_CFD_Pos 1 /**< \brief (PM_INTENCLR) Clock Failure Detector Interrupt Enable */
|
||||
#define PM_INTENCLR_CFD (0x1ul << PM_INTENCLR_CFD_Pos)
|
||||
#define PM_INTENCLR_MASK 0x03ul /**< \brief (PM_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PM_INTENSET_Type;
|
||||
|
@ -477,14 +456,17 @@ typedef union {
|
|||
|
||||
#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
|
||||
#define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos)
|
||||
#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */
|
||||
#define PM_INTENSET_CFD_Pos 1 /**< \brief (PM_INTENSET) Clock Failure Detector Interrupt Enable */
|
||||
#define PM_INTENSET_CFD (0x1ul << PM_INTENSET_CFD_Pos)
|
||||
#define PM_INTENSET_MASK 0x03ul /**< \brief (PM_INTENSET) MASK Register */
|
||||
|
||||
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
|
||||
__I uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PM_INTFLAG_Type;
|
||||
|
@ -495,7 +477,9 @@ typedef union {
|
|||
|
||||
#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
|
||||
#define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos)
|
||||
#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */
|
||||
#define PM_INTFLAG_CFD_Pos 1 /**< \brief (PM_INTFLAG) Clock Failure Detector */
|
||||
#define PM_INTFLAG_CFD (0x1ul << PM_INTFLAG_CFD_Pos)
|
||||
#define PM_INTFLAG_MASK 0x03ul /**< \brief (PM_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -558,4 +542,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PM_COMPONENT_ */
|
||||
#endif /* _SAMD11_PM_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for PORT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_COMPONENT_
|
||||
#define _SAMD21_PORT_COMPONENT_
|
||||
#ifndef _SAMD11_PORT_COMPONENT_
|
||||
#define _SAMD11_PORT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PORT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PORT Port Module */
|
||||
/** \addtogroup SAMD11_PORT Port Module */
|
||||
/*@{*/
|
||||
|
||||
#define PORT_U2210
|
||||
|
@ -71,7 +68,7 @@ typedef union {
|
|||
|
||||
#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
|
||||
#define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
|
||||
#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
|
||||
#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
|
||||
#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
|
||||
|
@ -89,7 +86,7 @@ typedef union {
|
|||
|
||||
#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
|
||||
#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
|
||||
#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
|
||||
#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
|
||||
#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
|
||||
|
@ -107,7 +104,7 @@ typedef union {
|
|||
|
||||
#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
|
||||
#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
|
||||
#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
|
||||
#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
|
||||
#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
|
||||
|
@ -125,7 +122,7 @@ typedef union {
|
|||
|
||||
#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
|
||||
#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
|
||||
#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
|
||||
#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
|
||||
#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
|
||||
|
@ -143,7 +140,7 @@ typedef union {
|
|||
|
||||
#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
|
||||
#define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
|
||||
#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
|
||||
#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
|
||||
#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
|
||||
|
@ -161,7 +158,7 @@ typedef union {
|
|||
|
||||
#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
|
||||
#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
|
||||
#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
|
||||
#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
|
||||
#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
|
||||
|
@ -179,7 +176,7 @@ typedef union {
|
|||
|
||||
#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
|
||||
#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
|
||||
#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
|
||||
#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
|
||||
#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
|
||||
|
@ -197,7 +194,7 @@ typedef union {
|
|||
|
||||
#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
|
||||
#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
|
||||
#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
|
||||
#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
|
||||
#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
|
||||
|
@ -215,7 +212,7 @@ typedef union {
|
|||
|
||||
#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
|
||||
#define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos)
|
||||
#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
|
||||
#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
|
||||
#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
|
||||
|
||||
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
|
||||
|
@ -233,7 +230,7 @@ typedef union {
|
|||
|
||||
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
|
||||
#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
|
||||
#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
|
||||
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
|
||||
#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
|
||||
|
||||
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
|
||||
|
@ -262,7 +259,7 @@ typedef union {
|
|||
|
||||
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
|
||||
#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
|
||||
#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
|
||||
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
|
||||
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
|
||||
#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
|
||||
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
|
||||
|
@ -273,7 +270,7 @@ typedef union {
|
|||
#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
|
||||
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
|
||||
#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos)
|
||||
#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
|
||||
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
|
||||
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
|
||||
#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
|
||||
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
|
||||
|
@ -298,7 +295,7 @@ typedef union {
|
|||
|
||||
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
|
||||
#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
|
||||
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
|
||||
#define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
|
@ -317,7 +314,7 @@ typedef union {
|
|||
#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
|
||||
#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
|
||||
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
|
||||
#define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
|
@ -388,11 +385,11 @@ typedef struct {
|
|||
/** \brief PORT hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
|
||||
PortGroup Group[1]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
|
||||
} Port;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#define SECTION_PORT_IOBUS
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PORT_COMPONENT_ */
|
||||
#endif /* _SAMD11_PORT_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for RTC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_RTC_COMPONENT_
|
||||
#define _SAMD21_RTC_COMPONENT_
|
||||
#ifndef _SAMD11_RTC_COMPONENT_
|
||||
#define _SAMD11_RTC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR RTC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_RTC Real-Time Counter */
|
||||
/** \addtogroup SAMD11_RTC Real-Time Counter */
|
||||
/*@{*/
|
||||
|
||||
#define RTC_U2202
|
||||
|
@ -81,7 +78,7 @@ typedef union {
|
|||
#define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
|
||||
#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
|
||||
#define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
|
||||
#define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
|
||||
#define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
|
||||
#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
|
||||
#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
|
||||
#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
|
||||
|
@ -92,7 +89,7 @@ typedef union {
|
|||
#define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
|
||||
#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
|
||||
#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
|
||||
#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
|
||||
#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
|
||||
#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
|
||||
#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
|
||||
#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
|
||||
|
@ -141,7 +138,7 @@ typedef union {
|
|||
#define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
|
||||
#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
|
||||
#define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
|
||||
#define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
|
||||
#define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
|
||||
#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
|
||||
#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
|
||||
#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
|
||||
|
@ -150,7 +147,7 @@ typedef union {
|
|||
#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
|
||||
#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
|
||||
#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
|
||||
#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
|
||||
#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
|
||||
#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
|
||||
#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
|
||||
#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
|
||||
|
@ -201,7 +198,7 @@ typedef union {
|
|||
#define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
|
||||
#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
|
||||
#define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
|
||||
#define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
|
||||
#define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
|
||||
#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
|
||||
#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
|
||||
#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
|
||||
|
@ -214,7 +211,7 @@ typedef union {
|
|||
#define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
|
||||
#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
|
||||
#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
|
||||
#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
|
||||
#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
|
||||
#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
|
||||
#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
|
||||
#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
|
||||
|
@ -257,7 +254,7 @@ typedef union {
|
|||
|
||||
#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
|
||||
#define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
|
||||
#define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
|
||||
#define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
|
||||
#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
|
||||
#define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
|
||||
#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
|
||||
|
@ -310,12 +307,12 @@ typedef union {
|
|||
#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
|
||||
#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
|
||||
#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
|
||||
#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
|
||||
#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
|
||||
#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
|
||||
#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
|
||||
#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
|
||||
#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
|
||||
#define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
|
||||
|
@ -367,14 +364,14 @@ typedef union {
|
|||
#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
|
||||
#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
|
||||
#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
|
||||
#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
|
||||
#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
|
||||
#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
|
||||
#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
|
||||
#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
|
||||
#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
|
||||
#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
|
||||
#define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
|
||||
|
@ -425,12 +422,12 @@ typedef union {
|
|||
#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
|
||||
#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
|
||||
#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
|
||||
#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
|
||||
#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
|
||||
#define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
|
||||
|
@ -459,7 +456,7 @@ typedef union {
|
|||
#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
|
||||
#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
|
||||
#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
|
||||
#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
|
||||
#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
|
||||
#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
|
||||
#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
|
||||
|
@ -493,7 +490,7 @@ typedef union {
|
|||
#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
|
||||
#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
|
||||
#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
|
||||
#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
|
||||
#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
|
||||
#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
|
||||
#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
|
||||
|
@ -524,7 +521,7 @@ typedef union {
|
|||
#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
|
||||
#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
|
||||
#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
|
||||
#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
|
||||
#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
|
||||
#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
|
||||
#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
|
||||
|
@ -555,7 +552,7 @@ typedef union {
|
|||
#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
|
||||
#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
|
||||
#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
|
||||
#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
|
||||
#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
|
||||
#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
|
||||
#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
|
||||
|
@ -589,7 +586,7 @@ typedef union {
|
|||
#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
|
||||
#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
|
||||
#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
|
||||
#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
|
||||
#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
|
||||
#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
|
||||
#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
|
||||
|
@ -620,7 +617,7 @@ typedef union {
|
|||
#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
|
||||
#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
|
||||
#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
|
||||
#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
|
||||
#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
|
||||
#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
|
||||
#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
|
||||
|
@ -629,16 +626,16 @@ typedef union {
|
|||
|
||||
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t CMP:1; /*!< bit: 0 Compare x */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t CMP:1; /*!< bit: 0 Compare x */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} RTC_MODE0_INTFLAG_Type;
|
||||
|
@ -651,7 +648,7 @@ typedef union {
|
|||
#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
|
||||
#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
|
||||
#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
|
||||
#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
|
||||
#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
|
||||
#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
|
||||
#define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
|
||||
#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
|
||||
|
@ -660,17 +657,17 @@ typedef union {
|
|||
|
||||
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
|
||||
uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
__I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
|
||||
__I uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
__I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} RTC_MODE1_INTFLAG_Type;
|
||||
|
@ -685,7 +682,7 @@ typedef union {
|
|||
#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
|
||||
#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
|
||||
#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
|
||||
#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
|
||||
#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
|
||||
#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
|
||||
#define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
|
||||
#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
|
||||
|
@ -694,16 +691,16 @@ typedef union {
|
|||
|
||||
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
|
||||
uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
__I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
|
||||
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t ALARM:1; /*!< bit: 0 Alarm x */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} RTC_MODE2_INTFLAG_Type;
|
||||
|
@ -716,7 +713,7 @@ typedef union {
|
|||
#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
|
||||
#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
|
||||
#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
|
||||
#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
|
||||
#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
|
||||
#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
|
||||
#define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
|
||||
#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
|
||||
|
@ -775,7 +772,7 @@ typedef union {
|
|||
|
||||
#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
|
||||
#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
|
||||
#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
|
||||
#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
|
||||
#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
|
||||
#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
|
||||
#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
|
||||
|
@ -795,7 +792,7 @@ typedef union {
|
|||
|
||||
#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
|
||||
#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
|
||||
#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
|
||||
#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
|
||||
#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
|
||||
|
@ -813,7 +810,7 @@ typedef union {
|
|||
|
||||
#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
|
||||
#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
|
||||
#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
|
||||
#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
|
||||
#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
|
||||
|
@ -836,24 +833,24 @@ typedef union {
|
|||
|
||||
#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
|
||||
#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
|
||||
#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
|
||||
#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
|
||||
#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
|
||||
#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
|
||||
#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
|
||||
#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
|
||||
#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
|
||||
#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
|
||||
#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
|
||||
#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
|
||||
#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
|
||||
#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
|
||||
#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
|
||||
#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
|
||||
#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
|
||||
#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
|
||||
#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
|
||||
#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
|
||||
#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
|
||||
#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
|
||||
#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
|
||||
#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
|
||||
#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
|
||||
#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
|
||||
#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
|
||||
|
@ -871,7 +868,7 @@ typedef union {
|
|||
|
||||
#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
|
||||
#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
|
||||
#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
|
||||
#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
|
||||
#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
|
||||
|
@ -889,7 +886,7 @@ typedef union {
|
|||
|
||||
#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
|
||||
#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
|
||||
#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
|
||||
#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
|
||||
#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
|
||||
|
@ -907,7 +904,7 @@ typedef union {
|
|||
|
||||
#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
|
||||
#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
|
||||
#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
|
||||
#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
|
||||
#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
|
||||
|
@ -930,22 +927,22 @@ typedef union {
|
|||
|
||||
#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
|
||||
#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
|
||||
#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
|
||||
#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
|
||||
#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
|
||||
#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
|
||||
#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
|
||||
#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
|
||||
#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
|
||||
#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
|
||||
#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
|
||||
#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
|
||||
#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
|
||||
#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
|
||||
#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
|
||||
#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
|
||||
#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
|
||||
#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
|
||||
#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
|
||||
#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
|
||||
#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
|
||||
#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
|
||||
#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
|
||||
#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
|
||||
#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
|
||||
|
@ -964,7 +961,7 @@ typedef union {
|
|||
|
||||
#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
|
||||
#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
|
||||
#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
|
||||
#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
|
||||
#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
|
||||
#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
|
||||
#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
|
||||
|
@ -1062,4 +1059,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_RTC_COMPONENT_ */
|
||||
#endif /* _SAMD11_RTC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for SERCOM
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM_COMPONENT_
|
||||
#define _SAMD21_SERCOM_COMPONENT_
|
||||
#ifndef _SAMD11_SERCOM_COMPONENT_
|
||||
#define _SAMD11_SERCOM_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR SERCOM */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
|
||||
/** \addtogroup SAMD11_SERCOM Serial Communication Interface */
|
||||
/*@{*/
|
||||
|
||||
#define SERCOM_U2201
|
||||
#define REV_SERCOM 0x201
|
||||
#define REV_SERCOM 0x200
|
||||
|
||||
/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -91,7 +88,7 @@ typedef union {
|
|||
#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
|
||||
#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
|
||||
|
@ -110,19 +107,19 @@ typedef union {
|
|||
#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
|
||||
#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
|
||||
#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
|
||||
#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
|
||||
#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
|
||||
#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
|
||||
|
@ -162,7 +159,7 @@ typedef union {
|
|||
#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
|
||||
#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
|
||||
#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
|
||||
|
@ -181,12 +178,12 @@ typedef union {
|
|||
#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
|
||||
#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
|
||||
#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
|
||||
#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
|
||||
#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
|
||||
#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
|
||||
#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
|
||||
|
@ -227,7 +224,7 @@ typedef union {
|
|||
#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
|
||||
#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
|
||||
#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
|
||||
#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
|
||||
|
@ -246,13 +243,13 @@ typedef union {
|
|||
#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
|
||||
#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
|
||||
#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
|
||||
#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
|
||||
#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
|
||||
#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
|
||||
#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
|
||||
#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
|
||||
#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
|
||||
#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
|
||||
#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
|
||||
#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
|
||||
#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
|
||||
|
@ -296,7 +293,7 @@ typedef union {
|
|||
#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
|
||||
#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
|
||||
#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
|
||||
#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
|
||||
|
@ -315,19 +312,19 @@ typedef union {
|
|||
#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
|
||||
#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
|
||||
#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
|
||||
#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
|
||||
#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
|
||||
#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
|
||||
#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
|
||||
#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
|
||||
#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
|
||||
#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
|
||||
#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
|
||||
#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
|
||||
#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
|
||||
#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
|
||||
#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
|
||||
#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
|
||||
#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
|
||||
#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
|
||||
#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
|
||||
#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
|
||||
#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
|
||||
#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
|
||||
#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
|
||||
#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
|
||||
|
@ -361,7 +358,7 @@ typedef union {
|
|||
#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
|
||||
#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
|
||||
#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
|
||||
#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
|
||||
#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
|
||||
#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
|
||||
#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
|
||||
|
@ -395,10 +392,10 @@ typedef union {
|
|||
#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
|
||||
#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
|
||||
#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
|
||||
#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
|
||||
#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
|
||||
#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
|
||||
#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
|
||||
#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
|
||||
|
@ -428,7 +425,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
|
||||
#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
|
||||
#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
|
||||
#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
|
||||
|
@ -437,7 +434,7 @@ typedef union {
|
|||
#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
|
||||
#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
|
||||
#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
|
||||
#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
|
||||
#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
|
||||
#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
|
||||
#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
|
||||
#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
|
||||
|
@ -469,7 +466,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
|
||||
#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
|
||||
#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
|
||||
#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
|
||||
#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
|
||||
#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
|
||||
#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
|
||||
|
@ -504,16 +501,16 @@ typedef union {
|
|||
|
||||
#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
|
||||
#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
|
||||
#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
|
||||
#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
|
||||
|
@ -531,7 +528,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
|
||||
#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
|
||||
#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
|
||||
#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
|
||||
#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
|
||||
|
@ -560,31 +557,31 @@ typedef union {
|
|||
|
||||
#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
|
||||
|
||||
// FRAC mode
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
|
||||
#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
|
||||
#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
|
||||
#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
|
||||
|
||||
// FRACFP mode
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
|
||||
#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
|
||||
|
||||
// USARTFP mode
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
|
||||
|
@ -602,7 +599,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
|
||||
#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
|
||||
#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
|
||||
#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
|
||||
#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
|
||||
|
@ -841,12 +838,12 @@ typedef union {
|
|||
|
||||
/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
|
||||
uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
|
||||
uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
|
||||
__I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
|
||||
__I uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_I2CM_INTFLAG_Type;
|
||||
|
@ -865,13 +862,13 @@ typedef union {
|
|||
|
||||
/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
|
||||
uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
|
||||
uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
|
||||
uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
|
||||
__I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
|
||||
__I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
|
||||
__I uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_I2CS_INTFLAG_Type;
|
||||
|
@ -892,14 +889,14 @@ typedef union {
|
|||
|
||||
/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
|
||||
uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
__I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
__I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
__I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
|
||||
__I uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_SPI_INTFLAG_Type;
|
||||
|
@ -922,16 +919,16 @@ typedef union {
|
|||
|
||||
/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
|
||||
uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
|
||||
uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
|
||||
uint8_t :1; /*!< bit: 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
__I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
__I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
__I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
|
||||
__I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
|
||||
__I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
|
||||
__I uint8_t :1; /*!< bit: 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_USART_INTFLAG_Type;
|
||||
|
@ -987,7 +984,7 @@ typedef union {
|
|||
#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
|
||||
#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
|
||||
#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
|
||||
#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
|
||||
|
@ -1210,7 +1207,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
|
||||
#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
|
||||
#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
|
||||
#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
|
||||
#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
|
||||
#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
|
||||
#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
|
||||
|
@ -1219,7 +1216,7 @@ typedef union {
|
|||
#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
|
||||
#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
|
||||
#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
|
||||
#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
|
||||
#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
|
||||
#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
|
||||
|
@ -1245,12 +1242,12 @@ typedef union {
|
|||
#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
|
||||
#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
|
||||
#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
|
||||
#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
|
||||
#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
|
||||
#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
|
||||
|
@ -1271,10 +1268,10 @@ typedef union {
|
|||
|
||||
#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
|
||||
#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
|
||||
#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
|
||||
#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
|
||||
#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
|
||||
|
@ -1292,7 +1289,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
|
||||
#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
|
||||
#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
|
||||
#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
|
||||
#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
|
||||
|
@ -1310,7 +1307,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
|
||||
#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
|
||||
#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
|
||||
#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
|
||||
#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
|
||||
|
@ -1329,7 +1326,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
|
||||
#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
|
||||
#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
|
||||
#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
|
||||
#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
|
||||
|
@ -1348,7 +1345,7 @@ typedef union {
|
|||
|
||||
#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
|
||||
#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
|
||||
#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
|
||||
#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
|
||||
#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
|
||||
|
@ -1508,4 +1505,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_SERCOM_COMPONENT_ */
|
||||
#endif /* _SAMD11_SERCOM_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for SYSCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SYSCTRL_COMPONENT_
|
||||
#define _SAMD21_SYSCTRL_COMPONENT_
|
||||
#ifndef _SAMD11_SYSCTRL_COMPONENT_
|
||||
#define _SAMD11_SYSCTRL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR SYSCTRL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_SYSCTRL System Control */
|
||||
/** \addtogroup SAMD11_SYSCTRL System Control */
|
||||
/*@{*/
|
||||
|
||||
#define SYSCTRL_U2100
|
||||
#define REV_SYSCTRL 0x201
|
||||
#define REV_SYSCTRL 0x202
|
||||
|
||||
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -180,25 +177,25 @@ typedef union {
|
|||
|
||||
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
|
||||
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
|
||||
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
|
||||
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
|
||||
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
|
||||
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
|
||||
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
|
||||
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
|
||||
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
|
||||
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
|
||||
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
|
||||
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
|
||||
uint32_t :3; /*!< bit: 12..14 Reserved */
|
||||
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
|
||||
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
|
||||
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
|
||||
uint32_t :14; /*!< bit: 18..31 Reserved */
|
||||
__I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
|
||||
__I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
|
||||
__I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
|
||||
__I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
|
||||
__I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
|
||||
__I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
|
||||
__I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
|
||||
__I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
|
||||
__I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
|
||||
__I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
|
||||
__I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
|
||||
__I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
|
||||
__I uint32_t :3; /*!< bit: 12..14 Reserved */
|
||||
__I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
|
||||
__I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
|
||||
__I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
|
||||
__I uint32_t :14; /*!< bit: 18..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} SYSCTRL_INTFLAG_Type;
|
||||
|
@ -331,7 +328,7 @@ typedef union {
|
|||
#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
|
||||
#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
|
||||
#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
|
||||
#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
|
||||
#define SYSCTRL_XOSC_GAIN(value) (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
|
||||
#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */
|
||||
#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */
|
||||
#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */
|
||||
|
@ -346,7 +343,7 @@ typedef union {
|
|||
#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
|
||||
#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
|
||||
#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
|
||||
#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
|
||||
#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
|
||||
#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
|
||||
|
@ -389,7 +386,7 @@ typedef union {
|
|||
#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
|
||||
#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
|
||||
#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
|
||||
#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
|
||||
#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
|
||||
#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
|
||||
#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
|
||||
#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */
|
||||
|
@ -431,12 +428,12 @@ typedef union {
|
|||
#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
|
||||
#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
|
||||
#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
|
||||
#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
|
||||
#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
|
||||
#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
|
||||
#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
|
||||
#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
|
||||
#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
|
||||
#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
|
||||
#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
|
||||
#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
|
||||
|
@ -456,7 +453,7 @@ typedef union {
|
|||
|
||||
#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
|
||||
#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
|
||||
#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
|
||||
#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
|
||||
#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
|
||||
#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
|
||||
#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
|
||||
|
@ -491,7 +488,7 @@ typedef union {
|
|||
#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
|
||||
#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
|
||||
#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
|
||||
#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
|
||||
#define SYSCTRL_OSC8M_PRESC(value) (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
|
||||
#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */
|
||||
#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */
|
||||
#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */
|
||||
|
@ -502,10 +499,10 @@ typedef union {
|
|||
#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
|
||||
#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
|
||||
#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
|
||||
#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
|
||||
#define SYSCTRL_OSC8M_CALIB(value) (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
|
||||
#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
|
||||
#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
|
||||
#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
|
||||
#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
|
||||
#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
|
||||
#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
|
||||
#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
|
||||
|
@ -582,13 +579,13 @@ typedef union {
|
|||
|
||||
#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
|
||||
#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
|
||||
#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
|
||||
#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
|
||||
#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
|
||||
#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
|
||||
#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
|
||||
#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
|
||||
#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
|
||||
#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
|
||||
#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
|
||||
#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
|
||||
#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
|
||||
|
@ -608,13 +605,13 @@ typedef union {
|
|||
|
||||
#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
|
||||
#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
|
||||
#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
|
||||
#define SYSCTRL_DFLLMUL_MUL(value) (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
|
||||
#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
|
||||
#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
|
||||
#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
|
||||
#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
|
||||
#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
|
||||
#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
|
||||
#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
|
||||
#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
|
||||
#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
|
||||
|
@ -666,7 +663,7 @@ typedef union {
|
|||
#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos)
|
||||
#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
|
||||
#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
|
||||
#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
|
||||
#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
|
||||
#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */
|
||||
#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
|
||||
#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
|
||||
|
@ -681,7 +678,7 @@ typedef union {
|
|||
#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos)
|
||||
#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
|
||||
#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos)
|
||||
#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
|
||||
#define SYSCTRL_BOD33_PSEL(value) (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
|
||||
#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
|
||||
#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
|
||||
#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
|
||||
|
@ -716,32 +713,9 @@ typedef union {
|
|||
#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
|
||||
#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
|
||||
#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
|
||||
#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
|
||||
#define SYSCTRL_BOD33_LEVEL(value) (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
|
||||
#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t :6; /*!< bit: 0.. 5 Reserved */
|
||||
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
|
||||
uint16_t :6; /*!< bit: 7..12 Reserved */
|
||||
uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} SYSCTRL_VREG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
|
||||
#define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
|
||||
|
||||
#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
|
||||
#define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
|
||||
#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
|
||||
#define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
|
||||
#define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
|
@ -766,7 +740,7 @@ typedef union {
|
|||
#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
|
||||
#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
|
||||
#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
|
||||
#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
|
||||
#define SYSCTRL_VREF_CALIB(value) (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
|
||||
#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
|
||||
|
@ -812,10 +786,10 @@ typedef union {
|
|||
|
||||
#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
|
||||
#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
|
||||
#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
|
||||
#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
|
||||
#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
|
||||
|
@ -843,7 +817,7 @@ typedef union {
|
|||
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
|
||||
|
@ -858,7 +832,7 @@ typedef union {
|
|||
#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
|
||||
|
@ -867,13 +841,13 @@ typedef union {
|
|||
#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_NONE_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default No time-out */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) 8MS Time-out if no lock within 8 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) 9MS Time-out if no lock within 9 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) 10MS Time-out if no lock within 10 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) 11MS Time-out if no lock within 11 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_NONE (SYSCTRL_DPLLCTRLB_LTIME_NONE_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
|
@ -882,7 +856,7 @@ typedef union {
|
|||
#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
|
||||
#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
|
||||
|
@ -934,12 +908,10 @@ typedef struct {
|
|||
__IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
|
||||
RoReg8 Reserved5[0x3];
|
||||
__IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
RoReg8 Reserved6[0x4];
|
||||
__IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
|
||||
RoReg8 Reserved7[0x2];
|
||||
RoReg8 Reserved6[0x8];
|
||||
__IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
|
||||
__IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
|
||||
RoReg8 Reserved8[0x3];
|
||||
RoReg8 Reserved7[0x3];
|
||||
__IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
|
||||
__IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
|
||||
__I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
|
||||
|
@ -948,4 +920,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
|
||||
#endif /* _SAMD11_SYSCTRL_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for TC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC_COMPONENT_
|
||||
#define _SAMD21_TC_COMPONENT_
|
||||
#ifndef _SAMD11_TC_COMPONENT_
|
||||
#define _SAMD11_TC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR TC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_TC Basic Timer Counter */
|
||||
/** \addtogroup SAMD11_TC Basic Timer Counter */
|
||||
/*@{*/
|
||||
|
||||
#define TC_U2212
|
||||
#define REV_TC 0x131
|
||||
#define REV_TC 0x140
|
||||
|
||||
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -84,7 +81,7 @@ typedef union {
|
|||
#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
|
||||
#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
|
||||
#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
|
||||
#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
|
||||
#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
|
||||
#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
|
||||
#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
|
||||
#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
|
||||
|
@ -93,7 +90,7 @@ typedef union {
|
|||
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
|
||||
#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
|
||||
#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
|
||||
#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
|
||||
#define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
|
||||
#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
|
||||
#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
|
||||
#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
|
||||
|
@ -104,7 +101,7 @@ typedef union {
|
|||
#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
|
||||
#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
|
||||
#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
|
||||
#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
|
||||
#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
|
||||
#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
|
||||
#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
|
||||
#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
|
||||
|
@ -125,7 +122,7 @@ typedef union {
|
|||
#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
|
||||
#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
|
||||
#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
|
||||
#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
|
||||
#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
|
||||
#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
|
||||
#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
|
||||
#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
|
||||
|
@ -152,7 +149,7 @@ typedef union {
|
|||
|
||||
#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
|
||||
#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
|
||||
#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
|
||||
#define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
|
||||
#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
|
||||
#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
|
||||
#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
|
||||
|
@ -182,7 +179,7 @@ typedef union {
|
|||
#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
|
||||
#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
|
||||
#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
|
||||
#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
|
||||
#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
|
||||
#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
|
||||
#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
|
||||
#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
|
||||
|
@ -214,7 +211,7 @@ typedef union {
|
|||
#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
|
||||
#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
|
||||
#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
|
||||
#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
|
||||
#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
|
||||
#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
|
||||
#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
|
||||
#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
|
||||
|
@ -253,14 +250,14 @@ typedef union {
|
|||
#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
|
||||
#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
|
||||
#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
|
||||
#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
|
||||
#define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
|
||||
#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
|
||||
#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
|
||||
#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
|
||||
#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
|
||||
#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
|
||||
#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
|
||||
#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
|
||||
#define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
|
||||
#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
|
||||
|
||||
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
|
||||
|
@ -310,7 +307,7 @@ typedef union {
|
|||
|
||||
#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
|
||||
#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
|
||||
#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
|
||||
#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
|
||||
#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
|
||||
#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
|
||||
#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
|
||||
|
@ -335,7 +332,7 @@ typedef union {
|
|||
#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
|
||||
#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
|
||||
#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
|
||||
#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
|
||||
#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
|
||||
#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
|
||||
|
@ -374,7 +371,7 @@ typedef union {
|
|||
#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
|
||||
#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
|
||||
#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
|
||||
#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
|
||||
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
|
||||
#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
|
||||
|
@ -413,25 +410,25 @@ typedef union {
|
|||
#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
|
||||
#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
||||
#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
|
||||
#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
|
||||
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
|
||||
#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t OVF:1; /*!< bit: 0 Overflow */
|
||||
uint8_t ERR:1; /*!< bit: 1 Error */
|
||||
uint8_t :1; /*!< bit: 2 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
|
||||
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint8_t OVF:1; /*!< bit: 0 Overflow */
|
||||
__I uint8_t ERR:1; /*!< bit: 1 Error */
|
||||
__I uint8_t :1; /*!< bit: 2 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
__I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
|
||||
__I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
|
||||
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
||||
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
||||
__I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
|
||||
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} TC_INTFLAG_Type;
|
||||
|
@ -452,7 +449,7 @@ typedef union {
|
|||
#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
|
||||
#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
|
||||
#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
|
||||
#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
|
||||
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
|
||||
#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
|
||||
|
@ -495,7 +492,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
|
||||
#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
|
||||
#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
|
||||
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
|
||||
#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
|
||||
|
@ -513,7 +510,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
|
||||
#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
|
||||
#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
|
||||
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
|
||||
#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
|
||||
|
@ -531,7 +528,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
|
||||
#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
|
||||
#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
|
||||
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
|
||||
#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
|
||||
|
@ -549,7 +546,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
|
||||
#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
|
||||
#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
|
||||
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
|
||||
#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
|
||||
|
@ -567,7 +564,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
|
||||
#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
|
||||
#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
|
||||
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
|
||||
#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
|
||||
|
@ -585,7 +582,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
|
||||
#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
|
||||
#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
|
||||
#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
|
||||
#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
|
||||
|
@ -603,7 +600,7 @@ typedef union {
|
|||
|
||||
#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
|
||||
#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
|
||||
#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
|
||||
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
|
||||
#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
|
||||
|
||||
/** \brief TC_COUNT8 hardware registers */
|
||||
|
@ -684,4 +681,4 @@ typedef union {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_TC_COMPONENT_ */
|
||||
#endif /* _SAMD11_TC_COMPONENT_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for TCC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,21 +40,18 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC_COMPONENT_
|
||||
#define _SAMD21_TCC_COMPONENT_
|
||||
#ifndef _SAMD11_TCC_COMPONENT_
|
||||
#define _SAMD11_TCC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR TCC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_TCC Timer Counter Control */
|
||||
/** \addtogroup SAMD11_TCC Timer Counter Control */
|
||||
/*@{*/
|
||||
|
||||
#define TCC_U2213
|
||||
#define REV_TCC 0x121
|
||||
#define REV_TCC 0x111
|
||||
|
||||
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -94,7 +91,7 @@ typedef union {
|
|||
#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
|
||||
#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
|
||||
#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
|
||||
#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
|
||||
#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
|
||||
#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
|
||||
#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
|
||||
#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
|
||||
|
@ -105,7 +102,7 @@ typedef union {
|
|||
#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
|
||||
#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
|
||||
#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
|
||||
#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
|
||||
#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
|
||||
#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
|
||||
#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
|
||||
#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
|
||||
|
@ -126,7 +123,7 @@ typedef union {
|
|||
#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
|
||||
#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
|
||||
#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
|
||||
#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
|
||||
#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
|
||||
#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
|
||||
#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
|
||||
#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
|
||||
|
@ -145,7 +142,7 @@ typedef union {
|
|||
#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
|
||||
#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
|
||||
#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
|
||||
#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
|
||||
#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
|
||||
#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
|
||||
|
@ -173,7 +170,7 @@ typedef union {
|
|||
#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
|
||||
#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
|
||||
#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
|
||||
#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
|
||||
#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
|
||||
#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
|
||||
#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
|
||||
#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
|
||||
|
@ -184,11 +181,11 @@ typedef union {
|
|||
#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
|
||||
#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
|
||||
#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
|
||||
#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
|
||||
#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
|
||||
#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
|
||||
#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
|
||||
#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */
|
||||
#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
|
||||
#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
|
||||
|
@ -222,7 +219,7 @@ typedef union {
|
|||
#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
|
||||
#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
|
||||
#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
|
||||
#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
|
||||
#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
|
||||
#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
|
||||
#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
|
||||
#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
|
||||
|
@ -233,11 +230,11 @@ typedef union {
|
|||
#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
|
||||
#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
|
||||
#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
|
||||
#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
|
||||
#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
|
||||
#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
|
||||
#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
|
||||
#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */
|
||||
#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
|
||||
#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
|
||||
|
@ -312,7 +309,7 @@ typedef union {
|
|||
#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
|
||||
#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
|
||||
#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
|
||||
#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
|
||||
#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
|
||||
#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
|
||||
#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
|
||||
#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
|
||||
|
@ -329,7 +326,7 @@ typedef union {
|
|||
#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
|
||||
#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
|
||||
#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
|
||||
#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
|
||||
#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
|
||||
#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
|
||||
|
@ -345,7 +342,7 @@ typedef union {
|
|||
uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
|
||||
uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
|
||||
uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
|
||||
uint32_t :1; /*!< bit: 15 Reserved */
|
||||
uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */
|
||||
uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
|
||||
uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
|
@ -359,7 +356,7 @@ typedef union {
|
|||
|
||||
#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
|
||||
#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
|
||||
#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
|
||||
#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
|
||||
#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
|
||||
#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
|
||||
#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
|
||||
|
@ -374,12 +371,12 @@ typedef union {
|
|||
#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
|
||||
#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
|
||||
#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
|
||||
#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */
|
||||
#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
|
||||
#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
|
||||
#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
|
@ -387,7 +384,7 @@ typedef union {
|
|||
#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
|
||||
#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
|
||||
#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
|
||||
#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
|
||||
#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
|
||||
#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
|
||||
#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
|
||||
#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
|
||||
|
@ -398,7 +395,7 @@ typedef union {
|
|||
#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
|
||||
#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
|
||||
#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
|
||||
#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
|
||||
#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
|
||||
#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
|
||||
#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
|
||||
#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
|
||||
|
@ -409,7 +406,7 @@ typedef union {
|
|||
#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
|
||||
#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
|
||||
#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
|
||||
#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
|
||||
|
@ -417,6 +414,7 @@ typedef union {
|
|||
#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */
|
||||
#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */
|
||||
#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
|
||||
#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
|
@ -424,13 +422,16 @@ typedef union {
|
|||
#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */
|
||||
#define TCC_FCTRLA_BLANKPRESC (0x1ul << TCC_FCTRLA_BLANKPRESC_Pos)
|
||||
#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
|
||||
#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
|
||||
#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
|
||||
#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
|
||||
#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
|
||||
#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
|
||||
#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
|
||||
#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
|
||||
#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
|
||||
#define TCC_FCTRLA_MASK 0x0FFFFFFBul /**< \brief (TCC_FCTRLA) MASK Register */
|
||||
|
||||
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -445,7 +446,7 @@ typedef union {
|
|||
uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
|
||||
uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
|
||||
uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
|
||||
uint32_t :1; /*!< bit: 15 Reserved */
|
||||
uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */
|
||||
uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
|
||||
uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
|
@ -459,7 +460,7 @@ typedef union {
|
|||
|
||||
#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
|
||||
#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
|
||||
#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
|
||||
#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
|
||||
#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
|
||||
#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
|
||||
#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
|
||||
|
@ -474,12 +475,12 @@ typedef union {
|
|||
#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
|
||||
#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
|
||||
#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
|
||||
#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */
|
||||
#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
|
||||
#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
|
||||
#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
|
@ -487,7 +488,7 @@ typedef union {
|
|||
#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
|
||||
#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
|
||||
#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
|
||||
#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
|
||||
#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
|
||||
#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
|
||||
#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
|
||||
#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
|
||||
|
@ -498,7 +499,7 @@ typedef union {
|
|||
#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
|
||||
#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
|
||||
#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
|
||||
#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
|
||||
#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
|
||||
#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
|
||||
#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
|
||||
#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
|
||||
|
@ -509,7 +510,7 @@ typedef union {
|
|||
#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
|
||||
#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
|
||||
#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
|
||||
#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
|
||||
|
@ -517,6 +518,7 @@ typedef union {
|
|||
#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */
|
||||
#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */
|
||||
#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
|
||||
#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
|
@ -524,13 +526,16 @@ typedef union {
|
|||
#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */
|
||||
#define TCC_FCTRLB_BLANKPRESC (0x1ul << TCC_FCTRLB_BLANKPRESC_Pos)
|
||||
#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
|
||||
#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
|
||||
#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
|
||||
#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
|
||||
#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
|
||||
#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
|
||||
#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
|
||||
#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
|
||||
#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
|
||||
#define TCC_FCTRLB_MASK 0x0FFFFFFBul /**< \brief (TCC_FCTRLB) MASK Register */
|
||||
|
||||
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -560,7 +565,7 @@ typedef union {
|
|||
|
||||
#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
|
||||
#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
|
||||
#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
|
||||
#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
|
||||
#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
|
||||
#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
|
||||
|
@ -571,13 +576,13 @@ typedef union {
|
|||
#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
|
||||
#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
|
||||
#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
|
||||
#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
|
||||
#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
|
||||
#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
|
||||
#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
|
||||
#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
|
||||
#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
|
||||
#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
|
||||
#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
|
||||
#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
|
||||
|
@ -642,7 +647,7 @@ typedef union {
|
|||
#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
|
||||
#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
|
||||
#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
|
||||
#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
|
||||
#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
|
||||
#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
|
||||
#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
|
||||
#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
|
||||
|
@ -661,7 +666,7 @@ typedef union {
|
|||
#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
|
||||
#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
|
||||
#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
|
||||
#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
|
||||
#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
|
||||
#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
|
||||
#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
|
||||
#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
|
||||
|
@ -680,13 +685,13 @@ typedef union {
|
|||
#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
|
||||
#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
|
||||
#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
|
||||
#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
|
||||
#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
|
||||
#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
|
||||
#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
|
||||
#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
|
||||
#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
|
||||
#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
|
||||
#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
|
||||
#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
|
||||
#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
|
||||
#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
|
||||
|
@ -755,7 +760,7 @@ typedef union {
|
|||
|
||||
#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
|
||||
#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
|
||||
#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
|
||||
#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
|
||||
#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
|
||||
#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
|
||||
|
@ -772,7 +777,7 @@ typedef union {
|
|||
#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
|
||||
#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
|
||||
#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
|
||||
#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
|
||||
#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
|
||||
#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
|
||||
#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
|
||||
|
@ -791,7 +796,7 @@ typedef union {
|
|||
#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
|
||||
#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
|
||||
#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
|
||||
#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
|
||||
#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
|
||||
#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
|
||||
#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
|
||||
#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
|
||||
|
@ -812,14 +817,14 @@ typedef union {
|
|||
#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
|
||||
#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
|
||||
#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
|
||||
#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
|
||||
#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
|
||||
#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
|
||||
#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
|
||||
#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
|
||||
#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
|
||||
#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
|
||||
#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
|
||||
#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
|
||||
#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
|
||||
#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
|
||||
#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
|
||||
#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
|
||||
|
@ -830,7 +835,7 @@ typedef union {
|
|||
#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
|
||||
#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
|
||||
#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
|
||||
#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
|
||||
#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
|
||||
#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
|
||||
#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
|
||||
#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
|
||||
|
@ -841,7 +846,7 @@ typedef union {
|
|||
#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
|
||||
#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
|
||||
#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
|
||||
#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
|
||||
#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
|
||||
#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
|
||||
|
@ -904,7 +909,7 @@ typedef union {
|
|||
#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
|
||||
#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
|
||||
#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
|
||||
#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
|
||||
#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
|
||||
#define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
|
||||
|
@ -967,33 +972,33 @@ typedef union {
|
|||
#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
|
||||
#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
||||
#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
|
||||
#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
|
||||
#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
|
||||
#define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t OVF:1; /*!< bit: 0 Overflow */
|
||||
uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
||||
uint32_t CNT:1; /*!< bit: 2 Counter */
|
||||
uint32_t ERR:1; /*!< bit: 3 Error */
|
||||
uint32_t :7; /*!< bit: 4..10 Reserved */
|
||||
uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
||||
uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
|
||||
uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
|
||||
uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
||||
uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
||||
uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
||||
uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
||||
uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
||||
uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
__I uint32_t OVF:1; /*!< bit: 0 Overflow */
|
||||
__I uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
||||
__I uint32_t CNT:1; /*!< bit: 2 Counter */
|
||||
__I uint32_t ERR:1; /*!< bit: 3 Error */
|
||||
__I uint32_t :7; /*!< bit: 4..10 Reserved */
|
||||
__I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
||||
__I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
|
||||
__I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
|
||||
__I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
||||
__I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
||||
__I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
||||
__I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
||||
__I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
||||
__I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
||||
__I uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
__I uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
__I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
||||
__I uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} TCC_INTFLAG_Type;
|
||||
|
@ -1030,7 +1035,7 @@ typedef union {
|
|||
#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
|
||||
#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
|
||||
#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
|
||||
#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
|
||||
#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
|
||||
#define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
|
||||
|
@ -1118,7 +1123,7 @@ typedef union {
|
|||
#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
|
||||
#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
|
||||
#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
|
||||
#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
|
||||
#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
|
||||
#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
|
||||
#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
|
||||
#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
|
||||
|
@ -1129,7 +1134,7 @@ typedef union {
|
|||
#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
|
||||
#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
|
||||
#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
|
||||
#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
|
||||
#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
|
||||
#define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */
|
||||
|
||||
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
|
||||
|
@ -1164,24 +1169,24 @@ typedef union {
|
|||
// DITH4 mode
|
||||
#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
|
||||
#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
|
||||
#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
|
||||
#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
|
||||
|
||||
#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
|
||||
#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
|
||||
#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
|
||||
#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
|
||||
#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
|
||||
|
||||
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
|
||||
|
@ -1234,7 +1239,7 @@ typedef union {
|
|||
#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
|
||||
#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
|
||||
#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
|
||||
#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
|
||||
#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
|
||||
#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
|
||||
#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
|
||||
#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
|
||||
|
@ -1253,7 +1258,7 @@ typedef union {
|
|||
#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
|
||||
#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
|
||||
#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
|
||||
#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
|
||||
#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
|
||||
#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
|
||||
|
||||
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
|
||||
|
@ -1299,7 +1304,7 @@ typedef union {
|
|||
|
||||
#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
|
||||
#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
|
||||
#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
|
||||
#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
|
||||
#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
|
||||
#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
|
||||
#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
|
||||
|
@ -1316,13 +1321,15 @@ typedef union {
|
|||
#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
|
||||
#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
|
||||
#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
|
||||
#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
|
||||
#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
|
||||
#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos)
|
||||
#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
|
||||
|
@ -1335,7 +1342,7 @@ typedef union {
|
|||
#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
|
||||
#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
|
||||
#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
|
||||
#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
|
||||
#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
|
||||
#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
|
||||
#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
|
||||
#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
|
||||
|
@ -1346,7 +1353,7 @@ typedef union {
|
|||
#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
|
||||
#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
|
||||
#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
|
||||
#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
|
||||
#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
|
||||
#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
|
||||
#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
|
||||
#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
|
||||
|
@ -1357,7 +1364,7 @@ typedef union {
|
|||
#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
|
||||
#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
|
||||
#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
|
||||
#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
|
||||
#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
|
||||
#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
|
||||
|
||||
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
|
||||
|
@ -1392,33 +1399,33 @@ typedef union {
|
|||
// DITH4 mode
|
||||
#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
|
||||
#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
|
||||
#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)))
|
||||
#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
|
||||
#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
|
||||
#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
|
||||
#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)))
|
||||
#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
|
||||
#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
|
||||
#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
|
||||
#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)))
|
||||
#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
|
||||
#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
|
||||
|
||||
#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
|
||||
#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
|
||||
#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
|
||||
#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
|
||||
#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
|
||||
|
||||
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
|
||||
|
@ -1453,33 +1460,33 @@ typedef union {
|
|||
// DITH4 mode
|
||||
#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
|
||||
#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)))
|
||||
#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
|
||||
#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
|
||||
#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)))
|
||||
#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
|
||||
#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
|
||||
#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)))
|
||||
#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
|
||||
#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
|
||||
|
||||
#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
|
||||
#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
|
||||
#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
|
||||
#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
|
||||
#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
|
||||
|
||||
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
|
||||
|
@ -1532,7 +1539,7 @@ typedef union {
|
|||
#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
|
||||
#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
|
||||
#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
|
||||
#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
|
||||
#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
|
||||
#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
|
||||
#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
|
||||
#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
|
||||
|
@ -1551,7 +1558,7 @@ typedef union {
|
|||
#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
|
||||
#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
|
||||
#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
|
||||
#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
|
||||
#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
|
||||
#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
|
||||
|
||||
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
|
||||
|
@ -1597,7 +1604,7 @@ typedef union {
|
|||
|
||||
#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
|
||||
#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
|
||||
#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
|
||||
#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
|
||||
#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
|
||||
#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
|
||||
#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
|
||||
|
@ -1614,7 +1621,7 @@ typedef union {
|
|||
#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
|
||||
#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
|
||||
#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
|
||||
#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
|
||||
#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
|
||||
|
@ -1633,7 +1640,7 @@ typedef union {
|
|||
#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
|
||||
#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
|
||||
#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
|
||||
#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
|
||||
#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
|
||||
#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
|
||||
#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
|
||||
#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
|
||||
|
@ -1644,7 +1651,7 @@ typedef union {
|
|||
#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
|
||||
#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
|
||||
#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
|
||||
#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
|
||||
#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
|
||||
#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
|
||||
#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
|
||||
#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
|
||||
|
@ -1655,7 +1662,7 @@ typedef union {
|
|||
#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
|
||||
#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
|
||||
#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
|
||||
#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
|
||||
#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
|
||||
#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
|
||||
|
||||
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
|
||||
|
@ -1690,33 +1697,33 @@ typedef union {
|
|||
// DITH4 mode
|
||||
#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
|
||||
#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
|
||||
#define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)))
|
||||
#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
|
||||
#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
|
||||
#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
|
||||
#define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)))
|
||||
#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
|
||||
#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
|
||||
#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
|
||||
#define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)))
|
||||
#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
|
||||
#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
|
||||
|
||||
#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
|
||||
#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
|
||||
#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
|
||||
#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
|
||||
#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
|
||||
|
||||
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
|
||||
|
@ -1751,33 +1758,33 @@ typedef union {
|
|||
// DITH4 mode
|
||||
#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
|
||||
#define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)))
|
||||
#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
|
||||
#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
|
||||
#define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)))
|
||||
#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
|
||||
#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
|
||||
#define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)))
|
||||
#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
|
||||
#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
|
||||
|
||||
#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
|
||||
#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
|
||||
#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
|
||||
#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
|
||||
|
||||
/** \brief TCC hardware registers */
|
||||
|
@ -1817,4 +1824,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_TCC_COMPONENT_ */
|
||||
#endif /* _SAMD11_TCC_COMPONENT_ */
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Component description for WDT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,17 +40,14 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_COMPONENT_
|
||||
#define _SAMD21_WDT_COMPONENT_
|
||||
#ifndef _SAMD11_WDT_COMPONENT_
|
||||
#define _SAMD11_WDT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR WDT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_WDT Watchdog Timer */
|
||||
/** \addtogroup SAMD11_WDT Watchdog Timer */
|
||||
/*@{*/
|
||||
|
||||
#define WDT_U2203
|
||||
|
@ -97,7 +94,7 @@ typedef union {
|
|||
|
||||
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
|
||||
#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
|
||||
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
|
||||
#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
|
@ -124,7 +121,7 @@ typedef union {
|
|||
#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
|
||||
#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
|
||||
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
|
||||
#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
|
@ -167,7 +164,7 @@ typedef union {
|
|||
|
||||
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
|
||||
#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
|
||||
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
|
||||
#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */
|
||||
|
@ -232,10 +229,10 @@ typedef union {
|
|||
|
||||
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t EW:1; /*!< bit: 0 Early Warning */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t EW:1; /*!< bit: 0 Early Warning */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTFLAG_Type;
|
||||
|
@ -281,7 +278,7 @@ typedef union {
|
|||
|
||||
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
|
||||
#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
|
||||
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
|
||||
#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */
|
||||
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */
|
||||
|
@ -303,4 +300,4 @@ typedef struct {
|
|||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_WDT_COMPONENT_ */
|
||||
#endif /* _SAMD11_WDT_COMPONENT_ */
|
||||
|
|
|
@ -1,51 +1,36 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
* @version V4.00
|
||||
* @date 22. August 2014
|
||||
* @version V3.01
|
||||
* @date 22. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
|
@ -68,8 +53,8 @@
|
|||
*/
|
||||
|
||||
/* CMSIS CM0P definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
|
||||
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
|
||||
|
||||
|
@ -81,18 +66,14 @@
|
|||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
@ -100,16 +81,9 @@
|
|||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0
|
||||
|
||||
|
@ -118,18 +92,13 @@
|
|||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI__VFP_SUPPORT____
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
|
@ -137,21 +106,12 @@
|
|||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ ) /* Cosmic */
|
||||
#if ( __CSMC__ & 0x400) // FPU present for parser
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <stdint.h> /* standard types definitions */
|
||||
#include <core_cmInstr.h> /* Core Instruction Access */
|
||||
#include <core_cmFunc.h> /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
@ -159,10 +119,6 @@
|
|||
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
|
@ -405,8 +361,8 @@ typedef struct
|
|||
|
||||
#if (__VTOR_PRESENT == 1)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
|
@ -494,7 +450,7 @@ typedef struct
|
|||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
@ -745,9 +701,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
|||
{
|
||||
|
||||
if(IRQn < 0) {
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
|
||||
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
|
||||
else {
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||
}
|
||||
|
||||
|
||||
|
@ -795,9 +751,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
|||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||
|
||||
SysTick->LOAD = ticks - 1; /* set reload register */
|
||||
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
|
@ -813,10 +769,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,46 +1,32 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.00
|
||||
* @date 28. August 2014
|
||||
* @version V3.00
|
||||
* @date 19. January 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
@ -196,9 +182,9 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
|||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
|
@ -240,7 +226,7 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
|||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
|
@ -267,10 +253,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
|||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
|
@ -303,7 +289,19 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
|||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
|
@ -316,7 +314,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
|
@ -327,7 +325,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
|
@ -354,7 +352,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
|
@ -416,7 +414,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
|||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
|
@ -426,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
|
@ -443,7 +441,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
|||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
|
@ -453,7 +451,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
|
@ -480,9 +478,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
|
@ -493,7 +491,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t p
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
|
@ -504,7 +502,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
|
@ -517,7 +515,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
@ -531,7 +529,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
|
@ -544,7 +542,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
@ -558,13 +556,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
|
@ -577,10 +575,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
|||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
__ASM volatile ("");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
|
@ -597,41 +592,25 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
/* Empty asm statement works as a scheduling barrier */
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
||||
__ASM volatile ("");
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
|
@ -1,39 +1,25 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.00
|
||||
* @date 28. August 2014
|
||||
* @version V3.00
|
||||
* @date 07. February 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
@ -125,13 +111,12 @@
|
|||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
|
@ -140,13 +125,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
|
|||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
@ -160,18 +143,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
#define __ROR __ror
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
|
@ -185,7 +157,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
|
@ -195,7 +167,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
|
@ -205,7 +177,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
|
@ -215,7 +187,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
|
@ -227,7 +199,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
|
@ -239,7 +211,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
|
@ -288,99 +260,25 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
|||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/* Define macros for porting to both thumb1 and thumb2.
|
||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
||||
* Otherwise, use general registers, specified by constrant "r" */
|
||||
#if defined (__thumb__) && !defined (__thumb2__)
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
||||
#else
|
||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
||||
#endif
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
|
@ -466,14 +364,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
@ -488,7 +382,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
@ -502,14 +396,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (short)__builtin_bswap16(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
@ -523,22 +413,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << (32 - op2));
|
||||
|
||||
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||
return(op1);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
|
@ -558,53 +439,39 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
|
|||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 8 bit value.
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
uint8_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 16 bit values.
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
uint16_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive LDR instruction for 32 bit values.
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
|
@ -613,14 +480,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 8 bit values.
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
|
@ -631,14 +498,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 16 bit values.
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
|
@ -649,14 +516,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function executes a exclusive STR instruction for 32 bit values.
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
|
@ -667,7 +534,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
@ -679,7 +546,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
|
@ -724,155 +591,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
|||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
|
||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||
/* Cosmic specific functions */
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for AC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,51 +40,48 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC_INSTANCE_
|
||||
#define _SAMD21_AC_INSTANCE_
|
||||
#ifndef _SAMD11_AC_INSTANCE_
|
||||
#define _SAMD11_AC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for AC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */
|
||||
#define REG_AC_CTRLA (0x42002400U) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (0x42002401U) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (0x42002402U) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (0x42002404U) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (0x42002405U) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (0x42002406U) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (0x42002408U) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (0x42002409U) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (0x4200240AU) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (0x4200240CU) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (0x42002410U) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (0x42002414U) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (0x42002420U) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (0x42002421U) /**< \brief (AC) Scaler 1 */
|
||||
#else
|
||||
#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
|
||||
#define REG_AC_CTRLA (*(RwReg8 *)0x42002400U) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (*(WoReg8 *)0x42002401U) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (*(RwReg16*)0x42002402U) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (*(RwReg8 *)0x42002404U) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (*(RwReg8 *)0x42002405U) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (*(RwReg8 *)0x42002406U) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (*(RoReg8 *)0x42002408U) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (*(RoReg8 *)0x42002409U) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (*(RoReg8 *)0x4200240AU) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200240CU) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42002410U) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42002414U) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (*(RwReg8 *)0x42002420U) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (*(RwReg8 *)0x42002421U) /**< \brief (AC) Scaler 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for AC peripheral ========== */
|
||||
#define AC_CMP_NUM 2 // Number of comparators
|
||||
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
|
||||
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
|
||||
#define AC_GCLK_ID_ANA 21 // Index of Generic Clock for analog
|
||||
#define AC_GCLK_ID_DIG 20 // Index of Generic Clock for digital
|
||||
#define AC_NUM_CMP 2
|
||||
#define AC_PAIRS 1 // Number of pairs of comparators
|
||||
|
||||
#endif /* _SAMD21_AC_INSTANCE_ */
|
||||
#endif /* _SAMD11_AC_INSTANCE_ */
|
||||
|
|
|
@ -1,87 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for AC1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC1_INSTANCE_
|
||||
#define _SAMD21_AC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for AC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_AC1_CTRLA (0x42005400U) /**< \brief (AC1) Control A */
|
||||
#define REG_AC1_CTRLB (0x42005401U) /**< \brief (AC1) Control B */
|
||||
#define REG_AC1_EVCTRL (0x42005402U) /**< \brief (AC1) Event Control */
|
||||
#define REG_AC1_INTENCLR (0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
|
||||
#define REG_AC1_INTENSET (0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
|
||||
#define REG_AC1_INTFLAG (0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
|
||||
#define REG_AC1_STATUSA (0x42005408U) /**< \brief (AC1) Status A */
|
||||
#define REG_AC1_STATUSB (0x42005409U) /**< \brief (AC1) Status B */
|
||||
#define REG_AC1_STATUSC (0x4200540AU) /**< \brief (AC1) Status C */
|
||||
#define REG_AC1_WINCTRL (0x4200540CU) /**< \brief (AC1) Window Control */
|
||||
#define REG_AC1_COMPCTRL0 (0x42005410U) /**< \brief (AC1) Comparator Control 0 */
|
||||
#define REG_AC1_COMPCTRL1 (0x42005414U) /**< \brief (AC1) Comparator Control 1 */
|
||||
#define REG_AC1_SCALER0 (0x42005420U) /**< \brief (AC1) Scaler 0 */
|
||||
#define REG_AC1_SCALER1 (0x42005421U) /**< \brief (AC1) Scaler 1 */
|
||||
#else
|
||||
#define REG_AC1_CTRLA (*(RwReg8 *)0x42005400U) /**< \brief (AC1) Control A */
|
||||
#define REG_AC1_CTRLB (*(WoReg8 *)0x42005401U) /**< \brief (AC1) Control B */
|
||||
#define REG_AC1_EVCTRL (*(RwReg16*)0x42005402U) /**< \brief (AC1) Event Control */
|
||||
#define REG_AC1_INTENCLR (*(RwReg8 *)0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */
|
||||
#define REG_AC1_INTENSET (*(RwReg8 *)0x42005405U) /**< \brief (AC1) Interrupt Enable Set */
|
||||
#define REG_AC1_INTFLAG (*(RwReg8 *)0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */
|
||||
#define REG_AC1_STATUSA (*(RoReg8 *)0x42005408U) /**< \brief (AC1) Status A */
|
||||
#define REG_AC1_STATUSB (*(RoReg8 *)0x42005409U) /**< \brief (AC1) Status B */
|
||||
#define REG_AC1_STATUSC (*(RoReg8 *)0x4200540AU) /**< \brief (AC1) Status C */
|
||||
#define REG_AC1_WINCTRL (*(RwReg8 *)0x4200540CU) /**< \brief (AC1) Window Control */
|
||||
#define REG_AC1_COMPCTRL0 (*(RwReg *)0x42005410U) /**< \brief (AC1) Comparator Control 0 */
|
||||
#define REG_AC1_COMPCTRL1 (*(RwReg *)0x42005414U) /**< \brief (AC1) Comparator Control 1 */
|
||||
#define REG_AC1_SCALER0 (*(RwReg8 *)0x42005420U) /**< \brief (AC1) Scaler 0 */
|
||||
#define REG_AC1_SCALER1 (*(RwReg8 *)0x42005421U) /**< \brief (AC1) Scaler 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for AC1 peripheral ========== */
|
||||
#define AC1_CMP_NUM 2 // Number of comparators
|
||||
#define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog
|
||||
#define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital
|
||||
#define AC1_NUM_CMP 2
|
||||
#define AC1_PAIRS 1 // Number of pairs of comparators
|
||||
|
||||
#endif /* _SAMD21_AC1_INSTANCE_ */
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for ADC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,63 +40,60 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_INSTANCE_
|
||||
#define _SAMD21_ADC_INSTANCE_
|
||||
#ifndef _SAMD11_ADC_INSTANCE_
|
||||
#define _SAMD11_ADC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */
|
||||
#define REG_ADC_CTRLA (0x42002000U) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (0x42002001U) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (0x42002002U) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (0x42002003U) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (0x42002004U) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (0x42002008U) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (0x4200200CU) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (0x42002010U) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (0x42002014U) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (0x42002016U) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (0x42002017U) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (0x42002018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (0x42002019U) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (0x4200201AU) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (0x4200201CU) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (0x42002020U) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (0x42002024U) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (0x42002026U) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (0x42002028U) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (0x4200202AU) /**< \brief (ADC) Debug Control */
|
||||
#else
|
||||
#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
|
||||
#define REG_ADC_CTRLA (*(RwReg8 *)0x42002000U) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (*(RwReg8 *)0x42002001U) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42002002U) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42002003U) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (*(RwReg16*)0x42002004U) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (*(RwReg8 *)0x42002008U) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200200CU) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (*(RwReg *)0x42002010U) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (*(RwReg8 *)0x42002014U) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (*(RwReg8 *)0x42002016U) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (*(RwReg8 *)0x42002017U) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (*(RwReg8 *)0x42002018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (*(RoReg8 *)0x42002019U) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (*(RoReg16*)0x4200201AU) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (*(RwReg16*)0x4200201CU) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (*(RwReg16*)0x42002020U) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (*(RwReg16*)0x42002024U) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42002026U) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (*(RwReg16*)0x42002028U) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200202AU) /**< \brief (ADC) Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for ADC peripheral ========== */
|
||||
#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger
|
||||
#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
|
||||
#define ADC_GCLK_ID 30 // Index of Generic Clock
|
||||
#define ADC_DMAC_ID_RESRDY 18 // Index of DMA RESRDY trigger
|
||||
#define ADC_EXTCHANNEL_MSB 9 // Number of external channels
|
||||
#define ADC_GCLK_ID 19 // Index of Generic Clock
|
||||
#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield
|
||||
#define ADC_RESULT_MSB 15 // Size of Result
|
||||
|
||||
#endif /* _SAMD21_ADC_INSTANCE_ */
|
||||
#endif /* _SAMD11_ADC_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for DAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,38 +40,35 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_INSTANCE_
|
||||
#define _SAMD21_DAC_INSTANCE_
|
||||
#ifndef _SAMD11_DAC_INSTANCE_
|
||||
#define _SAMD11_DAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */
|
||||
#define REG_DAC_CTRLA (0x42002800U) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (0x42002801U) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (0x42002802U) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (0x42002804U) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (0x42002805U) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (0x42002806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (0x42002807U) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (0x42002808U) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (0x4200280CU) /**< \brief (DAC) Data Buffer */
|
||||
#else
|
||||
#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
|
||||
#define REG_DAC_CTRLA (*(RwReg8 *)0x42002800U) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (*(RwReg8 *)0x42002801U) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42002802U) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42002804U) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (*(RwReg8 *)0x42002805U) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42002806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (*(RoReg8 *)0x42002807U) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (*(RwReg16*)0x42002808U) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (*(RwReg16*)0x4200280CU) /**< \brief (DAC) Data Buffer */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DAC peripheral ========== */
|
||||
#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger
|
||||
#define DAC_GCLK_ID 33 // Index of Generic Clock
|
||||
#define DAC_DMAC_ID_EMPTY 19 // Index of DMAC EMPTY trigger
|
||||
#define DAC_GCLK_ID 22 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_DAC_INSTANCE_ */
|
||||
#endif /* _SAMD11_DAC_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for DMAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DMAC_INSTANCE_
|
||||
#define _SAMD21_DMAC_INSTANCE_
|
||||
#ifndef _SAMD11_DMAC_INSTANCE_
|
||||
#define _SAMD11_DMAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -99,14 +96,14 @@
|
|||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DMAC peripheral ========== */
|
||||
#define DMAC_CH_BITS 4 // Number of bits to select channel
|
||||
#define DMAC_CH_NUM 12 // Number of channels
|
||||
#define DMAC_CH_BITS 3 // Number of bits to select channel
|
||||
#define DMAC_CH_NUM 6 // Number of channels
|
||||
#define DMAC_CLK_AHB_ID 5 // AHB clock index
|
||||
#define DMAC_EVIN_NUM 4 // Number of input events
|
||||
#define DMAC_EVOUT_NUM 4 // Number of output events
|
||||
#define DMAC_LVL_BITS 2 // Number of bit to select level priority
|
||||
#define DMAC_LVL_NUM 4 // Enable priority level number
|
||||
#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
|
||||
#define DMAC_TRIG_NUM 45 // Number of peripheral triggers
|
||||
#define DMAC_TRIG_BITS 5 // Number of bits to select trigger source
|
||||
#define DMAC_TRIG_NUM 20 // Number of peripheral triggers
|
||||
|
||||
#endif /* _SAMD21_DMAC_INSTANCE_ */
|
||||
#endif /* _SAMD11_DMAC_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for DSU
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_INSTANCE_
|
||||
#define _SAMD21_DSU_INSTANCE_
|
||||
#ifndef _SAMD11_DSU_INSTANCE_
|
||||
#define _SAMD11_DSU_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DSU peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -58,11 +55,16 @@
|
|||
#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
|
||||
#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration 0 */
|
||||
#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration 1 */
|
||||
#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
|
||||
#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
|
||||
#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
|
||||
#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */
|
||||
#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */
|
||||
#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */
|
||||
#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
|
||||
#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
|
||||
#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
|
||||
|
@ -81,11 +83,16 @@
|
|||
#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
|
||||
#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration 0 */
|
||||
#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration 1 */
|
||||
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
|
||||
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
|
||||
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
|
||||
#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */
|
||||
#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */
|
||||
#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */
|
||||
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
|
||||
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
|
||||
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
|
||||
|
@ -97,6 +104,7 @@
|
|||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DSU peripheral ========== */
|
||||
#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register
|
||||
#define DSU_CLK_AHB_DOMAIN // Clock domain of AHB clock
|
||||
#define DSU_CLK_AHB_ID 3 // Index of AHB clock in PM.AHBMASK register
|
||||
|
||||
#endif /* _SAMD21_DSU_INSTANCE_ */
|
||||
#endif /* _SAMD11_DSU_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for EIC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_INSTANCE_
|
||||
#define _SAMD21_EIC_INSTANCE_
|
||||
#ifndef _SAMD11_EIC_INSTANCE_
|
||||
#define _SAMD11_EIC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EIC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -59,7 +56,6 @@
|
|||
#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
|
||||
#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */
|
||||
#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */
|
||||
#else
|
||||
#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
|
||||
#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
|
||||
|
@ -71,11 +67,11 @@
|
|||
#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
|
||||
#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */
|
||||
#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EIC peripheral ========== */
|
||||
#define EIC_CONFIG_NUM 2 // Number of CONFIG registers
|
||||
#define EIC_CONFIG_NUM 1 // Number of CONFIG registers
|
||||
#define EIC_EXTINT_NUM 8 // Number of External Interrupts
|
||||
#define EIC_GCLK_ID 5 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_EIC_INSTANCE_ */
|
||||
#endif /* _SAMD11_EIC_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_INSTANCE_
|
||||
#define _SAMD21_EVSYS_INSTANCE_
|
||||
#ifndef _SAMD11_EVSYS_INSTANCE_
|
||||
#define _SAMD11_EVSYS_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EVSYS peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -67,9 +64,9 @@
|
|||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EVSYS peripheral ========== */
|
||||
#define EVSYS_CHANNELS 12 // Number of Channels
|
||||
#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel
|
||||
#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1
|
||||
#define EVSYS_CHANNELS 6 // Number of Channels
|
||||
#define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel
|
||||
#define EVSYS_CHANNELS_MSB 5 // Number of Channels - 1
|
||||
#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
|
||||
#define EVSYS_GCLK_ID_0 7
|
||||
#define EVSYS_GCLK_ID_1 8
|
||||
|
@ -77,18 +74,12 @@
|
|||
#define EVSYS_GCLK_ID_3 10
|
||||
#define EVSYS_GCLK_ID_4 11
|
||||
#define EVSYS_GCLK_ID_5 12
|
||||
#define EVSYS_GCLK_ID_6 13
|
||||
#define EVSYS_GCLK_ID_7 14
|
||||
#define EVSYS_GCLK_ID_8 15
|
||||
#define EVSYS_GCLK_ID_9 16
|
||||
#define EVSYS_GCLK_ID_10 17
|
||||
#define EVSYS_GCLK_ID_11 18
|
||||
#define EVSYS_GCLK_ID_LSB 7
|
||||
#define EVSYS_GCLK_ID_MSB 18
|
||||
#define EVSYS_GCLK_ID_SIZE 12
|
||||
#define EVSYS_GENERATORS 76 // Total Number of Event Generators
|
||||
#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
|
||||
#define EVSYS_USERS 31 // Total Number of Event Users
|
||||
#define EVSYS_GCLK_ID_MSB 12
|
||||
#define EVSYS_GCLK_ID_SIZE 6
|
||||
#define EVSYS_GENERATORS 44 // Total Number of Event Generators
|
||||
#define EVSYS_GENERATORS_BITS 6 // Number of bits to select Event Generator
|
||||
#define EVSYS_USERS 18 // Total Number of Event Users
|
||||
#define EVSYS_USERS_BITS 5 // Number of bits to select Event User
|
||||
|
||||
// GENERATORS
|
||||
|
@ -111,63 +102,31 @@
|
|||
#define EVSYS_ID_GEN_EIC_EXTINT_5 17
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_6 18
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_7 19
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_8 20
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_9 21
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_10 22
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_11 23
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_12 24
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_13 25
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_14 26
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_15 27
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_16 28
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_17 29
|
||||
#define EVSYS_ID_GEN_DMAC_CH_0 30
|
||||
#define EVSYS_ID_GEN_DMAC_CH_1 31
|
||||
#define EVSYS_ID_GEN_DMAC_CH_2 32
|
||||
#define EVSYS_ID_GEN_DMAC_CH_3 33
|
||||
#define EVSYS_ID_GEN_TCC0_OVF 34
|
||||
#define EVSYS_ID_GEN_TCC0_TRG 35
|
||||
#define EVSYS_ID_GEN_TCC0_CNT 36
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_0 37
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_1 38
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_2 39
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_3 40
|
||||
#define EVSYS_ID_GEN_TCC1_OVF 41
|
||||
#define EVSYS_ID_GEN_TCC1_TRG 42
|
||||
#define EVSYS_ID_GEN_TCC1_CNT 43
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_0 44
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_1 45
|
||||
#define EVSYS_ID_GEN_TCC2_OVF 46
|
||||
#define EVSYS_ID_GEN_TCC2_TRG 47
|
||||
#define EVSYS_ID_GEN_TCC2_CNT 48
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_0 49
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_1 50
|
||||
#define EVSYS_ID_GEN_TC3_OVF 51
|
||||
#define EVSYS_ID_GEN_TC3_MCX_0 52
|
||||
#define EVSYS_ID_GEN_TC3_MCX_1 53
|
||||
#define EVSYS_ID_GEN_TC4_OVF 54
|
||||
#define EVSYS_ID_GEN_TC4_MCX_0 55
|
||||
#define EVSYS_ID_GEN_TC4_MCX_1 56
|
||||
#define EVSYS_ID_GEN_TC5_OVF 57
|
||||
#define EVSYS_ID_GEN_TC5_MCX_0 58
|
||||
#define EVSYS_ID_GEN_TC5_MCX_1 59
|
||||
#define EVSYS_ID_GEN_TC6_OVF 60
|
||||
#define EVSYS_ID_GEN_TC6_MCX_0 61
|
||||
#define EVSYS_ID_GEN_TC6_MCX_1 62
|
||||
#define EVSYS_ID_GEN_TC7_OVF 63
|
||||
#define EVSYS_ID_GEN_TC7_MCX_0 64
|
||||
#define EVSYS_ID_GEN_TC7_MCX_1 65
|
||||
#define EVSYS_ID_GEN_ADC_RESRDY 66
|
||||
#define EVSYS_ID_GEN_ADC_WINMON 67
|
||||
#define EVSYS_ID_GEN_AC_COMP_0 68
|
||||
#define EVSYS_ID_GEN_AC_COMP_1 69
|
||||
#define EVSYS_ID_GEN_AC_WIN_0 70
|
||||
#define EVSYS_ID_GEN_DAC_EMPTY 71
|
||||
#define EVSYS_ID_GEN_PTC_EOC 72
|
||||
#define EVSYS_ID_GEN_PTC_WCOMP 73
|
||||
#define EVSYS_ID_GEN_AC1_COMP_0 74
|
||||
#define EVSYS_ID_GEN_AC1_COMP_1 75
|
||||
#define EVSYS_ID_GEN_AC1_WIN_0 76
|
||||
#define EVSYS_ID_GEN_DMAC_CH_0 20
|
||||
#define EVSYS_ID_GEN_DMAC_CH_1 21
|
||||
#define EVSYS_ID_GEN_DMAC_CH_2 22
|
||||
#define EVSYS_ID_GEN_DMAC_CH_3 23
|
||||
#define EVSYS_ID_GEN_TCC0_OVF 24
|
||||
#define EVSYS_ID_GEN_TCC0_TRG 25
|
||||
#define EVSYS_ID_GEN_TCC0_CNT 26
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_0 27
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_1 28
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_2 29
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_3 30
|
||||
#define EVSYS_ID_GEN_TC1_OVF 31
|
||||
#define EVSYS_ID_GEN_TC1_MCX_0 32
|
||||
#define EVSYS_ID_GEN_TC1_MCX_1 33
|
||||
#define EVSYS_ID_GEN_TC2_OVF 34
|
||||
#define EVSYS_ID_GEN_TC2_MCX_0 35
|
||||
#define EVSYS_ID_GEN_TC2_MCX_1 36
|
||||
#define EVSYS_ID_GEN_ADC_RESRDY 37
|
||||
#define EVSYS_ID_GEN_ADC_WINMON 38
|
||||
#define EVSYS_ID_GEN_AC_COMP_0 39
|
||||
#define EVSYS_ID_GEN_AC_COMP_1 40
|
||||
#define EVSYS_ID_GEN_AC_WIN_0 41
|
||||
#define EVSYS_ID_GEN_DAC_EMPTY 42
|
||||
#define EVSYS_ID_GEN_PTC_EOC 43
|
||||
#define EVSYS_ID_GEN_PTC_WCOMP 44
|
||||
|
||||
// USERS
|
||||
#define EVSYS_ID_USER_DMAC_CH_0 0
|
||||
|
@ -180,26 +139,13 @@
|
|||
#define EVSYS_ID_USER_TCC0_MC_1 7
|
||||
#define EVSYS_ID_USER_TCC0_MC_2 8
|
||||
#define EVSYS_ID_USER_TCC0_MC_3 9
|
||||
#define EVSYS_ID_USER_TCC1_EV_0 10
|
||||
#define EVSYS_ID_USER_TCC1_EV_1 11
|
||||
#define EVSYS_ID_USER_TCC1_MC_0 12
|
||||
#define EVSYS_ID_USER_TCC1_MC_1 13
|
||||
#define EVSYS_ID_USER_TCC2_EV_0 14
|
||||
#define EVSYS_ID_USER_TCC2_EV_1 15
|
||||
#define EVSYS_ID_USER_TCC2_MC_0 16
|
||||
#define EVSYS_ID_USER_TCC2_MC_1 17
|
||||
#define EVSYS_ID_USER_TC3_EVU 18
|
||||
#define EVSYS_ID_USER_TC4_EVU 19
|
||||
#define EVSYS_ID_USER_TC5_EVU 20
|
||||
#define EVSYS_ID_USER_TC6_EVU 21
|
||||
#define EVSYS_ID_USER_TC7_EVU 22
|
||||
#define EVSYS_ID_USER_ADC_START 23
|
||||
#define EVSYS_ID_USER_ADC_SYNC 24
|
||||
#define EVSYS_ID_USER_AC_SOC_0 25
|
||||
#define EVSYS_ID_USER_AC_SOC_1 26
|
||||
#define EVSYS_ID_USER_DAC_START 27
|
||||
#define EVSYS_ID_USER_PTC_STCONV 28
|
||||
#define EVSYS_ID_USER_AC1_SOC_0 29
|
||||
#define EVSYS_ID_USER_AC1_SOC_1 30
|
||||
#define EVSYS_ID_USER_TC1_EVU 10
|
||||
#define EVSYS_ID_USER_TC2_EVU 11
|
||||
#define EVSYS_ID_USER_ADC_START 12
|
||||
#define EVSYS_ID_USER_ADC_SYNC 13
|
||||
#define EVSYS_ID_USER_AC_SOC_0 14
|
||||
#define EVSYS_ID_USER_AC_SOC_1 15
|
||||
#define EVSYS_ID_USER_DAC_START 16
|
||||
#define EVSYS_ID_USER_PTC_STCONV 17
|
||||
|
||||
#endif /* _SAMD21_EVSYS_INSTANCE_ */
|
||||
#endif /* _SAMD11_EVSYS_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for GCLK
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_INSTANCE_
|
||||
#define _SAMD21_GCLK_INSTANCE_
|
||||
#ifndef _SAMD11_GCLK_INSTANCE_
|
||||
#define _SAMD11_GCLK_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GCLK peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -64,19 +61,19 @@
|
|||
|
||||
/* ========== Instance parameters for GCLK peripheral ========== */
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
|
||||
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
|
||||
#define GCLK_GEN_NUM 6 // Number of Generic Clock Generators
|
||||
#define GCLK_GEN_NUM_MSB 5 // Number of Generic Clock Generators - 1
|
||||
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
|
||||
#define GCLK_NUM 37 // Number of Generic Clock Users
|
||||
#define GCLK_SOURCE_DFLL48M 7 // DFLL48M output
|
||||
#define GCLK_SOURCE_FDPLL 8 // FDPLL output
|
||||
#define GCLK_SOURCE_GCLKGEN1 2 // Generic clock generator 1 output
|
||||
#define GCLK_SOURCE_GCLKIN 1 // Generator input pad
|
||||
#define GCLK_NUM 24 // Number of Generic Clock Users
|
||||
#define GCLK_SOURCE_DFLL48M 7
|
||||
#define GCLK_SOURCE_FDPLL 8
|
||||
#define GCLK_SOURCE_GCLKGEN1 2
|
||||
#define GCLK_SOURCE_GCLKIN 1
|
||||
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
|
||||
#define GCLK_SOURCE_OSCULP32K 3 // OSCULP32K oscillator output
|
||||
#define GCLK_SOURCE_OSC8M 6 // OSC8M oscillator output
|
||||
#define GCLK_SOURCE_OSC32K 4 // OSC32K oscillator outpur
|
||||
#define GCLK_SOURCE_XOSC 0 // XOSC oscillator output
|
||||
#define GCLK_SOURCE_XOSC32K 5 // XOSC32K oscillator output
|
||||
#define GCLK_SOURCE_OSCULP32K 3
|
||||
#define GCLK_SOURCE_OSC8M 6
|
||||
#define GCLK_SOURCE_OSC32K 4
|
||||
#define GCLK_SOURCE_XOSC 0
|
||||
#define GCLK_SOURCE_XOSC32K 5
|
||||
|
||||
#endif /* _SAMD21_GCLK_INSTANCE_ */
|
||||
#endif /* _SAMD11_GCLK_INSTANCE_ */
|
||||
|
|
|
@ -1,97 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for I2S
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_I2S_INSTANCE_
|
||||
#define _SAMD21_I2S_INSTANCE_
|
||||
|
||||
/* ========== Register definition for I2S peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */
|
||||
#define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
|
||||
#define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
|
||||
#define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
|
||||
#define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
|
||||
#define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
|
||||
#define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */
|
||||
#define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
|
||||
#define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
|
||||
#define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */
|
||||
#define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */
|
||||
#else
|
||||
#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
|
||||
#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
|
||||
#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
|
||||
#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
|
||||
#define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
|
||||
#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
|
||||
#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
|
||||
#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
|
||||
#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
|
||||
#define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */
|
||||
#define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for I2S peripheral ========== */
|
||||
#define I2S_CLK_NUM 2 // Number of clock units
|
||||
#define I2S_DMAC_ID_RX_0 41
|
||||
#define I2S_DMAC_ID_RX_1 42
|
||||
#define I2S_DMAC_ID_RX_LSB 41
|
||||
#define I2S_DMAC_ID_RX_MSB 42
|
||||
#define I2S_DMAC_ID_RX_SIZE 2
|
||||
#define I2S_DMAC_ID_TX_0 43
|
||||
#define I2S_DMAC_ID_TX_1 44
|
||||
#define I2S_DMAC_ID_TX_LSB 43
|
||||
#define I2S_DMAC_ID_TX_MSB 44
|
||||
#define I2S_DMAC_ID_TX_SIZE 2
|
||||
#define I2S_GCLK_ID_0 35
|
||||
#define I2S_GCLK_ID_1 36
|
||||
#define I2S_GCLK_ID_LSB 35
|
||||
#define I2S_GCLK_ID_MSB 36
|
||||
#define I2S_GCLK_ID_SIZE 2
|
||||
#define I2S_MAX_SLOTS 8 // Max number of data slots in frame
|
||||
#define I2S_SER_NUM 2 // Number of serializers
|
||||
|
||||
#endif /* _SAMD21_I2S_INSTANCE_ */
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for MTB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_INSTANCE_
|
||||
#define _SAMD21_MTB_INSTANCE_
|
||||
#ifndef _SAMD11_MTB_INSTANCE_
|
||||
#define _SAMD11_MTB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MTB peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -103,4 +100,4 @@
|
|||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
|
||||
#endif /* _SAMD21_MTB_INSTANCE_ */
|
||||
#endif /* _SAMD11_MTB_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_NVMCTRL_INSTANCE_
|
||||
#define _SAMD21_NVMCTRL_INSTANCE_
|
||||
#ifndef _SAMD11_NVMCTRL_INSTANCE_
|
||||
#define _SAMD11_NVMCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for NVMCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -77,9 +74,12 @@
|
|||
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
|
||||
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
|
||||
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
|
||||
#define NVMCTRL_FLASH_SIZE 65536
|
||||
#define NVMCTRL_FLASH_SIZE 16384
|
||||
#define NVMCTRL_FUSES_SECURE_NVM // NVM Vault Address
|
||||
#define NVMCTRL_FUSES_SECURE_RAM // RAM Vault Address
|
||||
#define NVMCTRL_FUSES_SECURE_STATE // Vault State
|
||||
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
|
||||
#define NVMCTRL_PAGES 1024
|
||||
#define NVMCTRL_PAGES 256
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
|
@ -90,7 +90,5 @@
|
|||
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
|
||||
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
|
||||
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
|
||||
#define NVMCTRL_RWWEE_PAGES 32 // Page size
|
||||
#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area
|
||||
|
||||
#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
|
||||
#endif /* _SAMD11_NVMCTRL_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PAC0
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC0_INSTANCE_
|
||||
#define _SAMD21_PAC0_INSTANCE_
|
||||
#ifndef _SAMD11_PAC0_INSTANCE_
|
||||
#define _SAMD11_PAC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -59,4 +56,4 @@
|
|||
/* ========== Instance parameters for PAC0 peripheral ========== */
|
||||
#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC0_INSTANCE_ */
|
||||
#endif /* _SAMD11_PAC0_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PAC1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC1_INSTANCE_
|
||||
#define _SAMD21_PAC1_INSTANCE_
|
||||
#ifndef _SAMD11_PAC1_INSTANCE_
|
||||
#define _SAMD11_PAC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -59,4 +56,4 @@
|
|||
/* ========== Instance parameters for PAC1 peripheral ========== */
|
||||
#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC1_INSTANCE_ */
|
||||
#endif /* _SAMD11_PAC1_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PAC2
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC2_INSTANCE_
|
||||
#define _SAMD21_PAC2_INSTANCE_
|
||||
#ifndef _SAMD11_PAC2_INSTANCE_
|
||||
#define _SAMD11_PAC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -57,6 +54,6 @@
|
|||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC2 peripheral ========== */
|
||||
#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset
|
||||
#define PAC2_WPROT_DEFAULT_VAL 0x00001000 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC2_INSTANCE_ */
|
||||
#endif /* _SAMD11_PAC2_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PM
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PM_INSTANCE_
|
||||
#define _SAMD21_PM_INSTANCE_
|
||||
#ifndef _SAMD11_PM_INSTANCE_
|
||||
#define _SAMD11_PM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PM peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -89,4 +86,4 @@
|
|||
#define PM_CTRL_MCSEL_XOSC 2
|
||||
#define PM_PM_CLK_APB_NUM 2
|
||||
|
||||
#endif /* _SAMD21_PM_INSTANCE_ */
|
||||
#endif /* _SAMD11_PM_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for PORT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_INSTANCE_
|
||||
#define _SAMD21_PORT_INSTANCE_
|
||||
#ifndef _SAMD11_PORT_INSTANCE_
|
||||
#define _SAMD11_PORT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PORT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -62,19 +59,6 @@
|
|||
#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
|
||||
#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
|
||||
#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
|
||||
#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
|
||||
#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
|
||||
#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
|
||||
#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
|
||||
#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
|
||||
#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
|
||||
#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
|
||||
#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
|
||||
#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
|
||||
#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
|
||||
#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
|
||||
#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
|
||||
#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
|
||||
#else
|
||||
#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
|
||||
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
|
||||
|
@ -89,51 +73,39 @@
|
|||
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
|
||||
#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
|
||||
#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
|
||||
#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
|
||||
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
|
||||
#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
|
||||
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
|
||||
#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
|
||||
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
|
||||
#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
|
||||
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
|
||||
#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
|
||||
#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
|
||||
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
|
||||
#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
|
||||
#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PORT peripheral ========== */
|
||||
#define PORT_BITS 64 // Number of PORT pins
|
||||
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for DIR of all pins
|
||||
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
|
||||
#define PORT_BITS 32 // Number of PORT pins
|
||||
#define PORT_DIR_DEFAULT_VAL { 0x00000000 } // Default value for DIR of all pins
|
||||
#define PORT_DIR_IMPLEMENTED { 0xDBC3CFFC } // Implementation mask for DIR of all pins
|
||||
#define PORT_DRVSTR 1 // DRVSTR supported
|
||||
#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
|
||||
#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
|
||||
#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000 }
|
||||
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for INEN of all pins
|
||||
#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
|
||||
#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000 } // Default value for DRVSTR of all pins
|
||||
#define PORT_DRVSTR_IMPLEMENTED { 0xD8C3CFFC } // Implementation mask for DRVSTR of all pins
|
||||
#define PORT_EVENT_IMPLEMENTED { 0x00000000 }
|
||||
#define PORT_GROUPS 1 // Number of 32-bit PORT groups
|
||||
#define PORT_INEN_DEFAULT_VAL { 0x10000000 } // Default value for INEN of all pins
|
||||
#define PORT_INEN_IMPLEMENTED { 0xDBC3CFFC } // Implementation mask for INEN of all pins
|
||||
#define PORT_ODRAIN 0 // ODRAIN supported
|
||||
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
|
||||
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
|
||||
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for OUT of all pins
|
||||
#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
|
||||
#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
|
||||
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
|
||||
#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
|
||||
#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
|
||||
#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
|
||||
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
|
||||
#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
|
||||
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000 } // Default value for ODRAIN of all pins
|
||||
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000 } // Implementation mask for ODRAIN of all pins
|
||||
#define PORT_OUT_DEFAULT_VAL { 0x10000000 } // Default value for OUT of all pins
|
||||
#define PORT_OUT_IMPLEMENTED { 0xDBC3CFFC } // Implementation mask for OUT of all pins
|
||||
#define PORT_PIN_IMPLEMENTED { 0xDBC3CFFC } // Implementation mask for all PORT pins
|
||||
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000 } // Default value for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBC3CFFC } // Implementation mask for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000 } // Default value for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBC3CFF0 } // Implementation mask for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000 } // Default value for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT2_IMPLEMENTED { 0xCBC3CFF0 } // Implementation mask for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000 } // Default value for PMUX[3] of all pins
|
||||
#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000 } // Implementation mask for PMUX[3] of all pins
|
||||
#define PORT_PMUXEN_DEFAULT_VAL { 0x643C3003 } // Default value for PMUXEN of all pins
|
||||
#define PORT_PMUXEN_IMPLEMENTED { 0xCBC3CFFC } // Implementation mask for PMUXEN of all pins
|
||||
#define PORT_PULLEN_DEFAULT_VAL { 0x10000000 } // Default value for PULLEN of all pins
|
||||
#define PORT_PULLEN_IMPLEMENTED { 0xDBC3CFFC } // Implementation mask for PULLEN of all pins
|
||||
#define PORT_SLEWLIM 0 // SLEWLIM supported
|
||||
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
|
||||
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
|
||||
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000 } // Default value for SLEWLIM of all pins
|
||||
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000 } // Implementation mask for SLEWLIM of all pins
|
||||
|
||||
#endif /* _SAMD21_PORT_INSTANCE_ */
|
||||
#endif /* _SAMD11_PORT_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for RTC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_RTC_INSTANCE_
|
||||
#define _SAMD21_RTC_INSTANCE_
|
||||
#ifndef _SAMD11_RTC_INSTANCE_
|
||||
#define _SAMD11_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -117,4 +114,4 @@
|
|||
#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
|
||||
#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
|
||||
|
||||
#endif /* _SAMD21_RTC_INSTANCE_ */
|
||||
#endif /* _SAMD11_RTC_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SBMATRIX
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SBMATRIX_INSTANCE_
|
||||
#define _SAMD21_SBMATRIX_INSTANCE_
|
||||
#ifndef _SAMD11_SBMATRIX_INSTANCE_
|
||||
#define _SAMD11_SBMATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SBMATRIX peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -165,4 +162,4 @@
|
|||
#define SBMATRIX_MASTER_DMAC 2
|
||||
#define SBMATRIX_MASTER_NUM 3
|
||||
|
||||
#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
|
||||
#endif /* _SAMD11_SBMATRIX_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM0
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM0_INSTANCE_
|
||||
#define _SAMD21_SERCOM0_INSTANCE_
|
||||
#ifndef _SAMD11_SERCOM0_INSTANCE_
|
||||
#define _SAMD11_SERCOM0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -139,8 +136,8 @@
|
|||
/* ========== Instance parameters for SERCOM0 peripheral ========== */
|
||||
#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
|
||||
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
|
||||
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
|
||||
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM0_GCLK_ID_CORE 14 // Index of Generic Clock for Core
|
||||
#define SERCOM0_GCLK_ID_SLOW 13 // Index of Generic Clock for SMbus Timeout
|
||||
#define SERCOM0_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM0_INSTANCE_ */
|
||||
#endif /* _SAMD11_SERCOM0_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM1_INSTANCE_
|
||||
#define _SAMD21_SERCOM1_INSTANCE_
|
||||
#ifndef _SAMD11_SERCOM1_INSTANCE_
|
||||
#define _SAMD11_SERCOM1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -139,8 +136,8 @@
|
|||
/* ========== Instance parameters for SERCOM1 peripheral ========== */
|
||||
#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger
|
||||
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
|
||||
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
|
||||
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM1_GCLK_ID_CORE 15 // Index of Generic Clock for Core
|
||||
#define SERCOM1_GCLK_ID_SLOW 13 // Index of Generic Clock for SMbus Timeout
|
||||
#define SERCOM1_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM1_INSTANCE_ */
|
||||
#endif /* _SAMD11_SERCOM1_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SERCOM2
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM2_INSTANCE_
|
||||
#define _SAMD21_SERCOM2_INSTANCE_
|
||||
#ifndef _SAMD11_SERCOM2_INSTANCE_
|
||||
#define _SAMD11_SERCOM2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -139,8 +136,8 @@
|
|||
/* ========== Instance parameters for SERCOM2 peripheral ========== */
|
||||
#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
|
||||
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
|
||||
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
|
||||
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM2_GCLK_ID_CORE 16 // Index of Generic Clock for Core
|
||||
#define SERCOM2_GCLK_ID_SLOW 13 // Index of Generic Clock for SMbus Timeout
|
||||
#define SERCOM2_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM2_INSTANCE_ */
|
||||
#endif /* _SAMD11_SERCOM2_INSTANCE_ */
|
||||
|
|
|
@ -1,146 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM3
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM3_INSTANCE_
|
||||
#define _SAMD21_SERCOM3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
|
||||
#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
|
||||
#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
|
||||
#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
|
||||
#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
|
||||
#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
|
||||
#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
|
||||
#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
|
||||
#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */
|
||||
#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */
|
||||
#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
|
||||
#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
|
||||
#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
|
||||
#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
|
||||
#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
|
||||
#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
|
||||
#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
|
||||
#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
|
||||
#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
|
||||
#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
|
||||
#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
|
||||
#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
|
||||
#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
|
||||
#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
|
||||
#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM3 peripheral ========== */
|
||||
#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
|
||||
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
|
||||
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
|
||||
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM3_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM3_INSTANCE_ */
|
|
@ -1,146 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM4
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM4_INSTANCE_
|
||||
#define _SAMD21_SERCOM4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
|
||||
#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
|
||||
#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
|
||||
#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
|
||||
#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
|
||||
#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
|
||||
#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
|
||||
#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
|
||||
#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */
|
||||
#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */
|
||||
#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
|
||||
#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
|
||||
#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
|
||||
#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
|
||||
#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
|
||||
#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
|
||||
#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
|
||||
#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
|
||||
#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
|
||||
#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
|
||||
#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
|
||||
#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
|
||||
#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
|
||||
#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
|
||||
#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM4 peripheral ========== */
|
||||
#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger
|
||||
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
|
||||
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
|
||||
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM4_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM4_INSTANCE_ */
|
|
@ -1,146 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM5
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM5_INSTANCE_
|
||||
#define _SAMD21_SERCOM5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
|
||||
#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
|
||||
#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
|
||||
#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
|
||||
#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
|
||||
#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
|
||||
#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
|
||||
#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
|
||||
#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
|
||||
#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
|
||||
#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
|
||||
#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
|
||||
#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
|
||||
#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
|
||||
#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
|
||||
#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
|
||||
#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
|
||||
#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
|
||||
#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
|
||||
#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
|
||||
#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
|
||||
#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
|
||||
#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
|
||||
#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
|
||||
#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM5 peripheral ========== */
|
||||
#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger
|
||||
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
|
||||
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
|
||||
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM5_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM5_INSTANCE_ */
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for SYSCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SYSCTRL_INSTANCE_
|
||||
#define _SAMD21_SYSCTRL_INSTANCE_
|
||||
#ifndef _SAMD11_SYSCTRL_INSTANCE_
|
||||
#define _SAMD11_SYSCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SYSCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -63,7 +60,6 @@
|
|||
#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
|
||||
#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
|
||||
#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
|
||||
#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
|
||||
#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
|
||||
|
@ -84,7 +80,6 @@
|
|||
#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
|
||||
#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
|
||||
#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
|
||||
#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
|
||||
#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
|
||||
|
@ -94,6 +89,7 @@
|
|||
|
||||
/* ========== Instance parameters for SYSCTRL peripheral ========== */
|
||||
#define SYSCTRL_BGAP_CALIB_MSB 11
|
||||
#define SYSCTRL_BOD12_CALIB_MSB 4
|
||||
#define SYSCTRL_BOD33_CALIB_MSB 5
|
||||
#define SYSCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define SYSCTRL_DFLL48M_FINE_MSB 9
|
||||
|
@ -110,14 +106,14 @@
|
|||
#define SYSCTRL_VREG_LEVEL_MSB 2
|
||||
#define SYSCTRL_BOD12_VERSION 0x111
|
||||
#define SYSCTRL_BOD33_VERSION 0x111
|
||||
#define SYSCTRL_DFLL48M_VERSION 0x301
|
||||
#define SYSCTRL_FDPLL_VERSION 0x111
|
||||
#define SYSCTRL_DFLL48M_VERSION 0x300
|
||||
#define SYSCTRL_FDPLL_VERSION 0x110
|
||||
#define SYSCTRL_OSCULP32K_VERSION 0x111
|
||||
#define SYSCTRL_OSC8M_VERSION 0x120
|
||||
#define SYSCTRL_OSC32K_VERSION 0x112
|
||||
#define SYSCTRL_OSC32K_VERSION 0x110
|
||||
#define SYSCTRL_VREF_VERSION 0x201
|
||||
#define SYSCTRL_VREG_VERSION 0x201
|
||||
#define SYSCTRL_XOSC_VERSION 0x114
|
||||
#define SYSCTRL_XOSC32K_VERSION 0x113
|
||||
#define SYSCTRL_XOSC_VERSION 0x112
|
||||
#define SYSCTRL_XOSC32K_VERSION 0x111
|
||||
|
||||
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
|
||||
#endif /* _SAMD11_SYSCTRL_INSTANCE_ */
|
||||
|
|
|
@ -0,0 +1,111 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC1
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD11_TC1_INSTANCE_
|
||||
#define _SAMD11_TC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC1_CTRLA (0x42001800U) /**< \brief (TC1) Control A */
|
||||
#define REG_TC1_READREQ (0x42001802U) /**< \brief (TC1) Read Request */
|
||||
#define REG_TC1_CTRLBCLR (0x42001804U) /**< \brief (TC1) Control B Clear */
|
||||
#define REG_TC1_CTRLBSET (0x42001805U) /**< \brief (TC1) Control B Set */
|
||||
#define REG_TC1_CTRLC (0x42001806U) /**< \brief (TC1) Control C */
|
||||
#define REG_TC1_DBGCTRL (0x42001808U) /**< \brief (TC1) Debug Control */
|
||||
#define REG_TC1_EVCTRL (0x4200180AU) /**< \brief (TC1) Event Control */
|
||||
#define REG_TC1_INTENCLR (0x4200180CU) /**< \brief (TC1) Interrupt Enable Clear */
|
||||
#define REG_TC1_INTENSET (0x4200180DU) /**< \brief (TC1) Interrupt Enable Set */
|
||||
#define REG_TC1_INTFLAG (0x4200180EU) /**< \brief (TC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TC1_STATUS (0x4200180FU) /**< \brief (TC1) Status */
|
||||
#define REG_TC1_COUNT16_COUNT (0x42001810U) /**< \brief (TC1) COUNT16 Counter Value */
|
||||
#define REG_TC1_COUNT16_CC0 (0x42001818U) /**< \brief (TC1) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC1_COUNT16_CC1 (0x4200181AU) /**< \brief (TC1) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC1_COUNT32_COUNT (0x42001810U) /**< \brief (TC1) COUNT32 Counter Value */
|
||||
#define REG_TC1_COUNT32_CC0 (0x42001818U) /**< \brief (TC1) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC1_COUNT32_CC1 (0x4200181CU) /**< \brief (TC1) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC1_COUNT8_COUNT (0x42001810U) /**< \brief (TC1) COUNT8 Counter Value */
|
||||
#define REG_TC1_COUNT8_PER (0x42001814U) /**< \brief (TC1) COUNT8 Period Value */
|
||||
#define REG_TC1_COUNT8_CC0 (0x42001818U) /**< \brief (TC1) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC1_COUNT8_CC1 (0x42001819U) /**< \brief (TC1) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC1_CTRLA (*(RwReg16*)0x42001800U) /**< \brief (TC1) Control A */
|
||||
#define REG_TC1_READREQ (*(RwReg16*)0x42001802U) /**< \brief (TC1) Read Request */
|
||||
#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42001804U) /**< \brief (TC1) Control B Clear */
|
||||
#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42001805U) /**< \brief (TC1) Control B Set */
|
||||
#define REG_TC1_CTRLC (*(RwReg8 *)0x42001806U) /**< \brief (TC1) Control C */
|
||||
#define REG_TC1_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (TC1) Debug Control */
|
||||
#define REG_TC1_EVCTRL (*(RwReg16*)0x4200180AU) /**< \brief (TC1) Event Control */
|
||||
#define REG_TC1_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (TC1) Interrupt Enable Clear */
|
||||
#define REG_TC1_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (TC1) Interrupt Enable Set */
|
||||
#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (TC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TC1_STATUS (*(RoReg8 *)0x4200180FU) /**< \brief (TC1) Status */
|
||||
#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42001810U) /**< \brief (TC1) COUNT16 Counter Value */
|
||||
#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x42001818U) /**< \brief (TC1) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200181AU) /**< \brief (TC1) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42001810U) /**< \brief (TC1) COUNT32 Counter Value */
|
||||
#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x42001818U) /**< \brief (TC1) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x4200181CU) /**< \brief (TC1) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42001810U) /**< \brief (TC1) COUNT8 Counter Value */
|
||||
#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x42001814U) /**< \brief (TC1) COUNT8 Period Value */
|
||||
#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x42001818U) /**< \brief (TC1) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x42001819U) /**< \brief (TC1) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC1 peripheral ========== */
|
||||
#define TC1_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC1_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC1_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC1_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC1_DMAC_ID_MC_0 13
|
||||
#define TC1_DMAC_ID_MC_1 14
|
||||
#define TC1_DMAC_ID_MC_LSB 13
|
||||
#define TC1_DMAC_ID_MC_MSB 14
|
||||
#define TC1_DMAC_ID_MC_SIZE 2
|
||||
#define TC1_DMAC_ID_OVF 12 // Indexes of DMA Overflow trigger
|
||||
#define TC1_GCLK_ID 18 // Index of Generic Clock
|
||||
#define TC1_MASTER 1
|
||||
#define TC1_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC1_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC1_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD11_TC1_INSTANCE_ */
|
|
@ -0,0 +1,111 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC2
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD11_TC2_INSTANCE_
|
||||
#define _SAMD11_TC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC2_CTRLA (0x42001C00U) /**< \brief (TC2) Control A */
|
||||
#define REG_TC2_READREQ (0x42001C02U) /**< \brief (TC2) Read Request */
|
||||
#define REG_TC2_CTRLBCLR (0x42001C04U) /**< \brief (TC2) Control B Clear */
|
||||
#define REG_TC2_CTRLBSET (0x42001C05U) /**< \brief (TC2) Control B Set */
|
||||
#define REG_TC2_CTRLC (0x42001C06U) /**< \brief (TC2) Control C */
|
||||
#define REG_TC2_DBGCTRL (0x42001C08U) /**< \brief (TC2) Debug Control */
|
||||
#define REG_TC2_EVCTRL (0x42001C0AU) /**< \brief (TC2) Event Control */
|
||||
#define REG_TC2_INTENCLR (0x42001C0CU) /**< \brief (TC2) Interrupt Enable Clear */
|
||||
#define REG_TC2_INTENSET (0x42001C0DU) /**< \brief (TC2) Interrupt Enable Set */
|
||||
#define REG_TC2_INTFLAG (0x42001C0EU) /**< \brief (TC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TC2_STATUS (0x42001C0FU) /**< \brief (TC2) Status */
|
||||
#define REG_TC2_COUNT16_COUNT (0x42001C10U) /**< \brief (TC2) COUNT16 Counter Value */
|
||||
#define REG_TC2_COUNT16_CC0 (0x42001C18U) /**< \brief (TC2) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC2_COUNT16_CC1 (0x42001C1AU) /**< \brief (TC2) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC2_COUNT32_COUNT (0x42001C10U) /**< \brief (TC2) COUNT32 Counter Value */
|
||||
#define REG_TC2_COUNT32_CC0 (0x42001C18U) /**< \brief (TC2) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC2_COUNT32_CC1 (0x42001C1CU) /**< \brief (TC2) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC2_COUNT8_COUNT (0x42001C10U) /**< \brief (TC2) COUNT8 Counter Value */
|
||||
#define REG_TC2_COUNT8_PER (0x42001C14U) /**< \brief (TC2) COUNT8 Period Value */
|
||||
#define REG_TC2_COUNT8_CC0 (0x42001C18U) /**< \brief (TC2) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC2_COUNT8_CC1 (0x42001C19U) /**< \brief (TC2) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC2_CTRLA (*(RwReg16*)0x42001C00U) /**< \brief (TC2) Control A */
|
||||
#define REG_TC2_READREQ (*(RwReg16*)0x42001C02U) /**< \brief (TC2) Read Request */
|
||||
#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42001C04U) /**< \brief (TC2) Control B Clear */
|
||||
#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42001C05U) /**< \brief (TC2) Control B Set */
|
||||
#define REG_TC2_CTRLC (*(RwReg8 *)0x42001C06U) /**< \brief (TC2) Control C */
|
||||
#define REG_TC2_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (TC2) Debug Control */
|
||||
#define REG_TC2_EVCTRL (*(RwReg16*)0x42001C0AU) /**< \brief (TC2) Event Control */
|
||||
#define REG_TC2_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (TC2) Interrupt Enable Clear */
|
||||
#define REG_TC2_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (TC2) Interrupt Enable Set */
|
||||
#define REG_TC2_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (TC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TC2_STATUS (*(RoReg8 *)0x42001C0FU) /**< \brief (TC2) Status */
|
||||
#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42001C10U) /**< \brief (TC2) COUNT16 Counter Value */
|
||||
#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x42001C18U) /**< \brief (TC2) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x42001C1AU) /**< \brief (TC2) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42001C10U) /**< \brief (TC2) COUNT32 Counter Value */
|
||||
#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x42001C18U) /**< \brief (TC2) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42001C1CU) /**< \brief (TC2) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42001C10U) /**< \brief (TC2) COUNT8 Counter Value */
|
||||
#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x42001C14U) /**< \brief (TC2) COUNT8 Period Value */
|
||||
#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x42001C18U) /**< \brief (TC2) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x42001C19U) /**< \brief (TC2) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC2 peripheral ========== */
|
||||
#define TC2_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC2_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC2_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC2_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC2_DMAC_ID_MC_0 16
|
||||
#define TC2_DMAC_ID_MC_1 17
|
||||
#define TC2_DMAC_ID_MC_LSB 16
|
||||
#define TC2_DMAC_ID_MC_MSB 17
|
||||
#define TC2_DMAC_ID_MC_SIZE 2
|
||||
#define TC2_DMAC_ID_OVF 15 // Indexes of DMA Overflow trigger
|
||||
#define TC2_GCLK_ID 18 // Index of Generic Clock
|
||||
#define TC2_MASTER 0
|
||||
#define TC2_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC2_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC2_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD11_TC2_INSTANCE_ */
|
|
@ -1,114 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC3
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC3_INSTANCE_
|
||||
#define _SAMD21_TC3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */
|
||||
#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */
|
||||
#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */
|
||||
#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */
|
||||
#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */
|
||||
#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */
|
||||
#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */
|
||||
#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
|
||||
#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
|
||||
#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
|
||||
#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */
|
||||
#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
|
||||
#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
|
||||
#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
|
||||
#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
|
||||
#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
|
||||
#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
|
||||
#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
|
||||
#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
|
||||
#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
|
||||
#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
|
||||
#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
|
||||
#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
|
||||
#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
|
||||
#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
|
||||
#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
|
||||
#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
|
||||
#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
|
||||
#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
|
||||
#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
|
||||
#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC3 peripheral ========== */
|
||||
#define TC3_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC3_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC3_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC3_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC3_DMAC_ID_MC_0 25
|
||||
#define TC3_DMAC_ID_MC_1 26
|
||||
#define TC3_DMAC_ID_MC_LSB 25
|
||||
#define TC3_DMAC_ID_MC_MSB 26
|
||||
#define TC3_DMAC_ID_MC_SIZE 2
|
||||
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
|
||||
#define TC3_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TC3_MASTER 0
|
||||
#define TC3_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC3_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC3_INSTANCE_ */
|
|
@ -1,114 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC4
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC4_INSTANCE_
|
||||
#define _SAMD21_TC4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */
|
||||
#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */
|
||||
#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */
|
||||
#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */
|
||||
#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */
|
||||
#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */
|
||||
#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */
|
||||
#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
|
||||
#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
|
||||
#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
|
||||
#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */
|
||||
#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
|
||||
#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
|
||||
#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
|
||||
#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
|
||||
#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
|
||||
#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
|
||||
#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
|
||||
#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
|
||||
#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
|
||||
#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
|
||||
#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
|
||||
#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
|
||||
#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
|
||||
#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
|
||||
#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
|
||||
#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
|
||||
#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
|
||||
#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
|
||||
#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
|
||||
#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC4 peripheral ========== */
|
||||
#define TC4_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC4_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC4_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC4_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC4_DMAC_ID_MC_0 28
|
||||
#define TC4_DMAC_ID_MC_1 29
|
||||
#define TC4_DMAC_ID_MC_LSB 28
|
||||
#define TC4_DMAC_ID_MC_MSB 29
|
||||
#define TC4_DMAC_ID_MC_SIZE 2
|
||||
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
|
||||
#define TC4_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC4_MASTER 1
|
||||
#define TC4_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC4_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC4_INSTANCE_ */
|
|
@ -1,114 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC5
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC5_INSTANCE_
|
||||
#define _SAMD21_TC5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */
|
||||
#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */
|
||||
#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */
|
||||
#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */
|
||||
#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */
|
||||
#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */
|
||||
#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */
|
||||
#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
|
||||
#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
|
||||
#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
|
||||
#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */
|
||||
#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
|
||||
#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
|
||||
#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
|
||||
#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
|
||||
#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
|
||||
#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
|
||||
#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
|
||||
#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
|
||||
#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
|
||||
#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
|
||||
#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
|
||||
#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
|
||||
#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
|
||||
#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
|
||||
#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
|
||||
#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
|
||||
#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
|
||||
#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
|
||||
#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
|
||||
#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC5 peripheral ========== */
|
||||
#define TC5_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC5_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC5_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC5_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC5_DMAC_ID_MC_0 31
|
||||
#define TC5_DMAC_ID_MC_1 32
|
||||
#define TC5_DMAC_ID_MC_LSB 31
|
||||
#define TC5_DMAC_ID_MC_MSB 32
|
||||
#define TC5_DMAC_ID_MC_SIZE 2
|
||||
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
|
||||
#define TC5_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC5_MASTER 0
|
||||
#define TC5_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC5_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC5_INSTANCE_ */
|
|
@ -1,114 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC6
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC6_INSTANCE_
|
||||
#define _SAMD21_TC6_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC6 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */
|
||||
#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */
|
||||
#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */
|
||||
#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */
|
||||
#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */
|
||||
#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */
|
||||
#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */
|
||||
#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
|
||||
#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
|
||||
#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
|
||||
#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */
|
||||
#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
|
||||
#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
|
||||
#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
|
||||
#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
|
||||
#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
|
||||
#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
|
||||
#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
|
||||
#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
|
||||
#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
|
||||
#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
|
||||
#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
|
||||
#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
|
||||
#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
|
||||
#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
|
||||
#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
|
||||
#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
|
||||
#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
|
||||
#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
|
||||
#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
|
||||
#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC6 peripheral ========== */
|
||||
#define TC6_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC6_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC6_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC6_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC6_DMAC_ID_MC_0 34
|
||||
#define TC6_DMAC_ID_MC_1 35
|
||||
#define TC6_DMAC_ID_MC_LSB 34
|
||||
#define TC6_DMAC_ID_MC_MSB 35
|
||||
#define TC6_DMAC_ID_MC_SIZE 2
|
||||
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
|
||||
#define TC6_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC6_MASTER 1
|
||||
#define TC6_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC6_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC6_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC6_INSTANCE_ */
|
|
@ -1,114 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC7
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC7_INSTANCE_
|
||||
#define _SAMD21_TC7_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC7 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A */
|
||||
#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request */
|
||||
#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear */
|
||||
#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set */
|
||||
#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C */
|
||||
#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Control */
|
||||
#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control */
|
||||
#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
|
||||
#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
|
||||
#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
|
||||
#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status */
|
||||
#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
|
||||
#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
|
||||
#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
|
||||
#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
|
||||
#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
|
||||
#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
|
||||
#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
|
||||
#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
|
||||
#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
|
||||
#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
|
||||
#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
|
||||
#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
|
||||
#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
|
||||
#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
|
||||
#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
|
||||
#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
|
||||
#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
|
||||
#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
|
||||
#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
|
||||
#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC7 peripheral ========== */
|
||||
#define TC7_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC7_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC7_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC7_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC7_DMAC_ID_MC_0 37
|
||||
#define TC7_DMAC_ID_MC_1 38
|
||||
#define TC7_DMAC_ID_MC_LSB 37
|
||||
#define TC7_DMAC_ID_MC_MSB 38
|
||||
#define TC7_DMAC_ID_MC_SIZE 2
|
||||
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
|
||||
#define TC7_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC7_MASTER 0
|
||||
#define TC7_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC7_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC7_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC7_INSTANCE_ */
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for TCC0
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,96 +40,92 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC0_INSTANCE_
|
||||
#define _SAMD21_TCC0_INSTANCE_
|
||||
#ifndef _SAMD11_TCC0_INSTANCE_
|
||||
#define _SAMD11_TCC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#define REG_TCC0_CTRLA (0x42001400U) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (0x42001404U) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (0x42001405U) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (0x42001408U) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (0x4200140CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (0x42001410U) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (0x42001414U) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (0x42001418U) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (0x4200141EU) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (0x42001420U) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (0x42001424U) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (0x42001428U) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (0x4200142CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (0x42001430U) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (0x42001434U) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (0x42001438U) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (0x4200143CU) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (0x42001440U) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (0x42001444U) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (0x42001448U) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (0x4200144CU) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (0x42001450U) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (0x42001464U) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (0x42001468U) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (0x4200146CU) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (0x42001470U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (0x42001474U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (0x42001478U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (0x4200147CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#else
|
||||
#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#define REG_TCC0_CTRLA (*(RwReg *)0x42001400U) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001404U) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001405U) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001408U) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (*(RwReg *)0x4200140CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (*(RwReg *)0x42001410U) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001414U) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001418U) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200141EU) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (*(RwReg *)0x42001420U) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (*(RwReg *)0x42001424U) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (*(RwReg *)0x42001428U) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (*(RwReg *)0x4200142CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (*(RwReg *)0x42001430U) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (*(RwReg *)0x42001434U) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (*(RwReg16*)0x42001438U) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (*(RwReg *)0x4200143CU) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (*(RwReg *)0x42001440U) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (*(RwReg *)0x42001444U) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (*(RwReg *)0x42001448U) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (*(RwReg *)0x4200144CU) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (*(RwReg *)0x42001450U) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (*(RwReg16*)0x42001464U) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (*(RwReg *)0x42001468U) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (*(RwReg *)0x4200146CU) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (*(RwReg *)0x42001470U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (*(RwReg *)0x42001474U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (*(RwReg *)0x42001478U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (*(RwReg *)0x4200147CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC0 peripheral ========== */
|
||||
#define TCC0_CC_NUM 4 // Number of Compare/Capture units
|
||||
#define TCC0_DITHERING 1 // Dithering feature implemented
|
||||
#define TCC0_DMAC_ID_MC_0 14
|
||||
#define TCC0_DMAC_ID_MC_1 15
|
||||
#define TCC0_DMAC_ID_MC_2 16
|
||||
#define TCC0_DMAC_ID_MC_3 17
|
||||
#define TCC0_DMAC_ID_MC_LSB 14
|
||||
#define TCC0_DMAC_ID_MC_MSB 17
|
||||
#define TCC0_DMAC_ID_MC_0 8
|
||||
#define TCC0_DMAC_ID_MC_1 9
|
||||
#define TCC0_DMAC_ID_MC_2 10
|
||||
#define TCC0_DMAC_ID_MC_3 11
|
||||
#define TCC0_DMAC_ID_MC_LSB 8
|
||||
#define TCC0_DMAC_ID_MC_MSB 11
|
||||
#define TCC0_DMAC_ID_MC_SIZE 4
|
||||
#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC0_DMAC_ID_OVF 7 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
|
||||
#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
|
||||
#define TCC0_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC0_GCLK_ID 17 // Index of Generic Clock
|
||||
#define TCC0_MASTER 0
|
||||
#define TCC0_OTMX 1 // Output Matrix feature implemented
|
||||
#define TCC0_OW_NUM 8 // Number of Output Waveforms
|
||||
#define TCC0_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC0_SIZE 24
|
||||
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
|
||||
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC0_INSTANCE_ */
|
||||
#endif /* _SAMD11_TCC0_INSTANCE_ */
|
||||
|
|
|
@ -1,123 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC1_INSTANCE_
|
||||
#define _SAMD21_TCC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
|
||||
#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
|
||||
#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
|
||||
#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
|
||||
#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
|
||||
#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
|
||||
#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */
|
||||
#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
|
||||
#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
|
||||
#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
|
||||
#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
|
||||
#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
|
||||
#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
|
||||
#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
|
||||
#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
|
||||
#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
|
||||
#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
|
||||
#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
|
||||
#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
|
||||
#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
|
||||
#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
|
||||
#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
|
||||
#else
|
||||
#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
|
||||
#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
|
||||
#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
|
||||
#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
|
||||
#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
|
||||
#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
|
||||
#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */
|
||||
#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
|
||||
#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
|
||||
#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
|
||||
#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
|
||||
#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
|
||||
#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
|
||||
#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
|
||||
#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
|
||||
#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
|
||||
#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
|
||||
#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
|
||||
#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
|
||||
#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
|
||||
#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
|
||||
#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC1 peripheral ========== */
|
||||
#define TCC1_CC_NUM 2 // Number of Compare/Capture units
|
||||
#define TCC1_DITHERING 1 // Dithering feature implemented
|
||||
#define TCC1_DMAC_ID_MC_0 19
|
||||
#define TCC1_DMAC_ID_MC_1 20
|
||||
#define TCC1_DMAC_ID_MC_LSB 19
|
||||
#define TCC1_DMAC_ID_MC_MSB 20
|
||||
#define TCC1_DMAC_ID_MC_SIZE 2
|
||||
#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC1_EXT 24 // Coding of implemented extended features
|
||||
#define TCC1_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC1_MASTER 1
|
||||
#define TCC1_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC1_OW_NUM 4 // Number of Output Waveforms
|
||||
#define TCC1_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC1_SIZE 24
|
||||
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC1_INSTANCE_ */
|
|
@ -1,119 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC2
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC2_INSTANCE_
|
||||
#define _SAMD21_TCC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */
|
||||
#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */
|
||||
#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */
|
||||
#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
|
||||
#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
|
||||
#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
|
||||
#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */
|
||||
#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */
|
||||
#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */
|
||||
#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
|
||||
#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
|
||||
#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */
|
||||
#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */
|
||||
#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */
|
||||
#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */
|
||||
#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
|
||||
#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
|
||||
#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
|
||||
#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */
|
||||
#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
|
||||
#else
|
||||
#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */
|
||||
#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
|
||||
#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
|
||||
#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
|
||||
#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
|
||||
#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
|
||||
#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */
|
||||
#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
|
||||
#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */
|
||||
#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
|
||||
#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
|
||||
#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */
|
||||
#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */
|
||||
#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
|
||||
#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */
|
||||
#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
|
||||
#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
|
||||
#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
|
||||
#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
|
||||
#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC2 peripheral ========== */
|
||||
#define TCC2_CC_NUM 2 // Number of Compare/Capture units
|
||||
#define TCC2_DITHERING 0 // Dithering feature implemented
|
||||
#define TCC2_DMAC_ID_MC_0 22
|
||||
#define TCC2_DMAC_ID_MC_1 23
|
||||
#define TCC2_DMAC_ID_MC_LSB 22
|
||||
#define TCC2_DMAC_ID_MC_MSB 23
|
||||
#define TCC2_DMAC_ID_MC_SIZE 2
|
||||
#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC2_EXT 0 // Coding of implemented extended features
|
||||
#define TCC2_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TCC2_MASTER 0
|
||||
#define TCC2_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC2_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TCC2_PG 0 // Pattern Generation feature implemented
|
||||
#define TCC2_SIZE 16
|
||||
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC2_INSTANCE_ */
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for USB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_USB_INSTANCE_
|
||||
#define _SAMD21_USB_INSTANCE_
|
||||
#ifndef _SAMD11_USB_INSTANCE_
|
||||
#define _SAMD11_USB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USB peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -119,79 +116,6 @@
|
|||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
|
||||
#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */
|
||||
#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
|
||||
#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */
|
||||
#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
|
||||
#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
|
||||
#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
|
||||
#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
|
||||
#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
|
||||
#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
|
||||
#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
|
||||
#else
|
||||
#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
|
||||
#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
|
||||
|
@ -263,79 +187,6 @@
|
|||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
|
||||
#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
|
||||
#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
|
||||
#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
|
||||
#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
|
||||
#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
|
||||
#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
|
||||
#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
|
||||
#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
|
||||
#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
|
||||
#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for USB peripheral ========== */
|
||||
|
@ -344,4 +195,4 @@
|
|||
#define USB_GCLK_ID 6 // Index of Generic Clock
|
||||
#define USB_PIPE_NUM 8 // Number of USB pipes
|
||||
|
||||
#endif /* _SAMD21_USB_INSTANCE_ */
|
||||
#endif /* _SAMD11_USB_INSTANCE_ */
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* \brief Instance description for WDT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
|
@ -40,12 +40,9 @@
|
|||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_INSTANCE_
|
||||
#define _SAMD21_WDT_INSTANCE_
|
||||
#ifndef _SAMD11_WDT_INSTANCE_
|
||||
#define _SAMD11_WDT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
@ -71,4 +68,4 @@
|
|||
/* ========== Instance parameters for WDT peripheral ========== */
|
||||
#define WDT_GCLK_ID 3 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_WDT_INSTANCE_ */
|
||||
#endif /* _SAMD11_WDT_INSTANCE_ */
|
||||
|
|
|
@ -0,0 +1,360 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD11C14A
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD11C14A_PIO_
|
||||
#define _SAMD11C14A_PIO_
|
||||
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for CORE peripheral ========== */
|
||||
#define PIN_PA30G_CORE_SWCLK 30L /**< \brief CORE signal: SWCLK on PA30 mux G */
|
||||
#define MUX_PA30G_CORE_SWCLK 6L
|
||||
#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
|
||||
#define PORT_PA30G_CORE_SWCLK (1ul << 30)
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA08H_GCLK_IO0 8L /**< \brief GCLK signal: IO0 on PA08 mux H */
|
||||
#define MUX_PA08H_GCLK_IO0 7L
|
||||
#define PINMUX_PA08H_GCLK_IO0 ((PIN_PA08H_GCLK_IO0 << 16) | MUX_PA08H_GCLK_IO0)
|
||||
#define PORT_PA08H_GCLK_IO0 (1ul << 8)
|
||||
#define PIN_PA24H_GCLK_IO0 24L /**< \brief GCLK signal: IO0 on PA24 mux H */
|
||||
#define MUX_PA24H_GCLK_IO0 7L
|
||||
#define PINMUX_PA24H_GCLK_IO0 ((PIN_PA24H_GCLK_IO0 << 16) | MUX_PA24H_GCLK_IO0)
|
||||
#define PORT_PA24H_GCLK_IO0 (1ul << 24)
|
||||
#define PIN_PA25H_GCLK_IO0 25L /**< \brief GCLK signal: IO0 on PA25 mux H */
|
||||
#define MUX_PA25H_GCLK_IO0 7L
|
||||
#define PINMUX_PA25H_GCLK_IO0 ((PIN_PA25H_GCLK_IO0 << 16) | MUX_PA25H_GCLK_IO0)
|
||||
#define PORT_PA25H_GCLK_IO0 (1ul << 25)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA31H_GCLK_IO0 31L /**< \brief GCLK signal: IO0 on PA31 mux H */
|
||||
#define MUX_PA31H_GCLK_IO0 7L
|
||||
#define PINMUX_PA31H_GCLK_IO0 ((PIN_PA31H_GCLK_IO0 << 16) | MUX_PA31H_GCLK_IO0)
|
||||
#define PORT_PA31H_GCLK_IO0 (1ul << 31)
|
||||
#define PIN_PA09H_GCLK_IO1 9L /**< \brief GCLK signal: IO1 on PA09 mux H */
|
||||
#define MUX_PA09H_GCLK_IO1 7L
|
||||
#define PINMUX_PA09H_GCLK_IO1 ((PIN_PA09H_GCLK_IO1 << 16) | MUX_PA09H_GCLK_IO1)
|
||||
#define PORT_PA09H_GCLK_IO1 (1ul << 9)
|
||||
#define PIN_PA14H_GCLK_IO4 14L /**< \brief GCLK signal: IO4 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO4 7L
|
||||
#define PINMUX_PA14H_GCLK_IO4 ((PIN_PA14H_GCLK_IO4 << 16) | MUX_PA14H_GCLK_IO4)
|
||||
#define PORT_PA14H_GCLK_IO4 (1ul << 14)
|
||||
#define PIN_PA15H_GCLK_IO5 15L /**< \brief GCLK signal: IO5 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO5 7L
|
||||
#define PINMUX_PA15H_GCLK_IO5 ((PIN_PA15H_GCLK_IO5 << 16) | MUX_PA15H_GCLK_IO5)
|
||||
#define PORT_PA15H_GCLK_IO5 (1ul << 15)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA15A_EIC_EXTINT1 15L /**< \brief EIC signal: EXTINT1 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT1 ((PIN_PA15A_EIC_EXTINT1 << 16) | MUX_PA15A_EIC_EXTINT1)
|
||||
#define PORT_PA15A_EIC_EXTINT1 (1ul << 15)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA30A_EIC_EXTINT2 30L /**< \brief EIC signal: EXTINT2 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT2 ((PIN_PA30A_EIC_EXTINT2 << 16) | MUX_PA30A_EIC_EXTINT2)
|
||||
#define PORT_PA30A_EIC_EXTINT2 (1ul << 30)
|
||||
#define PIN_PA31A_EIC_EXTINT3 31L /**< \brief EIC signal: EXTINT3 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT3 ((PIN_PA31A_EIC_EXTINT3 << 16) | MUX_PA31A_EIC_EXTINT3)
|
||||
#define PORT_PA31A_EIC_EXTINT3 (1ul << 31)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA24A_EIC_EXTINT4 24L /**< \brief EIC signal: EXTINT4 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT4 ((PIN_PA24A_EIC_EXTINT4 << 16) | MUX_PA24A_EIC_EXTINT4)
|
||||
#define PORT_PA24A_EIC_EXTINT4 (1ul << 24)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA25A_EIC_EXTINT5 25L /**< \brief EIC signal: EXTINT5 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT5 ((PIN_PA25A_EIC_EXTINT5 << 16) | MUX_PA25A_EIC_EXTINT5)
|
||||
#define PORT_PA25A_EIC_EXTINT5 (1ul << 25)
|
||||
#define PIN_PA08A_EIC_EXTINT6 8L /**< \brief EIC signal: EXTINT6 on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA08A_EIC_EXTINT6 ((PIN_PA08A_EIC_EXTINT6 << 16) | MUX_PA08A_EIC_EXTINT6)
|
||||
#define PORT_PA08A_EIC_EXTINT6 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT7 9L /**< \brief EIC signal: EXTINT7 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT7 ((PIN_PA09A_EIC_EXTINT7 << 16) | MUX_PA09A_EIC_EXTINT7)
|
||||
#define PORT_PA09A_EIC_EXTINT7 (1ul << 9)
|
||||
#define PIN_PA14A_EIC_NMI 14L /**< \brief EIC signal: NMI on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_NMI 0L
|
||||
#define PINMUX_PA14A_EIC_NMI ((PIN_PA14A_EIC_NMI << 16) | MUX_PA14A_EIC_NMI)
|
||||
#define PORT_PA14A_EIC_NMI (1ul << 14)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA14C_SERCOM0_PAD0 14L /**< \brief SERCOM0 signal: PAD0 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA14C_SERCOM0_PAD0 ((PIN_PA14C_SERCOM0_PAD0 << 16) | MUX_PA14C_SERCOM0_PAD0)
|
||||
#define PORT_PA14C_SERCOM0_PAD0 (1ul << 14)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA15C_SERCOM0_PAD1 15L /**< \brief SERCOM0 signal: PAD1 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA15C_SERCOM0_PAD1 ((PIN_PA15C_SERCOM0_PAD1 << 16) | MUX_PA15C_SERCOM0_PAD1)
|
||||
#define PORT_PA15C_SERCOM0_PAD1 (1ul << 15)
|
||||
#define PIN_PA08D_SERCOM0_PAD2 8L /**< \brief SERCOM0 signal: PAD2 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA08D_SERCOM0_PAD2 ((PIN_PA08D_SERCOM0_PAD2 << 16) | MUX_PA08D_SERCOM0_PAD2)
|
||||
#define PORT_PA08D_SERCOM0_PAD2 (1ul << 8)
|
||||
#define PIN_PA04C_SERCOM0_PAD2 4L /**< \brief SERCOM0 signal: PAD2 on PA04 mux C */
|
||||
#define MUX_PA04C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA04C_SERCOM0_PAD2 ((PIN_PA04C_SERCOM0_PAD2 << 16) | MUX_PA04C_SERCOM0_PAD2)
|
||||
#define PORT_PA04C_SERCOM0_PAD2 (1ul << 4)
|
||||
#define PIN_PA09D_SERCOM0_PAD3 9L /**< \brief SERCOM0 signal: PAD3 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA09D_SERCOM0_PAD3 ((PIN_PA09D_SERCOM0_PAD3 << 16) | MUX_PA09D_SERCOM0_PAD3)
|
||||
#define PORT_PA09D_SERCOM0_PAD3 (1ul << 9)
|
||||
#define PIN_PA05C_SERCOM0_PAD3 5L /**< \brief SERCOM0 signal: PAD3 on PA05 mux C */
|
||||
#define MUX_PA05C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA05C_SERCOM0_PAD3 ((PIN_PA05C_SERCOM0_PAD3 << 16) | MUX_PA05C_SERCOM0_PAD3)
|
||||
#define PORT_PA05C_SERCOM0_PAD3 (1ul << 5)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA30C_SERCOM1_PAD0 30L /**< \brief SERCOM1 signal: PAD0 on PA30 mux C */
|
||||
#define MUX_PA30C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA30C_SERCOM1_PAD0 ((PIN_PA30C_SERCOM1_PAD0 << 16) | MUX_PA30C_SERCOM1_PAD0)
|
||||
#define PORT_PA30C_SERCOM1_PAD0 (1ul << 30)
|
||||
#define PIN_PA31C_SERCOM1_PAD1 31L /**< \brief SERCOM1 signal: PAD1 on PA31 mux C */
|
||||
#define MUX_PA31C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA31C_SERCOM1_PAD1 ((PIN_PA31C_SERCOM1_PAD1 << 16) | MUX_PA31C_SERCOM1_PAD1)
|
||||
#define PORT_PA31C_SERCOM1_PAD1 (1ul << 31)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA24C_SERCOM1_PAD2 24L /**< \brief SERCOM1 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM1_PAD2 ((PIN_PA24C_SERCOM1_PAD2 << 16) | MUX_PA24C_SERCOM1_PAD2)
|
||||
#define PORT_PA24C_SERCOM1_PAD2 (1ul << 24)
|
||||
#define PIN_PA08C_SERCOM1_PAD2 8L /**< \brief SERCOM1 signal: PAD2 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA08C_SERCOM1_PAD2 ((PIN_PA08C_SERCOM1_PAD2 << 16) | MUX_PA08C_SERCOM1_PAD2)
|
||||
#define PORT_PA08C_SERCOM1_PAD2 (1ul << 8)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA25C_SERCOM1_PAD3 25L /**< \brief SERCOM1 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM1_PAD3 ((PIN_PA25C_SERCOM1_PAD3 << 16) | MUX_PA25C_SERCOM1_PAD3)
|
||||
#define PORT_PA25C_SERCOM1_PAD3 (1ul << 25)
|
||||
#define PIN_PA09C_SERCOM1_PAD3 9L /**< \brief SERCOM1 signal: PAD3 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA09C_SERCOM1_PAD3 ((PIN_PA09C_SERCOM1_PAD3 << 16) | MUX_PA09C_SERCOM1_PAD3)
|
||||
#define PORT_PA09C_SERCOM1_PAD3 (1ul << 9)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04F_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux F */
|
||||
#define MUX_PA04F_TCC0_WO0 5L
|
||||
#define PINMUX_PA04F_TCC0_WO0 ((PIN_PA04F_TCC0_WO0 << 16) | MUX_PA04F_TCC0_WO0)
|
||||
#define PORT_PA04F_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA14F_TCC0_WO0 14L /**< \brief TCC0 signal: WO0 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO0 5L
|
||||
#define PINMUX_PA14F_TCC0_WO0 ((PIN_PA14F_TCC0_WO0 << 16) | MUX_PA14F_TCC0_WO0)
|
||||
#define PORT_PA14F_TCC0_WO0 (1ul << 14)
|
||||
#define PIN_PA05F_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux F */
|
||||
#define MUX_PA05F_TCC0_WO1 5L
|
||||
#define PINMUX_PA05F_TCC0_WO1 ((PIN_PA05F_TCC0_WO1 << 16) | MUX_PA05F_TCC0_WO1)
|
||||
#define PORT_PA05F_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA15F_TCC0_WO1 15L /**< \brief TCC0 signal: WO1 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO1 5L
|
||||
#define PINMUX_PA15F_TCC0_WO1 ((PIN_PA15F_TCC0_WO1 << 16) | MUX_PA15F_TCC0_WO1)
|
||||
#define PORT_PA15F_TCC0_WO1 (1ul << 15)
|
||||
#define PIN_PA30F_TCC0_WO2 30L /**< \brief TCC0 signal: WO2 on PA30 mux F */
|
||||
#define MUX_PA30F_TCC0_WO2 5L
|
||||
#define PINMUX_PA30F_TCC0_WO2 ((PIN_PA30F_TCC0_WO2 << 16) | MUX_PA30F_TCC0_WO2)
|
||||
#define PORT_PA30F_TCC0_WO2 (1ul << 30)
|
||||
#define PIN_PA08E_TCC0_WO2 8L /**< \brief TCC0 signal: WO2 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO2 4L
|
||||
#define PINMUX_PA08E_TCC0_WO2 ((PIN_PA08E_TCC0_WO2 << 16) | MUX_PA08E_TCC0_WO2)
|
||||
#define PORT_PA08E_TCC0_WO2 (1ul << 8)
|
||||
#define PIN_PA24E_TCC0_WO2 24L /**< \brief TCC0 signal: WO2 on PA24 mux E */
|
||||
#define MUX_PA24E_TCC0_WO2 4L
|
||||
#define PINMUX_PA24E_TCC0_WO2 ((PIN_PA24E_TCC0_WO2 << 16) | MUX_PA24E_TCC0_WO2)
|
||||
#define PORT_PA24E_TCC0_WO2 (1ul << 24)
|
||||
#define PIN_PA31F_TCC0_WO3 31L /**< \brief TCC0 signal: WO3 on PA31 mux F */
|
||||
#define MUX_PA31F_TCC0_WO3 5L
|
||||
#define PINMUX_PA31F_TCC0_WO3 ((PIN_PA31F_TCC0_WO3 << 16) | MUX_PA31F_TCC0_WO3)
|
||||
#define PORT_PA31F_TCC0_WO3 (1ul << 31)
|
||||
#define PIN_PA09E_TCC0_WO3 9L /**< \brief TCC0 signal: WO3 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO3 4L
|
||||
#define PINMUX_PA09E_TCC0_WO3 ((PIN_PA09E_TCC0_WO3 << 16) | MUX_PA09E_TCC0_WO3)
|
||||
#define PORT_PA09E_TCC0_WO3 (1ul << 9)
|
||||
#define PIN_PA25E_TCC0_WO3 25L /**< \brief TCC0 signal: WO3 on PA25 mux E */
|
||||
#define MUX_PA25E_TCC0_WO3 4L
|
||||
#define PINMUX_PA25E_TCC0_WO3 ((PIN_PA25E_TCC0_WO3 << 16) | MUX_PA25E_TCC0_WO3)
|
||||
#define PORT_PA25E_TCC0_WO3 (1ul << 25)
|
||||
#define PIN_PA24F_TCC0_WO4 24L /**< \brief TCC0 signal: WO4 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC0_WO4 5L
|
||||
#define PINMUX_PA24F_TCC0_WO4 ((PIN_PA24F_TCC0_WO4 << 16) | MUX_PA24F_TCC0_WO4)
|
||||
#define PORT_PA24F_TCC0_WO4 (1ul << 24)
|
||||
#define PIN_PA08F_TCC0_WO4 8L /**< \brief TCC0 signal: WO4 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC0_WO4 5L
|
||||
#define PINMUX_PA08F_TCC0_WO4 ((PIN_PA08F_TCC0_WO4 << 16) | MUX_PA08F_TCC0_WO4)
|
||||
#define PORT_PA08F_TCC0_WO4 (1ul << 8)
|
||||
#define PIN_PA25F_TCC0_WO5 25L /**< \brief TCC0 signal: WO5 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC0_WO5 5L
|
||||
#define PINMUX_PA25F_TCC0_WO5 ((PIN_PA25F_TCC0_WO5 << 16) | MUX_PA25F_TCC0_WO5)
|
||||
#define PORT_PA25F_TCC0_WO5 (1ul << 25)
|
||||
#define PIN_PA09F_TCC0_WO5 9L /**< \brief TCC0 signal: WO5 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC0_WO5 5L
|
||||
#define PINMUX_PA09F_TCC0_WO5 ((PIN_PA09F_TCC0_WO5 << 16) | MUX_PA09F_TCC0_WO5)
|
||||
#define PORT_PA09F_TCC0_WO5 (1ul << 9)
|
||||
/* ========== PORT definition for TC1 peripheral ========== */
|
||||
#define PIN_PA04E_TC1_WO0 4L /**< \brief TC1 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TC1_WO0 4L
|
||||
#define PINMUX_PA04E_TC1_WO0 ((PIN_PA04E_TC1_WO0 << 16) | MUX_PA04E_TC1_WO0)
|
||||
#define PORT_PA04E_TC1_WO0 (1ul << 4)
|
||||
#define PIN_PA14E_TC1_WO0 14L /**< \brief TC1 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC1_WO0 4L
|
||||
#define PINMUX_PA14E_TC1_WO0 ((PIN_PA14E_TC1_WO0 << 16) | MUX_PA14E_TC1_WO0)
|
||||
#define PORT_PA14E_TC1_WO0 (1ul << 14)
|
||||
#define PIN_PA05E_TC1_WO1 5L /**< \brief TC1 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TC1_WO1 4L
|
||||
#define PINMUX_PA05E_TC1_WO1 ((PIN_PA05E_TC1_WO1 << 16) | MUX_PA05E_TC1_WO1)
|
||||
#define PORT_PA05E_TC1_WO1 (1ul << 5)
|
||||
#define PIN_PA15E_TC1_WO1 15L /**< \brief TC1 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC1_WO1 4L
|
||||
#define PINMUX_PA15E_TC1_WO1 ((PIN_PA15E_TC1_WO1 << 16) | MUX_PA15E_TC1_WO1)
|
||||
#define PORT_PA15E_TC1_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC2 peripheral ========== */
|
||||
#define PIN_PA30E_TC2_WO0 30L /**< \brief TC2 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TC2_WO0 4L
|
||||
#define PINMUX_PA30E_TC2_WO0 ((PIN_PA30E_TC2_WO0 << 16) | MUX_PA30E_TC2_WO0)
|
||||
#define PORT_PA30E_TC2_WO0 (1ul << 30)
|
||||
#define PIN_PA31E_TC2_WO1 31L /**< \brief TC2 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TC2_WO1 4L
|
||||
#define PINMUX_PA31E_TC2_WO1 ((PIN_PA31E_TC2_WO1 << 16) | MUX_PA31E_TC2_WO1)
|
||||
#define PORT_PA31E_TC2_WO1 (1ul << 31)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA04B_ADC_AIN2 4L /**< \brief ADC signal: AIN2 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN2 1L
|
||||
#define PINMUX_PA04B_ADC_AIN2 ((PIN_PA04B_ADC_AIN2 << 16) | MUX_PA04B_ADC_AIN2)
|
||||
#define PORT_PA04B_ADC_AIN2 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN3 5L /**< \brief ADC signal: AIN3 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN3 1L
|
||||
#define PINMUX_PA05B_ADC_AIN3 ((PIN_PA05B_ADC_AIN3 << 16) | MUX_PA05B_ADC_AIN3)
|
||||
#define PORT_PA05B_ADC_AIN3 (1ul << 5)
|
||||
#define PIN_PA14B_ADC_AIN6 14L /**< \brief ADC signal: AIN6 on PA14 mux B */
|
||||
#define MUX_PA14B_ADC_AIN6 1L
|
||||
#define PINMUX_PA14B_ADC_AIN6 ((PIN_PA14B_ADC_AIN6 << 16) | MUX_PA14B_ADC_AIN6)
|
||||
#define PORT_PA14B_ADC_AIN6 (1ul << 14)
|
||||
#define PIN_PA15B_ADC_AIN7 15L /**< \brief ADC signal: AIN7 on PA15 mux B */
|
||||
#define MUX_PA15B_ADC_AIN7 1L
|
||||
#define PINMUX_PA15B_ADC_AIN7 ((PIN_PA15B_ADC_AIN7 << 16) | MUX_PA15B_ADC_AIN7)
|
||||
#define PORT_PA15B_ADC_AIN7 (1ul << 15)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA14G_AC_CMP0 14L /**< \brief AC signal: CMP0 on PA14 mux G */
|
||||
#define MUX_PA14G_AC_CMP0 6L
|
||||
#define PINMUX_PA14G_AC_CMP0 ((PIN_PA14G_AC_CMP0 << 16) | MUX_PA14G_AC_CMP0)
|
||||
#define PORT_PA14G_AC_CMP0 (1ul << 14)
|
||||
#define PIN_PA15G_AC_CMP1 15L /**< \brief AC signal: CMP1 on PA15 mux G */
|
||||
#define MUX_PA15G_AC_CMP1 6L
|
||||
#define PINMUX_PA15G_AC_CMP1 ((PIN_PA15G_AC_CMP1 << 16) | MUX_PA15G_AC_CMP1)
|
||||
#define PORT_PA15G_AC_CMP1 (1ul << 15)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
|
||||
#endif /* _SAMD11C14A_PIO_ */
|
|
@ -0,0 +1,637 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD11D14AM
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD11D14AM_PIO_
|
||||
#define _SAMD11D14AM_PIO_
|
||||
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for CORE peripheral ========== */
|
||||
#define PIN_PA30G_CORE_SWCLK 30L /**< \brief CORE signal: SWCLK on PA30 mux G */
|
||||
#define MUX_PA30G_CORE_SWCLK 6L
|
||||
#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
|
||||
#define PORT_PA30G_CORE_SWCLK (1ul << 30)
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA08H_GCLK_IO0 8L /**< \brief GCLK signal: IO0 on PA08 mux H */
|
||||
#define MUX_PA08H_GCLK_IO0 7L
|
||||
#define PINMUX_PA08H_GCLK_IO0 ((PIN_PA08H_GCLK_IO0 << 16) | MUX_PA08H_GCLK_IO0)
|
||||
#define PORT_PA08H_GCLK_IO0 (1ul << 8)
|
||||
#define PIN_PA24H_GCLK_IO0 24L /**< \brief GCLK signal: IO0 on PA24 mux H */
|
||||
#define MUX_PA24H_GCLK_IO0 7L
|
||||
#define PINMUX_PA24H_GCLK_IO0 ((PIN_PA24H_GCLK_IO0 << 16) | MUX_PA24H_GCLK_IO0)
|
||||
#define PORT_PA24H_GCLK_IO0 (1ul << 24)
|
||||
#define PIN_PA25H_GCLK_IO0 25L /**< \brief GCLK signal: IO0 on PA25 mux H */
|
||||
#define MUX_PA25H_GCLK_IO0 7L
|
||||
#define PINMUX_PA25H_GCLK_IO0 ((PIN_PA25H_GCLK_IO0 << 16) | MUX_PA25H_GCLK_IO0)
|
||||
#define PORT_PA25H_GCLK_IO0 (1ul << 25)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA31H_GCLK_IO0 31L /**< \brief GCLK signal: IO0 on PA31 mux H */
|
||||
#define MUX_PA31H_GCLK_IO0 7L
|
||||
#define PINMUX_PA31H_GCLK_IO0 ((PIN_PA31H_GCLK_IO0 << 16) | MUX_PA31H_GCLK_IO0)
|
||||
#define PORT_PA31H_GCLK_IO0 (1ul << 31)
|
||||
#define PIN_PA09H_GCLK_IO1 9L /**< \brief GCLK signal: IO1 on PA09 mux H */
|
||||
#define MUX_PA09H_GCLK_IO1 7L
|
||||
#define PINMUX_PA09H_GCLK_IO1 ((PIN_PA09H_GCLK_IO1 << 16) | MUX_PA09H_GCLK_IO1)
|
||||
#define PORT_PA09H_GCLK_IO1 (1ul << 9)
|
||||
#define PIN_PA22H_GCLK_IO1 22L /**< \brief GCLK signal: IO1 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO1 7L
|
||||
#define PINMUX_PA22H_GCLK_IO1 ((PIN_PA22H_GCLK_IO1 << 16) | MUX_PA22H_GCLK_IO1)
|
||||
#define PORT_PA22H_GCLK_IO1 (1ul << 22)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA23H_GCLK_IO2 23L /**< \brief GCLK signal: IO2 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO2 7L
|
||||
#define PINMUX_PA23H_GCLK_IO2 ((PIN_PA23H_GCLK_IO2 << 16) | MUX_PA23H_GCLK_IO2)
|
||||
#define PORT_PA23H_GCLK_IO2 (1ul << 23)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA14H_GCLK_IO4 14L /**< \brief GCLK signal: IO4 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO4 7L
|
||||
#define PINMUX_PA14H_GCLK_IO4 ((PIN_PA14H_GCLK_IO4 << 16) | MUX_PA14H_GCLK_IO4)
|
||||
#define PORT_PA14H_GCLK_IO4 (1ul << 14)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA15H_GCLK_IO5 15L /**< \brief GCLK signal: IO5 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO5 7L
|
||||
#define PINMUX_PA15H_GCLK_IO5 ((PIN_PA15H_GCLK_IO5 << 16) | MUX_PA15H_GCLK_IO5)
|
||||
#define PORT_PA15H_GCLK_IO5 (1ul << 15)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA15A_EIC_EXTINT1 15L /**< \brief EIC signal: EXTINT1 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT1 ((PIN_PA15A_EIC_EXTINT1 << 16) | MUX_PA15A_EIC_EXTINT1)
|
||||
#define PORT_PA15A_EIC_EXTINT1 (1ul << 15)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA10A_EIC_EXTINT2 10L /**< \brief EIC signal: EXTINT2 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT2 ((PIN_PA10A_EIC_EXTINT2 << 16) | MUX_PA10A_EIC_EXTINT2)
|
||||
#define PORT_PA10A_EIC_EXTINT2 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT2 30L /**< \brief EIC signal: EXTINT2 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT2 ((PIN_PA30A_EIC_EXTINT2 << 16) | MUX_PA30A_EIC_EXTINT2)
|
||||
#define PORT_PA30A_EIC_EXTINT2 (1ul << 30)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA11A_EIC_EXTINT3 11L /**< \brief EIC signal: EXTINT3 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT3 ((PIN_PA11A_EIC_EXTINT3 << 16) | MUX_PA11A_EIC_EXTINT3)
|
||||
#define PORT_PA11A_EIC_EXTINT3 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT3 31L /**< \brief EIC signal: EXTINT3 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT3 ((PIN_PA31A_EIC_EXTINT3 << 16) | MUX_PA31A_EIC_EXTINT3)
|
||||
#define PORT_PA31A_EIC_EXTINT3 (1ul << 31)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA24A_EIC_EXTINT4 24L /**< \brief EIC signal: EXTINT4 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT4 ((PIN_PA24A_EIC_EXTINT4 << 16) | MUX_PA24A_EIC_EXTINT4)
|
||||
#define PORT_PA24A_EIC_EXTINT4 (1ul << 24)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA25A_EIC_EXTINT5 25L /**< \brief EIC signal: EXTINT5 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT5 ((PIN_PA25A_EIC_EXTINT5 << 16) | MUX_PA25A_EIC_EXTINT5)
|
||||
#define PORT_PA25A_EIC_EXTINT5 (1ul << 25)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA08A_EIC_EXTINT6 8L /**< \brief EIC signal: EXTINT6 on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA08A_EIC_EXTINT6 ((PIN_PA08A_EIC_EXTINT6 << 16) | MUX_PA08A_EIC_EXTINT6)
|
||||
#define PORT_PA08A_EIC_EXTINT6 (1ul << 8)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA09A_EIC_EXTINT7 9L /**< \brief EIC signal: EXTINT7 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT7 ((PIN_PA09A_EIC_EXTINT7 << 16) | MUX_PA09A_EIC_EXTINT7)
|
||||
#define PORT_PA09A_EIC_EXTINT7 (1ul << 9)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA27A_EIC_EXTINT7 27L /**< \brief EIC signal: EXTINT7 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT7 ((PIN_PA27A_EIC_EXTINT7 << 16) | MUX_PA27A_EIC_EXTINT7)
|
||||
#define PORT_PA27A_EIC_EXTINT7 (1ul << 27)
|
||||
#define PIN_PA14A_EIC_NMI 14L /**< \brief EIC signal: NMI on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_NMI 0L
|
||||
#define PINMUX_PA14A_EIC_NMI ((PIN_PA14A_EIC_NMI << 16) | MUX_PA14A_EIC_NMI)
|
||||
#define PORT_PA14A_EIC_NMI (1ul << 14)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA14C_SERCOM0_PAD0 14L /**< \brief SERCOM0 signal: PAD0 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA14C_SERCOM0_PAD0 ((PIN_PA14C_SERCOM0_PAD0 << 16) | MUX_PA14C_SERCOM0_PAD0)
|
||||
#define PORT_PA14C_SERCOM0_PAD0 (1ul << 14)
|
||||
#define PIN_PA06C_SERCOM0_PAD0 6L /**< \brief SERCOM0 signal: PAD0 on PA06 mux C */
|
||||
#define MUX_PA06C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA06C_SERCOM0_PAD0 ((PIN_PA06C_SERCOM0_PAD0 << 16) | MUX_PA06C_SERCOM0_PAD0)
|
||||
#define PORT_PA06C_SERCOM0_PAD0 (1ul << 6)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA15C_SERCOM0_PAD1 15L /**< \brief SERCOM0 signal: PAD1 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA15C_SERCOM0_PAD1 ((PIN_PA15C_SERCOM0_PAD1 << 16) | MUX_PA15C_SERCOM0_PAD1)
|
||||
#define PORT_PA15C_SERCOM0_PAD1 (1ul << 15)
|
||||
#define PIN_PA07C_SERCOM0_PAD1 7L /**< \brief SERCOM0 signal: PAD1 on PA07 mux C */
|
||||
#define MUX_PA07C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA07C_SERCOM0_PAD1 ((PIN_PA07C_SERCOM0_PAD1 << 16) | MUX_PA07C_SERCOM0_PAD1)
|
||||
#define PORT_PA07C_SERCOM0_PAD1 (1ul << 7)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA08D_SERCOM0_PAD2 8L /**< \brief SERCOM0 signal: PAD2 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA08D_SERCOM0_PAD2 ((PIN_PA08D_SERCOM0_PAD2 << 16) | MUX_PA08D_SERCOM0_PAD2)
|
||||
#define PORT_PA08D_SERCOM0_PAD2 (1ul << 8)
|
||||
#define PIN_PA04C_SERCOM0_PAD2 4L /**< \brief SERCOM0 signal: PAD2 on PA04 mux C */
|
||||
#define MUX_PA04C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA04C_SERCOM0_PAD2 ((PIN_PA04C_SERCOM0_PAD2 << 16) | MUX_PA04C_SERCOM0_PAD2)
|
||||
#define PORT_PA04C_SERCOM0_PAD2 (1ul << 4)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA09D_SERCOM0_PAD3 9L /**< \brief SERCOM0 signal: PAD3 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA09D_SERCOM0_PAD3 ((PIN_PA09D_SERCOM0_PAD3 << 16) | MUX_PA09D_SERCOM0_PAD3)
|
||||
#define PORT_PA09D_SERCOM0_PAD3 (1ul << 9)
|
||||
#define PIN_PA05C_SERCOM0_PAD3 5L /**< \brief SERCOM0 signal: PAD3 on PA05 mux C */
|
||||
#define MUX_PA05C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA05C_SERCOM0_PAD3 ((PIN_PA05C_SERCOM0_PAD3 << 16) | MUX_PA05C_SERCOM0_PAD3)
|
||||
#define PORT_PA05C_SERCOM0_PAD3 (1ul << 5)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA22C_SERCOM1_PAD0 22L /**< \brief SERCOM1 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM1_PAD0 ((PIN_PA22C_SERCOM1_PAD0 << 16) | MUX_PA22C_SERCOM1_PAD0)
|
||||
#define PORT_PA22C_SERCOM1_PAD0 (1ul << 22)
|
||||
#define PIN_PA30C_SERCOM1_PAD0 30L /**< \brief SERCOM1 signal: PAD0 on PA30 mux C */
|
||||
#define MUX_PA30C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA30C_SERCOM1_PAD0 ((PIN_PA30C_SERCOM1_PAD0 << 16) | MUX_PA30C_SERCOM1_PAD0)
|
||||
#define PORT_PA30C_SERCOM1_PAD0 (1ul << 30)
|
||||
#define PIN_PA23C_SERCOM1_PAD1 23L /**< \brief SERCOM1 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM1_PAD1 ((PIN_PA23C_SERCOM1_PAD1 << 16) | MUX_PA23C_SERCOM1_PAD1)
|
||||
#define PORT_PA23C_SERCOM1_PAD1 (1ul << 23)
|
||||
#define PIN_PA31C_SERCOM1_PAD1 31L /**< \brief SERCOM1 signal: PAD1 on PA31 mux C */
|
||||
#define MUX_PA31C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA31C_SERCOM1_PAD1 ((PIN_PA31C_SERCOM1_PAD1 << 16) | MUX_PA31C_SERCOM1_PAD1)
|
||||
#define PORT_PA31C_SERCOM1_PAD1 (1ul << 31)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA16C_SERCOM1_PAD2 16L /**< \brief SERCOM1 signal: PAD2 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD2 ((PIN_PA16C_SERCOM1_PAD2 << 16) | MUX_PA16C_SERCOM1_PAD2)
|
||||
#define PORT_PA16C_SERCOM1_PAD2 (1ul << 16)
|
||||
#define PIN_PA24C_SERCOM1_PAD2 24L /**< \brief SERCOM1 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM1_PAD2 ((PIN_PA24C_SERCOM1_PAD2 << 16) | MUX_PA24C_SERCOM1_PAD2)
|
||||
#define PORT_PA24C_SERCOM1_PAD2 (1ul << 24)
|
||||
#define PIN_PA08C_SERCOM1_PAD2 8L /**< \brief SERCOM1 signal: PAD2 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA08C_SERCOM1_PAD2 ((PIN_PA08C_SERCOM1_PAD2 << 16) | MUX_PA08C_SERCOM1_PAD2)
|
||||
#define PORT_PA08C_SERCOM1_PAD2 (1ul << 8)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA17C_SERCOM1_PAD3 17L /**< \brief SERCOM1 signal: PAD3 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD3 ((PIN_PA17C_SERCOM1_PAD3 << 16) | MUX_PA17C_SERCOM1_PAD3)
|
||||
#define PORT_PA17C_SERCOM1_PAD3 (1ul << 17)
|
||||
#define PIN_PA25C_SERCOM1_PAD3 25L /**< \brief SERCOM1 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM1_PAD3 ((PIN_PA25C_SERCOM1_PAD3 << 16) | MUX_PA25C_SERCOM1_PAD3)
|
||||
#define PORT_PA25C_SERCOM1_PAD3 (1ul << 25)
|
||||
#define PIN_PA09C_SERCOM1_PAD3 9L /**< \brief SERCOM1 signal: PAD3 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA09C_SERCOM1_PAD3 ((PIN_PA09C_SERCOM1_PAD3 << 16) | MUX_PA09C_SERCOM1_PAD3)
|
||||
#define PORT_PA09C_SERCOM1_PAD3 (1ul << 9)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA14D_SERCOM2_PAD0 14L /**< \brief SERCOM2 signal: PAD0 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA14D_SERCOM2_PAD0 ((PIN_PA14D_SERCOM2_PAD0 << 16) | MUX_PA14D_SERCOM2_PAD0)
|
||||
#define PORT_PA14D_SERCOM2_PAD0 (1ul << 14)
|
||||
#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0)
|
||||
#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22)
|
||||
#define PIN_PA15D_SERCOM2_PAD1 15L /**< \brief SERCOM2 signal: PAD1 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA15D_SERCOM2_PAD1 ((PIN_PA15D_SERCOM2_PAD1 << 16) | MUX_PA15D_SERCOM2_PAD1)
|
||||
#define PORT_PA15D_SERCOM2_PAD1 (1ul << 15)
|
||||
#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1)
|
||||
#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA16D_SERCOM2_PAD2 16L /**< \brief SERCOM2 signal: PAD2 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA16D_SERCOM2_PAD2 ((PIN_PA16D_SERCOM2_PAD2 << 16) | MUX_PA16D_SERCOM2_PAD2)
|
||||
#define PORT_PA16D_SERCOM2_PAD2 (1ul << 16)
|
||||
#define PIN_PA24D_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM2_PAD2 ((PIN_PA24D_SERCOM2_PAD2 << 16) | MUX_PA24D_SERCOM2_PAD2)
|
||||
#define PORT_PA24D_SERCOM2_PAD2 (1ul << 24)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA17D_SERCOM2_PAD3 17L /**< \brief SERCOM2 signal: PAD3 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA17D_SERCOM2_PAD3 ((PIN_PA17D_SERCOM2_PAD3 << 16) | MUX_PA17D_SERCOM2_PAD3)
|
||||
#define PORT_PA17D_SERCOM2_PAD3 (1ul << 17)
|
||||
#define PIN_PA25D_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM2_PAD3 ((PIN_PA25D_SERCOM2_PAD3 << 16) | MUX_PA25D_SERCOM2_PAD3)
|
||||
#define PORT_PA25D_SERCOM2_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04F_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux F */
|
||||
#define MUX_PA04F_TCC0_WO0 5L
|
||||
#define PINMUX_PA04F_TCC0_WO0 ((PIN_PA04F_TCC0_WO0 << 16) | MUX_PA04F_TCC0_WO0)
|
||||
#define PORT_PA04F_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA14F_TCC0_WO0 14L /**< \brief TCC0 signal: WO0 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO0 5L
|
||||
#define PINMUX_PA14F_TCC0_WO0 ((PIN_PA14F_TCC0_WO0 << 16) | MUX_PA14F_TCC0_WO0)
|
||||
#define PORT_PA14F_TCC0_WO0 (1ul << 14)
|
||||
#define PIN_PA05F_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux F */
|
||||
#define MUX_PA05F_TCC0_WO1 5L
|
||||
#define PINMUX_PA05F_TCC0_WO1 ((PIN_PA05F_TCC0_WO1 << 16) | MUX_PA05F_TCC0_WO1)
|
||||
#define PORT_PA05F_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA15F_TCC0_WO1 15L /**< \brief TCC0 signal: WO1 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO1 5L
|
||||
#define PINMUX_PA15F_TCC0_WO1 ((PIN_PA15F_TCC0_WO1 << 16) | MUX_PA15F_TCC0_WO1)
|
||||
#define PORT_PA15F_TCC0_WO1 (1ul << 15)
|
||||
#define PIN_PA06F_TCC0_WO2 6L /**< \brief TCC0 signal: WO2 on PA06 mux F */
|
||||
#define MUX_PA06F_TCC0_WO2 5L
|
||||
#define PINMUX_PA06F_TCC0_WO2 ((PIN_PA06F_TCC0_WO2 << 16) | MUX_PA06F_TCC0_WO2)
|
||||
#define PORT_PA06F_TCC0_WO2 (1ul << 6)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA30F_TCC0_WO2 30L /**< \brief TCC0 signal: WO2 on PA30 mux F */
|
||||
#define MUX_PA30F_TCC0_WO2 5L
|
||||
#define PINMUX_PA30F_TCC0_WO2 ((PIN_PA30F_TCC0_WO2 << 16) | MUX_PA30F_TCC0_WO2)
|
||||
#define PORT_PA30F_TCC0_WO2 (1ul << 30)
|
||||
#define PIN_PA08E_TCC0_WO2 8L /**< \brief TCC0 signal: WO2 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO2 4L
|
||||
#define PINMUX_PA08E_TCC0_WO2 ((PIN_PA08E_TCC0_WO2 << 16) | MUX_PA08E_TCC0_WO2)
|
||||
#define PORT_PA08E_TCC0_WO2 (1ul << 8)
|
||||
#define PIN_PA24E_TCC0_WO2 24L /**< \brief TCC0 signal: WO2 on PA24 mux E */
|
||||
#define MUX_PA24E_TCC0_WO2 4L
|
||||
#define PINMUX_PA24E_TCC0_WO2 ((PIN_PA24E_TCC0_WO2 << 16) | MUX_PA24E_TCC0_WO2)
|
||||
#define PORT_PA24E_TCC0_WO2 (1ul << 24)
|
||||
#define PIN_PA07F_TCC0_WO3 7L /**< \brief TCC0 signal: WO3 on PA07 mux F */
|
||||
#define MUX_PA07F_TCC0_WO3 5L
|
||||
#define PINMUX_PA07F_TCC0_WO3 ((PIN_PA07F_TCC0_WO3 << 16) | MUX_PA07F_TCC0_WO3)
|
||||
#define PORT_PA07F_TCC0_WO3 (1ul << 7)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA31F_TCC0_WO3 31L /**< \brief TCC0 signal: WO3 on PA31 mux F */
|
||||
#define MUX_PA31F_TCC0_WO3 5L
|
||||
#define PINMUX_PA31F_TCC0_WO3 ((PIN_PA31F_TCC0_WO3 << 16) | MUX_PA31F_TCC0_WO3)
|
||||
#define PORT_PA31F_TCC0_WO3 (1ul << 31)
|
||||
#define PIN_PA09E_TCC0_WO3 9L /**< \brief TCC0 signal: WO3 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO3 4L
|
||||
#define PINMUX_PA09E_TCC0_WO3 ((PIN_PA09E_TCC0_WO3 << 16) | MUX_PA09E_TCC0_WO3)
|
||||
#define PORT_PA09E_TCC0_WO3 (1ul << 9)
|
||||
#define PIN_PA25E_TCC0_WO3 25L /**< \brief TCC0 signal: WO3 on PA25 mux E */
|
||||
#define MUX_PA25E_TCC0_WO3 4L
|
||||
#define PINMUX_PA25E_TCC0_WO3 ((PIN_PA25E_TCC0_WO3 << 16) | MUX_PA25E_TCC0_WO3)
|
||||
#define PORT_PA25E_TCC0_WO3 (1ul << 25)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA24F_TCC0_WO4 24L /**< \brief TCC0 signal: WO4 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC0_WO4 5L
|
||||
#define PINMUX_PA24F_TCC0_WO4 ((PIN_PA24F_TCC0_WO4 << 16) | MUX_PA24F_TCC0_WO4)
|
||||
#define PORT_PA24F_TCC0_WO4 (1ul << 24)
|
||||
#define PIN_PA08F_TCC0_WO4 8L /**< \brief TCC0 signal: WO4 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC0_WO4 5L
|
||||
#define PINMUX_PA08F_TCC0_WO4 ((PIN_PA08F_TCC0_WO4 << 16) | MUX_PA08F_TCC0_WO4)
|
||||
#define PORT_PA08F_TCC0_WO4 (1ul << 8)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA25F_TCC0_WO5 25L /**< \brief TCC0 signal: WO5 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC0_WO5 5L
|
||||
#define PINMUX_PA25F_TCC0_WO5 ((PIN_PA25F_TCC0_WO5 << 16) | MUX_PA25F_TCC0_WO5)
|
||||
#define PORT_PA25F_TCC0_WO5 (1ul << 25)
|
||||
#define PIN_PA09F_TCC0_WO5 9L /**< \brief TCC0 signal: WO5 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC0_WO5 5L
|
||||
#define PINMUX_PA09F_TCC0_WO5 ((PIN_PA09F_TCC0_WO5 << 16) | MUX_PA09F_TCC0_WO5)
|
||||
#define PORT_PA09F_TCC0_WO5 (1ul << 9)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TC1 peripheral ========== */
|
||||
#define PIN_PA04E_TC1_WO0 4L /**< \brief TC1 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TC1_WO0 4L
|
||||
#define PINMUX_PA04E_TC1_WO0 ((PIN_PA04E_TC1_WO0 << 16) | MUX_PA04E_TC1_WO0)
|
||||
#define PORT_PA04E_TC1_WO0 (1ul << 4)
|
||||
#define PIN_PA14E_TC1_WO0 14L /**< \brief TC1 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC1_WO0 4L
|
||||
#define PINMUX_PA14E_TC1_WO0 ((PIN_PA14E_TC1_WO0 << 16) | MUX_PA14E_TC1_WO0)
|
||||
#define PORT_PA14E_TC1_WO0 (1ul << 14)
|
||||
#define PIN_PA16E_TC1_WO0 16L /**< \brief TC1 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TC1_WO0 4L
|
||||
#define PINMUX_PA16E_TC1_WO0 ((PIN_PA16E_TC1_WO0 << 16) | MUX_PA16E_TC1_WO0)
|
||||
#define PORT_PA16E_TC1_WO0 (1ul << 16)
|
||||
#define PIN_PA22E_TC1_WO0 22L /**< \brief TC1 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC1_WO0 4L
|
||||
#define PINMUX_PA22E_TC1_WO0 ((PIN_PA22E_TC1_WO0 << 16) | MUX_PA22E_TC1_WO0)
|
||||
#define PORT_PA22E_TC1_WO0 (1ul << 22)
|
||||
#define PIN_PA05E_TC1_WO1 5L /**< \brief TC1 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TC1_WO1 4L
|
||||
#define PINMUX_PA05E_TC1_WO1 ((PIN_PA05E_TC1_WO1 << 16) | MUX_PA05E_TC1_WO1)
|
||||
#define PORT_PA05E_TC1_WO1 (1ul << 5)
|
||||
#define PIN_PA15E_TC1_WO1 15L /**< \brief TC1 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC1_WO1 4L
|
||||
#define PINMUX_PA15E_TC1_WO1 ((PIN_PA15E_TC1_WO1 << 16) | MUX_PA15E_TC1_WO1)
|
||||
#define PORT_PA15E_TC1_WO1 (1ul << 15)
|
||||
#define PIN_PA17E_TC1_WO1 17L /**< \brief TC1 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TC1_WO1 4L
|
||||
#define PINMUX_PA17E_TC1_WO1 ((PIN_PA17E_TC1_WO1 << 16) | MUX_PA17E_TC1_WO1)
|
||||
#define PORT_PA17E_TC1_WO1 (1ul << 17)
|
||||
#define PIN_PA23E_TC1_WO1 23L /**< \brief TC1 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC1_WO1 4L
|
||||
#define PINMUX_PA23E_TC1_WO1 ((PIN_PA23E_TC1_WO1 << 16) | MUX_PA23E_TC1_WO1)
|
||||
#define PORT_PA23E_TC1_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC2 peripheral ========== */
|
||||
#define PIN_PA06E_TC2_WO0 6L /**< \brief TC2 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TC2_WO0 4L
|
||||
#define PINMUX_PA06E_TC2_WO0 ((PIN_PA06E_TC2_WO0 << 16) | MUX_PA06E_TC2_WO0)
|
||||
#define PORT_PA06E_TC2_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TC2_WO0 10L /**< \brief TC2 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TC2_WO0 4L
|
||||
#define PINMUX_PA10E_TC2_WO0 ((PIN_PA10E_TC2_WO0 << 16) | MUX_PA10E_TC2_WO0)
|
||||
#define PORT_PA10E_TC2_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TC2_WO0 30L /**< \brief TC2 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TC2_WO0 4L
|
||||
#define PINMUX_PA30E_TC2_WO0 ((PIN_PA30E_TC2_WO0 << 16) | MUX_PA30E_TC2_WO0)
|
||||
#define PORT_PA30E_TC2_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TC2_WO1 7L /**< \brief TC2 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TC2_WO1 4L
|
||||
#define PINMUX_PA07E_TC2_WO1 ((PIN_PA07E_TC2_WO1 << 16) | MUX_PA07E_TC2_WO1)
|
||||
#define PORT_PA07E_TC2_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TC2_WO1 11L /**< \brief TC2 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TC2_WO1 4L
|
||||
#define PINMUX_PA11E_TC2_WO1 ((PIN_PA11E_TC2_WO1 << 16) | MUX_PA11E_TC2_WO1)
|
||||
#define PORT_PA11E_TC2_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TC2_WO1 31L /**< \brief TC2 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TC2_WO1 4L
|
||||
#define PINMUX_PA31E_TC2_WO1 ((PIN_PA31E_TC2_WO1 << 16) | MUX_PA31E_TC2_WO1)
|
||||
#define PORT_PA31E_TC2_WO1 (1ul << 31)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN2 4L /**< \brief ADC signal: AIN2 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN2 1L
|
||||
#define PINMUX_PA04B_ADC_AIN2 ((PIN_PA04B_ADC_AIN2 << 16) | MUX_PA04B_ADC_AIN2)
|
||||
#define PORT_PA04B_ADC_AIN2 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN3 5L /**< \brief ADC signal: AIN3 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN3 1L
|
||||
#define PINMUX_PA05B_ADC_AIN3 ((PIN_PA05B_ADC_AIN3 << 16) | MUX_PA05B_ADC_AIN3)
|
||||
#define PORT_PA05B_ADC_AIN3 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN4 6L /**< \brief ADC signal: AIN4 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN4 1L
|
||||
#define PINMUX_PA06B_ADC_AIN4 ((PIN_PA06B_ADC_AIN4 << 16) | MUX_PA06B_ADC_AIN4)
|
||||
#define PORT_PA06B_ADC_AIN4 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN5 7L /**< \brief ADC signal: AIN5 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN5 1L
|
||||
#define PINMUX_PA07B_ADC_AIN5 ((PIN_PA07B_ADC_AIN5 << 16) | MUX_PA07B_ADC_AIN5)
|
||||
#define PORT_PA07B_ADC_AIN5 (1ul << 7)
|
||||
#define PIN_PA14B_ADC_AIN6 14L /**< \brief ADC signal: AIN6 on PA14 mux B */
|
||||
#define MUX_PA14B_ADC_AIN6 1L
|
||||
#define PINMUX_PA14B_ADC_AIN6 ((PIN_PA14B_ADC_AIN6 << 16) | MUX_PA14B_ADC_AIN6)
|
||||
#define PORT_PA14B_ADC_AIN6 (1ul << 14)
|
||||
#define PIN_PA15B_ADC_AIN7 15L /**< \brief ADC signal: AIN7 on PA15 mux B */
|
||||
#define MUX_PA15B_ADC_AIN7 1L
|
||||
#define PINMUX_PA15B_ADC_AIN7 ((PIN_PA15B_ADC_AIN7 << 16) | MUX_PA15B_ADC_AIN7)
|
||||
#define PORT_PA15B_ADC_AIN7 (1ul << 15)
|
||||
#define PIN_PA10B_ADC_AIN8 10L /**< \brief ADC signal: AIN8 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN8 1L
|
||||
#define PINMUX_PA10B_ADC_AIN8 ((PIN_PA10B_ADC_AIN8 << 16) | MUX_PA10B_ADC_AIN8)
|
||||
#define PORT_PA10B_ADC_AIN8 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN9 11L /**< \brief ADC signal: AIN9 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN9 1L
|
||||
#define PINMUX_PA11B_ADC_AIN9 ((PIN_PA11B_ADC_AIN9 << 16) | MUX_PA11B_ADC_AIN9)
|
||||
#define PORT_PA11B_ADC_AIN9 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA14G_AC_CMP0 14L /**< \brief AC signal: CMP0 on PA14 mux G */
|
||||
#define MUX_PA14G_AC_CMP0 6L
|
||||
#define PINMUX_PA14G_AC_CMP0 ((PIN_PA14G_AC_CMP0 << 16) | MUX_PA14G_AC_CMP0)
|
||||
#define PORT_PA14G_AC_CMP0 (1ul << 14)
|
||||
#define PIN_PA10G_AC_CMP0 10L /**< \brief AC signal: CMP0 on PA10 mux G */
|
||||
#define MUX_PA10G_AC_CMP0 6L
|
||||
#define PINMUX_PA10G_AC_CMP0 ((PIN_PA10G_AC_CMP0 << 16) | MUX_PA10G_AC_CMP0)
|
||||
#define PORT_PA10G_AC_CMP0 (1ul << 10)
|
||||
#define PIN_PA15G_AC_CMP1 15L /**< \brief AC signal: CMP1 on PA15 mux G */
|
||||
#define MUX_PA15G_AC_CMP1 6L
|
||||
#define PINMUX_PA15G_AC_CMP1 ((PIN_PA15G_AC_CMP1 << 16) | MUX_PA15G_AC_CMP1)
|
||||
#define PORT_PA15G_AC_CMP1 (1ul << 15)
|
||||
#define PIN_PA11G_AC_CMP1 11L /**< \brief AC signal: CMP1 on PA11 mux G */
|
||||
#define MUX_PA11G_AC_CMP1 6L
|
||||
#define PINMUX_PA11G_AC_CMP1 ((PIN_PA11G_AC_CMP1 << 16) | MUX_PA11G_AC_CMP1)
|
||||
#define PORT_PA11G_AC_CMP1 (1ul << 11)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
|
||||
#endif /* _SAMD11D14AM_PIO_ */
|
|
@ -0,0 +1,533 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD11D14AS
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD11D14AS_PIO_
|
||||
#define _SAMD11D14AS_PIO_
|
||||
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for CORE peripheral ========== */
|
||||
#define PIN_PA30G_CORE_SWCLK 30L /**< \brief CORE signal: SWCLK on PA30 mux G */
|
||||
#define MUX_PA30G_CORE_SWCLK 6L
|
||||
#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
|
||||
#define PORT_PA30G_CORE_SWCLK (1ul << 30)
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA08H_GCLK_IO0 8L /**< \brief GCLK signal: IO0 on PA08 mux H */
|
||||
#define MUX_PA08H_GCLK_IO0 7L
|
||||
#define PINMUX_PA08H_GCLK_IO0 ((PIN_PA08H_GCLK_IO0 << 16) | MUX_PA08H_GCLK_IO0)
|
||||
#define PORT_PA08H_GCLK_IO0 (1ul << 8)
|
||||
#define PIN_PA24H_GCLK_IO0 24L /**< \brief GCLK signal: IO0 on PA24 mux H */
|
||||
#define MUX_PA24H_GCLK_IO0 7L
|
||||
#define PINMUX_PA24H_GCLK_IO0 ((PIN_PA24H_GCLK_IO0 << 16) | MUX_PA24H_GCLK_IO0)
|
||||
#define PORT_PA24H_GCLK_IO0 (1ul << 24)
|
||||
#define PIN_PA25H_GCLK_IO0 25L /**< \brief GCLK signal: IO0 on PA25 mux H */
|
||||
#define MUX_PA25H_GCLK_IO0 7L
|
||||
#define PINMUX_PA25H_GCLK_IO0 ((PIN_PA25H_GCLK_IO0 << 16) | MUX_PA25H_GCLK_IO0)
|
||||
#define PORT_PA25H_GCLK_IO0 (1ul << 25)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA31H_GCLK_IO0 31L /**< \brief GCLK signal: IO0 on PA31 mux H */
|
||||
#define MUX_PA31H_GCLK_IO0 7L
|
||||
#define PINMUX_PA31H_GCLK_IO0 ((PIN_PA31H_GCLK_IO0 << 16) | MUX_PA31H_GCLK_IO0)
|
||||
#define PORT_PA31H_GCLK_IO0 (1ul << 31)
|
||||
#define PIN_PA09H_GCLK_IO1 9L /**< \brief GCLK signal: IO1 on PA09 mux H */
|
||||
#define MUX_PA09H_GCLK_IO1 7L
|
||||
#define PINMUX_PA09H_GCLK_IO1 ((PIN_PA09H_GCLK_IO1 << 16) | MUX_PA09H_GCLK_IO1)
|
||||
#define PORT_PA09H_GCLK_IO1 (1ul << 9)
|
||||
#define PIN_PA22H_GCLK_IO1 22L /**< \brief GCLK signal: IO1 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO1 7L
|
||||
#define PINMUX_PA22H_GCLK_IO1 ((PIN_PA22H_GCLK_IO1 << 16) | MUX_PA22H_GCLK_IO1)
|
||||
#define PORT_PA22H_GCLK_IO1 (1ul << 22)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA23H_GCLK_IO2 23L /**< \brief GCLK signal: IO2 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO2 7L
|
||||
#define PINMUX_PA23H_GCLK_IO2 ((PIN_PA23H_GCLK_IO2 << 16) | MUX_PA23H_GCLK_IO2)
|
||||
#define PORT_PA23H_GCLK_IO2 (1ul << 23)
|
||||
#define PIN_PA14H_GCLK_IO4 14L /**< \brief GCLK signal: IO4 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO4 7L
|
||||
#define PINMUX_PA14H_GCLK_IO4 ((PIN_PA14H_GCLK_IO4 << 16) | MUX_PA14H_GCLK_IO4)
|
||||
#define PORT_PA14H_GCLK_IO4 (1ul << 14)
|
||||
#define PIN_PA15H_GCLK_IO5 15L /**< \brief GCLK signal: IO5 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO5 7L
|
||||
#define PINMUX_PA15H_GCLK_IO5 ((PIN_PA15H_GCLK_IO5 << 16) | MUX_PA15H_GCLK_IO5)
|
||||
#define PORT_PA15H_GCLK_IO5 (1ul << 15)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA15A_EIC_EXTINT1 15L /**< \brief EIC signal: EXTINT1 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT1 ((PIN_PA15A_EIC_EXTINT1 << 16) | MUX_PA15A_EIC_EXTINT1)
|
||||
#define PORT_PA15A_EIC_EXTINT1 (1ul << 15)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA30A_EIC_EXTINT2 30L /**< \brief EIC signal: EXTINT2 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT2 ((PIN_PA30A_EIC_EXTINT2 << 16) | MUX_PA30A_EIC_EXTINT2)
|
||||
#define PORT_PA30A_EIC_EXTINT2 (1ul << 30)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA31A_EIC_EXTINT3 31L /**< \brief EIC signal: EXTINT3 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT3 ((PIN_PA31A_EIC_EXTINT3 << 16) | MUX_PA31A_EIC_EXTINT3)
|
||||
#define PORT_PA31A_EIC_EXTINT3 (1ul << 31)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA24A_EIC_EXTINT4 24L /**< \brief EIC signal: EXTINT4 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT4 ((PIN_PA24A_EIC_EXTINT4 << 16) | MUX_PA24A_EIC_EXTINT4)
|
||||
#define PORT_PA24A_EIC_EXTINT4 (1ul << 24)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA25A_EIC_EXTINT5 25L /**< \brief EIC signal: EXTINT5 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT5 ((PIN_PA25A_EIC_EXTINT5 << 16) | MUX_PA25A_EIC_EXTINT5)
|
||||
#define PORT_PA25A_EIC_EXTINT5 (1ul << 25)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA08A_EIC_EXTINT6 8L /**< \brief EIC signal: EXTINT6 on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA08A_EIC_EXTINT6 ((PIN_PA08A_EIC_EXTINT6 << 16) | MUX_PA08A_EIC_EXTINT6)
|
||||
#define PORT_PA08A_EIC_EXTINT6 (1ul << 8)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA09A_EIC_EXTINT7 9L /**< \brief EIC signal: EXTINT7 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT7 ((PIN_PA09A_EIC_EXTINT7 << 16) | MUX_PA09A_EIC_EXTINT7)
|
||||
#define PORT_PA09A_EIC_EXTINT7 (1ul << 9)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA14A_EIC_NMI 14L /**< \brief EIC signal: NMI on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_NMI 0L
|
||||
#define PINMUX_PA14A_EIC_NMI ((PIN_PA14A_EIC_NMI << 16) | MUX_PA14A_EIC_NMI)
|
||||
#define PORT_PA14A_EIC_NMI (1ul << 14)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA14C_SERCOM0_PAD0 14L /**< \brief SERCOM0 signal: PAD0 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA14C_SERCOM0_PAD0 ((PIN_PA14C_SERCOM0_PAD0 << 16) | MUX_PA14C_SERCOM0_PAD0)
|
||||
#define PORT_PA14C_SERCOM0_PAD0 (1ul << 14)
|
||||
#define PIN_PA06C_SERCOM0_PAD0 6L /**< \brief SERCOM0 signal: PAD0 on PA06 mux C */
|
||||
#define MUX_PA06C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA06C_SERCOM0_PAD0 ((PIN_PA06C_SERCOM0_PAD0 << 16) | MUX_PA06C_SERCOM0_PAD0)
|
||||
#define PORT_PA06C_SERCOM0_PAD0 (1ul << 6)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA15C_SERCOM0_PAD1 15L /**< \brief SERCOM0 signal: PAD1 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA15C_SERCOM0_PAD1 ((PIN_PA15C_SERCOM0_PAD1 << 16) | MUX_PA15C_SERCOM0_PAD1)
|
||||
#define PORT_PA15C_SERCOM0_PAD1 (1ul << 15)
|
||||
#define PIN_PA07C_SERCOM0_PAD1 7L /**< \brief SERCOM0 signal: PAD1 on PA07 mux C */
|
||||
#define MUX_PA07C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA07C_SERCOM0_PAD1 ((PIN_PA07C_SERCOM0_PAD1 << 16) | MUX_PA07C_SERCOM0_PAD1)
|
||||
#define PORT_PA07C_SERCOM0_PAD1 (1ul << 7)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA08D_SERCOM0_PAD2 8L /**< \brief SERCOM0 signal: PAD2 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA08D_SERCOM0_PAD2 ((PIN_PA08D_SERCOM0_PAD2 << 16) | MUX_PA08D_SERCOM0_PAD2)
|
||||
#define PORT_PA08D_SERCOM0_PAD2 (1ul << 8)
|
||||
#define PIN_PA04C_SERCOM0_PAD2 4L /**< \brief SERCOM0 signal: PAD2 on PA04 mux C */
|
||||
#define MUX_PA04C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA04C_SERCOM0_PAD2 ((PIN_PA04C_SERCOM0_PAD2 << 16) | MUX_PA04C_SERCOM0_PAD2)
|
||||
#define PORT_PA04C_SERCOM0_PAD2 (1ul << 4)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA09D_SERCOM0_PAD3 9L /**< \brief SERCOM0 signal: PAD3 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA09D_SERCOM0_PAD3 ((PIN_PA09D_SERCOM0_PAD3 << 16) | MUX_PA09D_SERCOM0_PAD3)
|
||||
#define PORT_PA09D_SERCOM0_PAD3 (1ul << 9)
|
||||
#define PIN_PA05C_SERCOM0_PAD3 5L /**< \brief SERCOM0 signal: PAD3 on PA05 mux C */
|
||||
#define MUX_PA05C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA05C_SERCOM0_PAD3 ((PIN_PA05C_SERCOM0_PAD3 << 16) | MUX_PA05C_SERCOM0_PAD3)
|
||||
#define PORT_PA05C_SERCOM0_PAD3 (1ul << 5)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA22C_SERCOM1_PAD0 22L /**< \brief SERCOM1 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM1_PAD0 ((PIN_PA22C_SERCOM1_PAD0 << 16) | MUX_PA22C_SERCOM1_PAD0)
|
||||
#define PORT_PA22C_SERCOM1_PAD0 (1ul << 22)
|
||||
#define PIN_PA30C_SERCOM1_PAD0 30L /**< \brief SERCOM1 signal: PAD0 on PA30 mux C */
|
||||
#define MUX_PA30C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA30C_SERCOM1_PAD0 ((PIN_PA30C_SERCOM1_PAD0 << 16) | MUX_PA30C_SERCOM1_PAD0)
|
||||
#define PORT_PA30C_SERCOM1_PAD0 (1ul << 30)
|
||||
#define PIN_PA23C_SERCOM1_PAD1 23L /**< \brief SERCOM1 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM1_PAD1 ((PIN_PA23C_SERCOM1_PAD1 << 16) | MUX_PA23C_SERCOM1_PAD1)
|
||||
#define PORT_PA23C_SERCOM1_PAD1 (1ul << 23)
|
||||
#define PIN_PA31C_SERCOM1_PAD1 31L /**< \brief SERCOM1 signal: PAD1 on PA31 mux C */
|
||||
#define MUX_PA31C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA31C_SERCOM1_PAD1 ((PIN_PA31C_SERCOM1_PAD1 << 16) | MUX_PA31C_SERCOM1_PAD1)
|
||||
#define PORT_PA31C_SERCOM1_PAD1 (1ul << 31)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA16C_SERCOM1_PAD2 16L /**< \brief SERCOM1 signal: PAD2 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD2 ((PIN_PA16C_SERCOM1_PAD2 << 16) | MUX_PA16C_SERCOM1_PAD2)
|
||||
#define PORT_PA16C_SERCOM1_PAD2 (1ul << 16)
|
||||
#define PIN_PA24C_SERCOM1_PAD2 24L /**< \brief SERCOM1 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM1_PAD2 ((PIN_PA24C_SERCOM1_PAD2 << 16) | MUX_PA24C_SERCOM1_PAD2)
|
||||
#define PORT_PA24C_SERCOM1_PAD2 (1ul << 24)
|
||||
#define PIN_PA08C_SERCOM1_PAD2 8L /**< \brief SERCOM1 signal: PAD2 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA08C_SERCOM1_PAD2 ((PIN_PA08C_SERCOM1_PAD2 << 16) | MUX_PA08C_SERCOM1_PAD2)
|
||||
#define PORT_PA08C_SERCOM1_PAD2 (1ul << 8)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA25C_SERCOM1_PAD3 25L /**< \brief SERCOM1 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM1_PAD3 ((PIN_PA25C_SERCOM1_PAD3 << 16) | MUX_PA25C_SERCOM1_PAD3)
|
||||
#define PORT_PA25C_SERCOM1_PAD3 (1ul << 25)
|
||||
#define PIN_PA09C_SERCOM1_PAD3 9L /**< \brief SERCOM1 signal: PAD3 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA09C_SERCOM1_PAD3 ((PIN_PA09C_SERCOM1_PAD3 << 16) | MUX_PA09C_SERCOM1_PAD3)
|
||||
#define PORT_PA09C_SERCOM1_PAD3 (1ul << 9)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA14D_SERCOM2_PAD0 14L /**< \brief SERCOM2 signal: PAD0 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA14D_SERCOM2_PAD0 ((PIN_PA14D_SERCOM2_PAD0 << 16) | MUX_PA14D_SERCOM2_PAD0)
|
||||
#define PORT_PA14D_SERCOM2_PAD0 (1ul << 14)
|
||||
#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0)
|
||||
#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22)
|
||||
#define PIN_PA15D_SERCOM2_PAD1 15L /**< \brief SERCOM2 signal: PAD1 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA15D_SERCOM2_PAD1 ((PIN_PA15D_SERCOM2_PAD1 << 16) | MUX_PA15D_SERCOM2_PAD1)
|
||||
#define PORT_PA15D_SERCOM2_PAD1 (1ul << 15)
|
||||
#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1)
|
||||
#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23)
|
||||
#define PIN_PA16D_SERCOM2_PAD2 16L /**< \brief SERCOM2 signal: PAD2 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA16D_SERCOM2_PAD2 ((PIN_PA16D_SERCOM2_PAD2 << 16) | MUX_PA16D_SERCOM2_PAD2)
|
||||
#define PORT_PA16D_SERCOM2_PAD2 (1ul << 16)
|
||||
#define PIN_PA24D_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM2_PAD2 ((PIN_PA24D_SERCOM2_PAD2 << 16) | MUX_PA24D_SERCOM2_PAD2)
|
||||
#define PORT_PA24D_SERCOM2_PAD2 (1ul << 24)
|
||||
#define PIN_PA25D_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM2_PAD3 ((PIN_PA25D_SERCOM2_PAD3 << 16) | MUX_PA25D_SERCOM2_PAD3)
|
||||
#define PORT_PA25D_SERCOM2_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04F_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux F */
|
||||
#define MUX_PA04F_TCC0_WO0 5L
|
||||
#define PINMUX_PA04F_TCC0_WO0 ((PIN_PA04F_TCC0_WO0 << 16) | MUX_PA04F_TCC0_WO0)
|
||||
#define PORT_PA04F_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA14F_TCC0_WO0 14L /**< \brief TCC0 signal: WO0 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO0 5L
|
||||
#define PINMUX_PA14F_TCC0_WO0 ((PIN_PA14F_TCC0_WO0 << 16) | MUX_PA14F_TCC0_WO0)
|
||||
#define PORT_PA14F_TCC0_WO0 (1ul << 14)
|
||||
#define PIN_PA05F_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux F */
|
||||
#define MUX_PA05F_TCC0_WO1 5L
|
||||
#define PINMUX_PA05F_TCC0_WO1 ((PIN_PA05F_TCC0_WO1 << 16) | MUX_PA05F_TCC0_WO1)
|
||||
#define PORT_PA05F_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA15F_TCC0_WO1 15L /**< \brief TCC0 signal: WO1 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO1 5L
|
||||
#define PINMUX_PA15F_TCC0_WO1 ((PIN_PA15F_TCC0_WO1 << 16) | MUX_PA15F_TCC0_WO1)
|
||||
#define PORT_PA15F_TCC0_WO1 (1ul << 15)
|
||||
#define PIN_PA06F_TCC0_WO2 6L /**< \brief TCC0 signal: WO2 on PA06 mux F */
|
||||
#define MUX_PA06F_TCC0_WO2 5L
|
||||
#define PINMUX_PA06F_TCC0_WO2 ((PIN_PA06F_TCC0_WO2 << 16) | MUX_PA06F_TCC0_WO2)
|
||||
#define PORT_PA06F_TCC0_WO2 (1ul << 6)
|
||||
#define PIN_PA30F_TCC0_WO2 30L /**< \brief TCC0 signal: WO2 on PA30 mux F */
|
||||
#define MUX_PA30F_TCC0_WO2 5L
|
||||
#define PINMUX_PA30F_TCC0_WO2 ((PIN_PA30F_TCC0_WO2 << 16) | MUX_PA30F_TCC0_WO2)
|
||||
#define PORT_PA30F_TCC0_WO2 (1ul << 30)
|
||||
#define PIN_PA08E_TCC0_WO2 8L /**< \brief TCC0 signal: WO2 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO2 4L
|
||||
#define PINMUX_PA08E_TCC0_WO2 ((PIN_PA08E_TCC0_WO2 << 16) | MUX_PA08E_TCC0_WO2)
|
||||
#define PORT_PA08E_TCC0_WO2 (1ul << 8)
|
||||
#define PIN_PA24E_TCC0_WO2 24L /**< \brief TCC0 signal: WO2 on PA24 mux E */
|
||||
#define MUX_PA24E_TCC0_WO2 4L
|
||||
#define PINMUX_PA24E_TCC0_WO2 ((PIN_PA24E_TCC0_WO2 << 16) | MUX_PA24E_TCC0_WO2)
|
||||
#define PORT_PA24E_TCC0_WO2 (1ul << 24)
|
||||
#define PIN_PA07F_TCC0_WO3 7L /**< \brief TCC0 signal: WO3 on PA07 mux F */
|
||||
#define MUX_PA07F_TCC0_WO3 5L
|
||||
#define PINMUX_PA07F_TCC0_WO3 ((PIN_PA07F_TCC0_WO3 << 16) | MUX_PA07F_TCC0_WO3)
|
||||
#define PORT_PA07F_TCC0_WO3 (1ul << 7)
|
||||
#define PIN_PA31F_TCC0_WO3 31L /**< \brief TCC0 signal: WO3 on PA31 mux F */
|
||||
#define MUX_PA31F_TCC0_WO3 5L
|
||||
#define PINMUX_PA31F_TCC0_WO3 ((PIN_PA31F_TCC0_WO3 << 16) | MUX_PA31F_TCC0_WO3)
|
||||
#define PORT_PA31F_TCC0_WO3 (1ul << 31)
|
||||
#define PIN_PA09E_TCC0_WO3 9L /**< \brief TCC0 signal: WO3 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO3 4L
|
||||
#define PINMUX_PA09E_TCC0_WO3 ((PIN_PA09E_TCC0_WO3 << 16) | MUX_PA09E_TCC0_WO3)
|
||||
#define PORT_PA09E_TCC0_WO3 (1ul << 9)
|
||||
#define PIN_PA25E_TCC0_WO3 25L /**< \brief TCC0 signal: WO3 on PA25 mux E */
|
||||
#define MUX_PA25E_TCC0_WO3 4L
|
||||
#define PINMUX_PA25E_TCC0_WO3 ((PIN_PA25E_TCC0_WO3 << 16) | MUX_PA25E_TCC0_WO3)
|
||||
#define PORT_PA25E_TCC0_WO3 (1ul << 25)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA24F_TCC0_WO4 24L /**< \brief TCC0 signal: WO4 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC0_WO4 5L
|
||||
#define PINMUX_PA24F_TCC0_WO4 ((PIN_PA24F_TCC0_WO4 << 16) | MUX_PA24F_TCC0_WO4)
|
||||
#define PORT_PA24F_TCC0_WO4 (1ul << 24)
|
||||
#define PIN_PA08F_TCC0_WO4 8L /**< \brief TCC0 signal: WO4 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC0_WO4 5L
|
||||
#define PINMUX_PA08F_TCC0_WO4 ((PIN_PA08F_TCC0_WO4 << 16) | MUX_PA08F_TCC0_WO4)
|
||||
#define PORT_PA08F_TCC0_WO4 (1ul << 8)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA25F_TCC0_WO5 25L /**< \brief TCC0 signal: WO5 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC0_WO5 5L
|
||||
#define PINMUX_PA25F_TCC0_WO5 ((PIN_PA25F_TCC0_WO5 << 16) | MUX_PA25F_TCC0_WO5)
|
||||
#define PORT_PA25F_TCC0_WO5 (1ul << 25)
|
||||
#define PIN_PA09F_TCC0_WO5 9L /**< \brief TCC0 signal: WO5 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC0_WO5 5L
|
||||
#define PINMUX_PA09F_TCC0_WO5 ((PIN_PA09F_TCC0_WO5 << 16) | MUX_PA09F_TCC0_WO5)
|
||||
#define PORT_PA09F_TCC0_WO5 (1ul << 9)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
/* ========== PORT definition for TC1 peripheral ========== */
|
||||
#define PIN_PA04E_TC1_WO0 4L /**< \brief TC1 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TC1_WO0 4L
|
||||
#define PINMUX_PA04E_TC1_WO0 ((PIN_PA04E_TC1_WO0 << 16) | MUX_PA04E_TC1_WO0)
|
||||
#define PORT_PA04E_TC1_WO0 (1ul << 4)
|
||||
#define PIN_PA14E_TC1_WO0 14L /**< \brief TC1 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC1_WO0 4L
|
||||
#define PINMUX_PA14E_TC1_WO0 ((PIN_PA14E_TC1_WO0 << 16) | MUX_PA14E_TC1_WO0)
|
||||
#define PORT_PA14E_TC1_WO0 (1ul << 14)
|
||||
#define PIN_PA16E_TC1_WO0 16L /**< \brief TC1 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TC1_WO0 4L
|
||||
#define PINMUX_PA16E_TC1_WO0 ((PIN_PA16E_TC1_WO0 << 16) | MUX_PA16E_TC1_WO0)
|
||||
#define PORT_PA16E_TC1_WO0 (1ul << 16)
|
||||
#define PIN_PA22E_TC1_WO0 22L /**< \brief TC1 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC1_WO0 4L
|
||||
#define PINMUX_PA22E_TC1_WO0 ((PIN_PA22E_TC1_WO0 << 16) | MUX_PA22E_TC1_WO0)
|
||||
#define PORT_PA22E_TC1_WO0 (1ul << 22)
|
||||
#define PIN_PA05E_TC1_WO1 5L /**< \brief TC1 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TC1_WO1 4L
|
||||
#define PINMUX_PA05E_TC1_WO1 ((PIN_PA05E_TC1_WO1 << 16) | MUX_PA05E_TC1_WO1)
|
||||
#define PORT_PA05E_TC1_WO1 (1ul << 5)
|
||||
#define PIN_PA15E_TC1_WO1 15L /**< \brief TC1 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC1_WO1 4L
|
||||
#define PINMUX_PA15E_TC1_WO1 ((PIN_PA15E_TC1_WO1 << 16) | MUX_PA15E_TC1_WO1)
|
||||
#define PORT_PA15E_TC1_WO1 (1ul << 15)
|
||||
#define PIN_PA23E_TC1_WO1 23L /**< \brief TC1 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC1_WO1 4L
|
||||
#define PINMUX_PA23E_TC1_WO1 ((PIN_PA23E_TC1_WO1 << 16) | MUX_PA23E_TC1_WO1)
|
||||
#define PORT_PA23E_TC1_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC2 peripheral ========== */
|
||||
#define PIN_PA06E_TC2_WO0 6L /**< \brief TC2 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TC2_WO0 4L
|
||||
#define PINMUX_PA06E_TC2_WO0 ((PIN_PA06E_TC2_WO0 << 16) | MUX_PA06E_TC2_WO0)
|
||||
#define PORT_PA06E_TC2_WO0 (1ul << 6)
|
||||
#define PIN_PA30E_TC2_WO0 30L /**< \brief TC2 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TC2_WO0 4L
|
||||
#define PINMUX_PA30E_TC2_WO0 ((PIN_PA30E_TC2_WO0 << 16) | MUX_PA30E_TC2_WO0)
|
||||
#define PORT_PA30E_TC2_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TC2_WO1 7L /**< \brief TC2 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TC2_WO1 4L
|
||||
#define PINMUX_PA07E_TC2_WO1 ((PIN_PA07E_TC2_WO1 << 16) | MUX_PA07E_TC2_WO1)
|
||||
#define PORT_PA07E_TC2_WO1 (1ul << 7)
|
||||
#define PIN_PA31E_TC2_WO1 31L /**< \brief TC2 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TC2_WO1 4L
|
||||
#define PINMUX_PA31E_TC2_WO1 ((PIN_PA31E_TC2_WO1 << 16) | MUX_PA31E_TC2_WO1)
|
||||
#define PORT_PA31E_TC2_WO1 (1ul << 31)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN2 4L /**< \brief ADC signal: AIN2 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN2 1L
|
||||
#define PINMUX_PA04B_ADC_AIN2 ((PIN_PA04B_ADC_AIN2 << 16) | MUX_PA04B_ADC_AIN2)
|
||||
#define PORT_PA04B_ADC_AIN2 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN3 5L /**< \brief ADC signal: AIN3 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN3 1L
|
||||
#define PINMUX_PA05B_ADC_AIN3 ((PIN_PA05B_ADC_AIN3 << 16) | MUX_PA05B_ADC_AIN3)
|
||||
#define PORT_PA05B_ADC_AIN3 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN4 6L /**< \brief ADC signal: AIN4 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN4 1L
|
||||
#define PINMUX_PA06B_ADC_AIN4 ((PIN_PA06B_ADC_AIN4 << 16) | MUX_PA06B_ADC_AIN4)
|
||||
#define PORT_PA06B_ADC_AIN4 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN5 7L /**< \brief ADC signal: AIN5 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN5 1L
|
||||
#define PINMUX_PA07B_ADC_AIN5 ((PIN_PA07B_ADC_AIN5 << 16) | MUX_PA07B_ADC_AIN5)
|
||||
#define PORT_PA07B_ADC_AIN5 (1ul << 7)
|
||||
#define PIN_PA14B_ADC_AIN6 14L /**< \brief ADC signal: AIN6 on PA14 mux B */
|
||||
#define MUX_PA14B_ADC_AIN6 1L
|
||||
#define PINMUX_PA14B_ADC_AIN6 ((PIN_PA14B_ADC_AIN6 << 16) | MUX_PA14B_ADC_AIN6)
|
||||
#define PORT_PA14B_ADC_AIN6 (1ul << 14)
|
||||
#define PIN_PA15B_ADC_AIN7 15L /**< \brief ADC signal: AIN7 on PA15 mux B */
|
||||
#define MUX_PA15B_ADC_AIN7 1L
|
||||
#define PINMUX_PA15B_ADC_AIN7 ((PIN_PA15B_ADC_AIN7 << 16) | MUX_PA15B_ADC_AIN7)
|
||||
#define PORT_PA15B_ADC_AIN7 (1ul << 15)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA14G_AC_CMP0 14L /**< \brief AC signal: CMP0 on PA14 mux G */
|
||||
#define MUX_PA14G_AC_CMP0 6L
|
||||
#define PINMUX_PA14G_AC_CMP0 ((PIN_PA14G_AC_CMP0 << 16) | MUX_PA14G_AC_CMP0)
|
||||
#define PORT_PA14G_AC_CMP0 (1ul << 14)
|
||||
#define PIN_PA15G_AC_CMP1 15L /**< \brief AC signal: CMP1 on PA15 mux G */
|
||||
#define MUX_PA15G_AC_CMP1 6L
|
||||
#define PINMUX_PA15G_AC_CMP1 ((PIN_PA15G_AC_CMP1 << 16) | MUX_PA15G_AC_CMP1)
|
||||
#define PORT_PA15G_AC_CMP1 (1ul << 15)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
|
||||
#endif /* _SAMD11D14AS_PIO_ */
|
|
@ -0,0 +1,533 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD11D14AU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD11D14AU_PIO_
|
||||
#define _SAMD11D14AU_PIO_
|
||||
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for CORE peripheral ========== */
|
||||
#define PIN_PA30G_CORE_SWCLK 30L /**< \brief CORE signal: SWCLK on PA30 mux G */
|
||||
#define MUX_PA30G_CORE_SWCLK 6L
|
||||
#define PINMUX_PA30G_CORE_SWCLK ((PIN_PA30G_CORE_SWCLK << 16) | MUX_PA30G_CORE_SWCLK)
|
||||
#define PORT_PA30G_CORE_SWCLK (1ul << 30)
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA08H_GCLK_IO0 8L /**< \brief GCLK signal: IO0 on PA08 mux H */
|
||||
#define MUX_PA08H_GCLK_IO0 7L
|
||||
#define PINMUX_PA08H_GCLK_IO0 ((PIN_PA08H_GCLK_IO0 << 16) | MUX_PA08H_GCLK_IO0)
|
||||
#define PORT_PA08H_GCLK_IO0 (1ul << 8)
|
||||
#define PIN_PA24H_GCLK_IO0 24L /**< \brief GCLK signal: IO0 on PA24 mux H */
|
||||
#define MUX_PA24H_GCLK_IO0 7L
|
||||
#define PINMUX_PA24H_GCLK_IO0 ((PIN_PA24H_GCLK_IO0 << 16) | MUX_PA24H_GCLK_IO0)
|
||||
#define PORT_PA24H_GCLK_IO0 (1ul << 24)
|
||||
#define PIN_PA25H_GCLK_IO0 25L /**< \brief GCLK signal: IO0 on PA25 mux H */
|
||||
#define MUX_PA25H_GCLK_IO0 7L
|
||||
#define PINMUX_PA25H_GCLK_IO0 ((PIN_PA25H_GCLK_IO0 << 16) | MUX_PA25H_GCLK_IO0)
|
||||
#define PORT_PA25H_GCLK_IO0 (1ul << 25)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA31H_GCLK_IO0 31L /**< \brief GCLK signal: IO0 on PA31 mux H */
|
||||
#define MUX_PA31H_GCLK_IO0 7L
|
||||
#define PINMUX_PA31H_GCLK_IO0 ((PIN_PA31H_GCLK_IO0 << 16) | MUX_PA31H_GCLK_IO0)
|
||||
#define PORT_PA31H_GCLK_IO0 (1ul << 31)
|
||||
#define PIN_PA09H_GCLK_IO1 9L /**< \brief GCLK signal: IO1 on PA09 mux H */
|
||||
#define MUX_PA09H_GCLK_IO1 7L
|
||||
#define PINMUX_PA09H_GCLK_IO1 ((PIN_PA09H_GCLK_IO1 << 16) | MUX_PA09H_GCLK_IO1)
|
||||
#define PORT_PA09H_GCLK_IO1 (1ul << 9)
|
||||
#define PIN_PA22H_GCLK_IO1 22L /**< \brief GCLK signal: IO1 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO1 7L
|
||||
#define PINMUX_PA22H_GCLK_IO1 ((PIN_PA22H_GCLK_IO1 << 16) | MUX_PA22H_GCLK_IO1)
|
||||
#define PORT_PA22H_GCLK_IO1 (1ul << 22)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA23H_GCLK_IO2 23L /**< \brief GCLK signal: IO2 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO2 7L
|
||||
#define PINMUX_PA23H_GCLK_IO2 ((PIN_PA23H_GCLK_IO2 << 16) | MUX_PA23H_GCLK_IO2)
|
||||
#define PORT_PA23H_GCLK_IO2 (1ul << 23)
|
||||
#define PIN_PA14H_GCLK_IO4 14L /**< \brief GCLK signal: IO4 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO4 7L
|
||||
#define PINMUX_PA14H_GCLK_IO4 ((PIN_PA14H_GCLK_IO4 << 16) | MUX_PA14H_GCLK_IO4)
|
||||
#define PORT_PA14H_GCLK_IO4 (1ul << 14)
|
||||
#define PIN_PA15H_GCLK_IO5 15L /**< \brief GCLK signal: IO5 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO5 7L
|
||||
#define PINMUX_PA15H_GCLK_IO5 ((PIN_PA15H_GCLK_IO5 << 16) | MUX_PA15H_GCLK_IO5)
|
||||
#define PORT_PA15H_GCLK_IO5 (1ul << 15)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA15A_EIC_EXTINT1 15L /**< \brief EIC signal: EXTINT1 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT1 ((PIN_PA15A_EIC_EXTINT1 << 16) | MUX_PA15A_EIC_EXTINT1)
|
||||
#define PORT_PA15A_EIC_EXTINT1 (1ul << 15)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA30A_EIC_EXTINT2 30L /**< \brief EIC signal: EXTINT2 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT2 ((PIN_PA30A_EIC_EXTINT2 << 16) | MUX_PA30A_EIC_EXTINT2)
|
||||
#define PORT_PA30A_EIC_EXTINT2 (1ul << 30)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA31A_EIC_EXTINT3 31L /**< \brief EIC signal: EXTINT3 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT3 ((PIN_PA31A_EIC_EXTINT3 << 16) | MUX_PA31A_EIC_EXTINT3)
|
||||
#define PORT_PA31A_EIC_EXTINT3 (1ul << 31)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA24A_EIC_EXTINT4 24L /**< \brief EIC signal: EXTINT4 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT4 ((PIN_PA24A_EIC_EXTINT4 << 16) | MUX_PA24A_EIC_EXTINT4)
|
||||
#define PORT_PA24A_EIC_EXTINT4 (1ul << 24)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA25A_EIC_EXTINT5 25L /**< \brief EIC signal: EXTINT5 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT5 ((PIN_PA25A_EIC_EXTINT5 << 16) | MUX_PA25A_EIC_EXTINT5)
|
||||
#define PORT_PA25A_EIC_EXTINT5 (1ul << 25)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA08A_EIC_EXTINT6 8L /**< \brief EIC signal: EXTINT6 on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA08A_EIC_EXTINT6 ((PIN_PA08A_EIC_EXTINT6 << 16) | MUX_PA08A_EIC_EXTINT6)
|
||||
#define PORT_PA08A_EIC_EXTINT6 (1ul << 8)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA09A_EIC_EXTINT7 9L /**< \brief EIC signal: EXTINT7 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT7 ((PIN_PA09A_EIC_EXTINT7 << 16) | MUX_PA09A_EIC_EXTINT7)
|
||||
#define PORT_PA09A_EIC_EXTINT7 (1ul << 9)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA14A_EIC_NMI 14L /**< \brief EIC signal: NMI on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_NMI 0L
|
||||
#define PINMUX_PA14A_EIC_NMI ((PIN_PA14A_EIC_NMI << 16) | MUX_PA14A_EIC_NMI)
|
||||
#define PORT_PA14A_EIC_NMI (1ul << 14)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA14C_SERCOM0_PAD0 14L /**< \brief SERCOM0 signal: PAD0 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA14C_SERCOM0_PAD0 ((PIN_PA14C_SERCOM0_PAD0 << 16) | MUX_PA14C_SERCOM0_PAD0)
|
||||
#define PORT_PA14C_SERCOM0_PAD0 (1ul << 14)
|
||||
#define PIN_PA06C_SERCOM0_PAD0 6L /**< \brief SERCOM0 signal: PAD0 on PA06 mux C */
|
||||
#define MUX_PA06C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA06C_SERCOM0_PAD0 ((PIN_PA06C_SERCOM0_PAD0 << 16) | MUX_PA06C_SERCOM0_PAD0)
|
||||
#define PORT_PA06C_SERCOM0_PAD0 (1ul << 6)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA15C_SERCOM0_PAD1 15L /**< \brief SERCOM0 signal: PAD1 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA15C_SERCOM0_PAD1 ((PIN_PA15C_SERCOM0_PAD1 << 16) | MUX_PA15C_SERCOM0_PAD1)
|
||||
#define PORT_PA15C_SERCOM0_PAD1 (1ul << 15)
|
||||
#define PIN_PA07C_SERCOM0_PAD1 7L /**< \brief SERCOM0 signal: PAD1 on PA07 mux C */
|
||||
#define MUX_PA07C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA07C_SERCOM0_PAD1 ((PIN_PA07C_SERCOM0_PAD1 << 16) | MUX_PA07C_SERCOM0_PAD1)
|
||||
#define PORT_PA07C_SERCOM0_PAD1 (1ul << 7)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA08D_SERCOM0_PAD2 8L /**< \brief SERCOM0 signal: PAD2 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA08D_SERCOM0_PAD2 ((PIN_PA08D_SERCOM0_PAD2 << 16) | MUX_PA08D_SERCOM0_PAD2)
|
||||
#define PORT_PA08D_SERCOM0_PAD2 (1ul << 8)
|
||||
#define PIN_PA04C_SERCOM0_PAD2 4L /**< \brief SERCOM0 signal: PAD2 on PA04 mux C */
|
||||
#define MUX_PA04C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA04C_SERCOM0_PAD2 ((PIN_PA04C_SERCOM0_PAD2 << 16) | MUX_PA04C_SERCOM0_PAD2)
|
||||
#define PORT_PA04C_SERCOM0_PAD2 (1ul << 4)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA09D_SERCOM0_PAD3 9L /**< \brief SERCOM0 signal: PAD3 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA09D_SERCOM0_PAD3 ((PIN_PA09D_SERCOM0_PAD3 << 16) | MUX_PA09D_SERCOM0_PAD3)
|
||||
#define PORT_PA09D_SERCOM0_PAD3 (1ul << 9)
|
||||
#define PIN_PA05C_SERCOM0_PAD3 5L /**< \brief SERCOM0 signal: PAD3 on PA05 mux C */
|
||||
#define MUX_PA05C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA05C_SERCOM0_PAD3 ((PIN_PA05C_SERCOM0_PAD3 << 16) | MUX_PA05C_SERCOM0_PAD3)
|
||||
#define PORT_PA05C_SERCOM0_PAD3 (1ul << 5)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA22C_SERCOM1_PAD0 22L /**< \brief SERCOM1 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM1_PAD0 ((PIN_PA22C_SERCOM1_PAD0 << 16) | MUX_PA22C_SERCOM1_PAD0)
|
||||
#define PORT_PA22C_SERCOM1_PAD0 (1ul << 22)
|
||||
#define PIN_PA30C_SERCOM1_PAD0 30L /**< \brief SERCOM1 signal: PAD0 on PA30 mux C */
|
||||
#define MUX_PA30C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA30C_SERCOM1_PAD0 ((PIN_PA30C_SERCOM1_PAD0 << 16) | MUX_PA30C_SERCOM1_PAD0)
|
||||
#define PORT_PA30C_SERCOM1_PAD0 (1ul << 30)
|
||||
#define PIN_PA23C_SERCOM1_PAD1 23L /**< \brief SERCOM1 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM1_PAD1 ((PIN_PA23C_SERCOM1_PAD1 << 16) | MUX_PA23C_SERCOM1_PAD1)
|
||||
#define PORT_PA23C_SERCOM1_PAD1 (1ul << 23)
|
||||
#define PIN_PA31C_SERCOM1_PAD1 31L /**< \brief SERCOM1 signal: PAD1 on PA31 mux C */
|
||||
#define MUX_PA31C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA31C_SERCOM1_PAD1 ((PIN_PA31C_SERCOM1_PAD1 << 16) | MUX_PA31C_SERCOM1_PAD1)
|
||||
#define PORT_PA31C_SERCOM1_PAD1 (1ul << 31)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA16C_SERCOM1_PAD2 16L /**< \brief SERCOM1 signal: PAD2 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD2 ((PIN_PA16C_SERCOM1_PAD2 << 16) | MUX_PA16C_SERCOM1_PAD2)
|
||||
#define PORT_PA16C_SERCOM1_PAD2 (1ul << 16)
|
||||
#define PIN_PA24C_SERCOM1_PAD2 24L /**< \brief SERCOM1 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM1_PAD2 ((PIN_PA24C_SERCOM1_PAD2 << 16) | MUX_PA24C_SERCOM1_PAD2)
|
||||
#define PORT_PA24C_SERCOM1_PAD2 (1ul << 24)
|
||||
#define PIN_PA08C_SERCOM1_PAD2 8L /**< \brief SERCOM1 signal: PAD2 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA08C_SERCOM1_PAD2 ((PIN_PA08C_SERCOM1_PAD2 << 16) | MUX_PA08C_SERCOM1_PAD2)
|
||||
#define PORT_PA08C_SERCOM1_PAD2 (1ul << 8)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA25C_SERCOM1_PAD3 25L /**< \brief SERCOM1 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM1_PAD3 ((PIN_PA25C_SERCOM1_PAD3 << 16) | MUX_PA25C_SERCOM1_PAD3)
|
||||
#define PORT_PA25C_SERCOM1_PAD3 (1ul << 25)
|
||||
#define PIN_PA09C_SERCOM1_PAD3 9L /**< \brief SERCOM1 signal: PAD3 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA09C_SERCOM1_PAD3 ((PIN_PA09C_SERCOM1_PAD3 << 16) | MUX_PA09C_SERCOM1_PAD3)
|
||||
#define PORT_PA09C_SERCOM1_PAD3 (1ul << 9)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA14D_SERCOM2_PAD0 14L /**< \brief SERCOM2 signal: PAD0 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA14D_SERCOM2_PAD0 ((PIN_PA14D_SERCOM2_PAD0 << 16) | MUX_PA14D_SERCOM2_PAD0)
|
||||
#define PORT_PA14D_SERCOM2_PAD0 (1ul << 14)
|
||||
#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0)
|
||||
#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22)
|
||||
#define PIN_PA15D_SERCOM2_PAD1 15L /**< \brief SERCOM2 signal: PAD1 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA15D_SERCOM2_PAD1 ((PIN_PA15D_SERCOM2_PAD1 << 16) | MUX_PA15D_SERCOM2_PAD1)
|
||||
#define PORT_PA15D_SERCOM2_PAD1 (1ul << 15)
|
||||
#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1)
|
||||
#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23)
|
||||
#define PIN_PA16D_SERCOM2_PAD2 16L /**< \brief SERCOM2 signal: PAD2 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA16D_SERCOM2_PAD2 ((PIN_PA16D_SERCOM2_PAD2 << 16) | MUX_PA16D_SERCOM2_PAD2)
|
||||
#define PORT_PA16D_SERCOM2_PAD2 (1ul << 16)
|
||||
#define PIN_PA24D_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM2_PAD2 ((PIN_PA24D_SERCOM2_PAD2 << 16) | MUX_PA24D_SERCOM2_PAD2)
|
||||
#define PORT_PA24D_SERCOM2_PAD2 (1ul << 24)
|
||||
#define PIN_PA25D_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM2_PAD3 ((PIN_PA25D_SERCOM2_PAD3 << 16) | MUX_PA25D_SERCOM2_PAD3)
|
||||
#define PORT_PA25D_SERCOM2_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04F_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux F */
|
||||
#define MUX_PA04F_TCC0_WO0 5L
|
||||
#define PINMUX_PA04F_TCC0_WO0 ((PIN_PA04F_TCC0_WO0 << 16) | MUX_PA04F_TCC0_WO0)
|
||||
#define PORT_PA04F_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA14F_TCC0_WO0 14L /**< \brief TCC0 signal: WO0 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO0 5L
|
||||
#define PINMUX_PA14F_TCC0_WO0 ((PIN_PA14F_TCC0_WO0 << 16) | MUX_PA14F_TCC0_WO0)
|
||||
#define PORT_PA14F_TCC0_WO0 (1ul << 14)
|
||||
#define PIN_PA05F_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux F */
|
||||
#define MUX_PA05F_TCC0_WO1 5L
|
||||
#define PINMUX_PA05F_TCC0_WO1 ((PIN_PA05F_TCC0_WO1 << 16) | MUX_PA05F_TCC0_WO1)
|
||||
#define PORT_PA05F_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA15F_TCC0_WO1 15L /**< \brief TCC0 signal: WO1 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO1 5L
|
||||
#define PINMUX_PA15F_TCC0_WO1 ((PIN_PA15F_TCC0_WO1 << 16) | MUX_PA15F_TCC0_WO1)
|
||||
#define PORT_PA15F_TCC0_WO1 (1ul << 15)
|
||||
#define PIN_PA06F_TCC0_WO2 6L /**< \brief TCC0 signal: WO2 on PA06 mux F */
|
||||
#define MUX_PA06F_TCC0_WO2 5L
|
||||
#define PINMUX_PA06F_TCC0_WO2 ((PIN_PA06F_TCC0_WO2 << 16) | MUX_PA06F_TCC0_WO2)
|
||||
#define PORT_PA06F_TCC0_WO2 (1ul << 6)
|
||||
#define PIN_PA30F_TCC0_WO2 30L /**< \brief TCC0 signal: WO2 on PA30 mux F */
|
||||
#define MUX_PA30F_TCC0_WO2 5L
|
||||
#define PINMUX_PA30F_TCC0_WO2 ((PIN_PA30F_TCC0_WO2 << 16) | MUX_PA30F_TCC0_WO2)
|
||||
#define PORT_PA30F_TCC0_WO2 (1ul << 30)
|
||||
#define PIN_PA08E_TCC0_WO2 8L /**< \brief TCC0 signal: WO2 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO2 4L
|
||||
#define PINMUX_PA08E_TCC0_WO2 ((PIN_PA08E_TCC0_WO2 << 16) | MUX_PA08E_TCC0_WO2)
|
||||
#define PORT_PA08E_TCC0_WO2 (1ul << 8)
|
||||
#define PIN_PA24E_TCC0_WO2 24L /**< \brief TCC0 signal: WO2 on PA24 mux E */
|
||||
#define MUX_PA24E_TCC0_WO2 4L
|
||||
#define PINMUX_PA24E_TCC0_WO2 ((PIN_PA24E_TCC0_WO2 << 16) | MUX_PA24E_TCC0_WO2)
|
||||
#define PORT_PA24E_TCC0_WO2 (1ul << 24)
|
||||
#define PIN_PA07F_TCC0_WO3 7L /**< \brief TCC0 signal: WO3 on PA07 mux F */
|
||||
#define MUX_PA07F_TCC0_WO3 5L
|
||||
#define PINMUX_PA07F_TCC0_WO3 ((PIN_PA07F_TCC0_WO3 << 16) | MUX_PA07F_TCC0_WO3)
|
||||
#define PORT_PA07F_TCC0_WO3 (1ul << 7)
|
||||
#define PIN_PA31F_TCC0_WO3 31L /**< \brief TCC0 signal: WO3 on PA31 mux F */
|
||||
#define MUX_PA31F_TCC0_WO3 5L
|
||||
#define PINMUX_PA31F_TCC0_WO3 ((PIN_PA31F_TCC0_WO3 << 16) | MUX_PA31F_TCC0_WO3)
|
||||
#define PORT_PA31F_TCC0_WO3 (1ul << 31)
|
||||
#define PIN_PA09E_TCC0_WO3 9L /**< \brief TCC0 signal: WO3 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO3 4L
|
||||
#define PINMUX_PA09E_TCC0_WO3 ((PIN_PA09E_TCC0_WO3 << 16) | MUX_PA09E_TCC0_WO3)
|
||||
#define PORT_PA09E_TCC0_WO3 (1ul << 9)
|
||||
#define PIN_PA25E_TCC0_WO3 25L /**< \brief TCC0 signal: WO3 on PA25 mux E */
|
||||
#define MUX_PA25E_TCC0_WO3 4L
|
||||
#define PINMUX_PA25E_TCC0_WO3 ((PIN_PA25E_TCC0_WO3 << 16) | MUX_PA25E_TCC0_WO3)
|
||||
#define PORT_PA25E_TCC0_WO3 (1ul << 25)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA24F_TCC0_WO4 24L /**< \brief TCC0 signal: WO4 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC0_WO4 5L
|
||||
#define PINMUX_PA24F_TCC0_WO4 ((PIN_PA24F_TCC0_WO4 << 16) | MUX_PA24F_TCC0_WO4)
|
||||
#define PORT_PA24F_TCC0_WO4 (1ul << 24)
|
||||
#define PIN_PA08F_TCC0_WO4 8L /**< \brief TCC0 signal: WO4 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC0_WO4 5L
|
||||
#define PINMUX_PA08F_TCC0_WO4 ((PIN_PA08F_TCC0_WO4 << 16) | MUX_PA08F_TCC0_WO4)
|
||||
#define PORT_PA08F_TCC0_WO4 (1ul << 8)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA25F_TCC0_WO5 25L /**< \brief TCC0 signal: WO5 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC0_WO5 5L
|
||||
#define PINMUX_PA25F_TCC0_WO5 ((PIN_PA25F_TCC0_WO5 << 16) | MUX_PA25F_TCC0_WO5)
|
||||
#define PORT_PA25F_TCC0_WO5 (1ul << 25)
|
||||
#define PIN_PA09F_TCC0_WO5 9L /**< \brief TCC0 signal: WO5 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC0_WO5 5L
|
||||
#define PINMUX_PA09F_TCC0_WO5 ((PIN_PA09F_TCC0_WO5 << 16) | MUX_PA09F_TCC0_WO5)
|
||||
#define PORT_PA09F_TCC0_WO5 (1ul << 9)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
/* ========== PORT definition for TC1 peripheral ========== */
|
||||
#define PIN_PA04E_TC1_WO0 4L /**< \brief TC1 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TC1_WO0 4L
|
||||
#define PINMUX_PA04E_TC1_WO0 ((PIN_PA04E_TC1_WO0 << 16) | MUX_PA04E_TC1_WO0)
|
||||
#define PORT_PA04E_TC1_WO0 (1ul << 4)
|
||||
#define PIN_PA14E_TC1_WO0 14L /**< \brief TC1 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC1_WO0 4L
|
||||
#define PINMUX_PA14E_TC1_WO0 ((PIN_PA14E_TC1_WO0 << 16) | MUX_PA14E_TC1_WO0)
|
||||
#define PORT_PA14E_TC1_WO0 (1ul << 14)
|
||||
#define PIN_PA16E_TC1_WO0 16L /**< \brief TC1 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TC1_WO0 4L
|
||||
#define PINMUX_PA16E_TC1_WO0 ((PIN_PA16E_TC1_WO0 << 16) | MUX_PA16E_TC1_WO0)
|
||||
#define PORT_PA16E_TC1_WO0 (1ul << 16)
|
||||
#define PIN_PA22E_TC1_WO0 22L /**< \brief TC1 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC1_WO0 4L
|
||||
#define PINMUX_PA22E_TC1_WO0 ((PIN_PA22E_TC1_WO0 << 16) | MUX_PA22E_TC1_WO0)
|
||||
#define PORT_PA22E_TC1_WO0 (1ul << 22)
|
||||
#define PIN_PA05E_TC1_WO1 5L /**< \brief TC1 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TC1_WO1 4L
|
||||
#define PINMUX_PA05E_TC1_WO1 ((PIN_PA05E_TC1_WO1 << 16) | MUX_PA05E_TC1_WO1)
|
||||
#define PORT_PA05E_TC1_WO1 (1ul << 5)
|
||||
#define PIN_PA15E_TC1_WO1 15L /**< \brief TC1 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC1_WO1 4L
|
||||
#define PINMUX_PA15E_TC1_WO1 ((PIN_PA15E_TC1_WO1 << 16) | MUX_PA15E_TC1_WO1)
|
||||
#define PORT_PA15E_TC1_WO1 (1ul << 15)
|
||||
#define PIN_PA23E_TC1_WO1 23L /**< \brief TC1 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC1_WO1 4L
|
||||
#define PINMUX_PA23E_TC1_WO1 ((PIN_PA23E_TC1_WO1 << 16) | MUX_PA23E_TC1_WO1)
|
||||
#define PORT_PA23E_TC1_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC2 peripheral ========== */
|
||||
#define PIN_PA06E_TC2_WO0 6L /**< \brief TC2 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TC2_WO0 4L
|
||||
#define PINMUX_PA06E_TC2_WO0 ((PIN_PA06E_TC2_WO0 << 16) | MUX_PA06E_TC2_WO0)
|
||||
#define PORT_PA06E_TC2_WO0 (1ul << 6)
|
||||
#define PIN_PA30E_TC2_WO0 30L /**< \brief TC2 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TC2_WO0 4L
|
||||
#define PINMUX_PA30E_TC2_WO0 ((PIN_PA30E_TC2_WO0 << 16) | MUX_PA30E_TC2_WO0)
|
||||
#define PORT_PA30E_TC2_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TC2_WO1 7L /**< \brief TC2 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TC2_WO1 4L
|
||||
#define PINMUX_PA07E_TC2_WO1 ((PIN_PA07E_TC2_WO1 << 16) | MUX_PA07E_TC2_WO1)
|
||||
#define PORT_PA07E_TC2_WO1 (1ul << 7)
|
||||
#define PIN_PA31E_TC2_WO1 31L /**< \brief TC2 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TC2_WO1 4L
|
||||
#define PINMUX_PA31E_TC2_WO1 ((PIN_PA31E_TC2_WO1 << 16) | MUX_PA31E_TC2_WO1)
|
||||
#define PORT_PA31E_TC2_WO1 (1ul << 31)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN2 4L /**< \brief ADC signal: AIN2 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN2 1L
|
||||
#define PINMUX_PA04B_ADC_AIN2 ((PIN_PA04B_ADC_AIN2 << 16) | MUX_PA04B_ADC_AIN2)
|
||||
#define PORT_PA04B_ADC_AIN2 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN3 5L /**< \brief ADC signal: AIN3 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN3 1L
|
||||
#define PINMUX_PA05B_ADC_AIN3 ((PIN_PA05B_ADC_AIN3 << 16) | MUX_PA05B_ADC_AIN3)
|
||||
#define PORT_PA05B_ADC_AIN3 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN4 6L /**< \brief ADC signal: AIN4 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN4 1L
|
||||
#define PINMUX_PA06B_ADC_AIN4 ((PIN_PA06B_ADC_AIN4 << 16) | MUX_PA06B_ADC_AIN4)
|
||||
#define PORT_PA06B_ADC_AIN4 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN5 7L /**< \brief ADC signal: AIN5 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN5 1L
|
||||
#define PINMUX_PA07B_ADC_AIN5 ((PIN_PA07B_ADC_AIN5 << 16) | MUX_PA07B_ADC_AIN5)
|
||||
#define PORT_PA07B_ADC_AIN5 (1ul << 7)
|
||||
#define PIN_PA14B_ADC_AIN6 14L /**< \brief ADC signal: AIN6 on PA14 mux B */
|
||||
#define MUX_PA14B_ADC_AIN6 1L
|
||||
#define PINMUX_PA14B_ADC_AIN6 ((PIN_PA14B_ADC_AIN6 << 16) | MUX_PA14B_ADC_AIN6)
|
||||
#define PORT_PA14B_ADC_AIN6 (1ul << 14)
|
||||
#define PIN_PA15B_ADC_AIN7 15L /**< \brief ADC signal: AIN7 on PA15 mux B */
|
||||
#define MUX_PA15B_ADC_AIN7 1L
|
||||
#define PINMUX_PA15B_ADC_AIN7 ((PIN_PA15B_ADC_AIN7 << 16) | MUX_PA15B_ADC_AIN7)
|
||||
#define PORT_PA15B_ADC_AIN7 (1ul << 15)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA14G_AC_CMP0 14L /**< \brief AC signal: CMP0 on PA14 mux G */
|
||||
#define MUX_PA14G_AC_CMP0 6L
|
||||
#define PINMUX_PA14G_AC_CMP0 ((PIN_PA14G_AC_CMP0 << 16) | MUX_PA14G_AC_CMP0)
|
||||
#define PORT_PA14G_AC_CMP0 (1ul << 14)
|
||||
#define PIN_PA15G_AC_CMP1 15L /**< \brief AC signal: CMP1 on PA15 mux G */
|
||||
#define MUX_PA15G_AC_CMP1 6L
|
||||
#define PINMUX_PA15G_AC_CMP1 ((PIN_PA15G_AC_CMP1 << 16) | MUX_PA15G_AC_CMP1)
|
||||
#define PORT_PA15G_AC_CMP1 (1ul << 15)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
|
||||
#endif /* _SAMD11D14AU_PIO_ */
|
|
@ -1,644 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E15A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E15A_PIO_
|
||||
#define _SAMD21E15A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E15A_PIO_ */
|
|
@ -1,641 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E15B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E15B_PIO_
|
||||
#define _SAMD21E15B_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E15B_PIO_ */
|
|
@ -1,641 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E15BU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E15BU_PIO_
|
||||
#define _SAMD21E15BU_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E15BU_PIO_ */
|
|
@ -1,620 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E15L
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E15L_PIO_
|
||||
#define _SAMD21E15L_PIO_
|
||||
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
|
||||
#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
|
||||
#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
|
||||
#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
|
||||
#define MUX_PB04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
|
||||
#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
|
||||
#define MUX_PB05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
|
||||
#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
|
||||
#define MUX_PB04B_ADC_AIN12 1L
|
||||
#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
|
||||
#define PORT_PB04B_ADC_AIN12 (1ul << 4)
|
||||
#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
|
||||
#define MUX_PB05B_ADC_AIN13 1L
|
||||
#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
|
||||
#define PORT_PB05B_ADC_AIN13 (1ul << 5)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for AC1 peripheral ========== */
|
||||
#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */
|
||||
#define MUX_PB04B_AC1_AIN0 1L
|
||||
#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
|
||||
#define PORT_PB04B_AC1_AIN0 (1ul << 4)
|
||||
#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */
|
||||
#define MUX_PB05B_AC1_AIN1 1L
|
||||
#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
|
||||
#define PORT_PB05B_AC1_AIN1 (1ul << 5)
|
||||
#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */
|
||||
#define MUX_PB02B_AC1_AIN2 1L
|
||||
#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
|
||||
#define PORT_PB02B_AC1_AIN2 (1ul << 2)
|
||||
#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */
|
||||
#define MUX_PB03B_AC1_AIN3 1L
|
||||
#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
|
||||
#define PORT_PB03B_AC1_AIN3 (1ul << 3)
|
||||
#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */
|
||||
#define MUX_PA24H_AC1_CMP0 7L
|
||||
#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
|
||||
#define PORT_PA24H_AC1_CMP0 (1ul << 24)
|
||||
#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */
|
||||
#define MUX_PA25H_AC1_CMP1 7L
|
||||
#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
|
||||
#define PORT_PA25H_AC1_CMP1 (1ul << 25)
|
||||
|
||||
#endif /* _SAMD21E15L_PIO_ */
|
|
@ -1,644 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E16A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E16A_PIO_
|
||||
#define _SAMD21E16A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E16A_PIO_ */
|
|
@ -1,641 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E16B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E16B_PIO_
|
||||
#define _SAMD21E16B_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E16B_PIO_ */
|
|
@ -1,641 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E16BU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E16BU_PIO_
|
||||
#define _SAMD21E16BU_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E16BU_PIO_ */
|
|
@ -1,620 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E16L
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E16L_PIO_
|
||||
#define _SAMD21E16L_PIO_
|
||||
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
|
||||
#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
|
||||
#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
|
||||
#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
|
||||
#define MUX_PB04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
|
||||
#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
|
||||
#define MUX_PB05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
|
||||
#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
|
||||
#define MUX_PB04B_ADC_AIN12 1L
|
||||
#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
|
||||
#define PORT_PB04B_ADC_AIN12 (1ul << 4)
|
||||
#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
|
||||
#define MUX_PB05B_ADC_AIN13 1L
|
||||
#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
|
||||
#define PORT_PB05B_ADC_AIN13 (1ul << 5)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for AC1 peripheral ========== */
|
||||
#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */
|
||||
#define MUX_PB04B_AC1_AIN0 1L
|
||||
#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0)
|
||||
#define PORT_PB04B_AC1_AIN0 (1ul << 4)
|
||||
#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */
|
||||
#define MUX_PB05B_AC1_AIN1 1L
|
||||
#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1)
|
||||
#define PORT_PB05B_AC1_AIN1 (1ul << 5)
|
||||
#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */
|
||||
#define MUX_PB02B_AC1_AIN2 1L
|
||||
#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2)
|
||||
#define PORT_PB02B_AC1_AIN2 (1ul << 2)
|
||||
#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */
|
||||
#define MUX_PB03B_AC1_AIN3 1L
|
||||
#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3)
|
||||
#define PORT_PB03B_AC1_AIN3 (1ul << 3)
|
||||
#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */
|
||||
#define MUX_PA24H_AC1_CMP0 7L
|
||||
#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0)
|
||||
#define PORT_PA24H_AC1_CMP0 (1ul << 24)
|
||||
#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */
|
||||
#define MUX_PA25H_AC1_CMP1 7L
|
||||
#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1)
|
||||
#define PORT_PA25H_AC1_CMP1 (1ul << 25)
|
||||
|
||||
#endif /* _SAMD21E16L_PIO_ */
|
|
@ -1,644 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E17A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E17A_PIO_
|
||||
#define _SAMD21E17A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E17A_PIO_ */
|
|
@ -1,644 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21E18A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E18A_PIO_
|
||||
#define _SAMD21E18A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21E18A_PIO_ */
|
|
@ -1,918 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G15A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G15A_PIO_
|
||||
#define _SAMD21G15A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
|
||||
#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
|
||||
#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
|
||||
#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
|
||||
#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
|
||||
#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
|
||||
#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
|
||||
#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
|
||||
#define MUX_PB22H_GCLK_IO0 7L
|
||||
#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
|
||||
#define PORT_PB22H_GCLK_IO0 (1ul << 22)
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
|
||||
#define MUX_PB23H_GCLK_IO1 7L
|
||||
#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
|
||||
#define PORT_PB23H_GCLK_IO1 (1ul << 23)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
|
||||
#define MUX_PB10H_GCLK_IO4 7L
|
||||
#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
|
||||
#define PORT_PB10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
|
||||
#define MUX_PB11H_GCLK_IO5 7L
|
||||
#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
|
||||
#define PORT_PB11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
||||
#define MUX_PB22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
||||
#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
||||
#define MUX_PB23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
||||
#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
||||
#define MUX_PB10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
||||
#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
||||
#define MUX_PB11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
||||
#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
||||
#define MUX_PB10D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
||||
#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
||||
#define MUX_PB11D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
||||
#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
||||
#define MUX_PB22D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
||||
#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
||||
#define MUX_PB23D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
||||
#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
||||
#define MUX_PB10F_TCC0_WO4 5L
|
||||
#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
||||
#define PORT_PB10F_TCC0_WO4 (1ul << 10)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
||||
#define MUX_PB11F_TCC0_WO5 5L
|
||||
#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
||||
#define PORT_PB11F_TCC0_WO5 (1ul << 11)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
|
||||
#define MUX_PB10E_TC5_WO0 4L
|
||||
#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
||||
#define PORT_PB10E_TC5_WO0 (1ul << 10)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
|
||||
#define MUX_PB11E_TC5_WO1 4L
|
||||
#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
||||
#define PORT_PB11E_TC5_WO1 (1ul << 11)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
|
||||
#define MUX_PB10G_I2S_MCK1 6L
|
||||
#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
|
||||
#define PORT_PB10G_I2S_MCK1 (1ul << 10)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
|
||||
#define MUX_PB11G_I2S_SCK1 6L
|
||||
#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
|
||||
#define PORT_PB11G_I2S_SCK1 (1ul << 11)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G15A_PIO_ */
|
|
@ -1,915 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G15B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G15B_PIO_
|
||||
#define _SAMD21G15B_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
|
||||
#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
|
||||
#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
|
||||
#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
|
||||
#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
|
||||
#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
|
||||
#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
|
||||
#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
|
||||
#define MUX_PB22H_GCLK_IO0 7L
|
||||
#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
|
||||
#define PORT_PB22H_GCLK_IO0 (1ul << 22)
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
|
||||
#define MUX_PB23H_GCLK_IO1 7L
|
||||
#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
|
||||
#define PORT_PB23H_GCLK_IO1 (1ul << 23)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
|
||||
#define MUX_PB10H_GCLK_IO4 7L
|
||||
#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
|
||||
#define PORT_PB10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
|
||||
#define MUX_PB11H_GCLK_IO5 7L
|
||||
#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
|
||||
#define PORT_PB11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
||||
#define MUX_PB22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
||||
#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
||||
#define MUX_PB23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
||||
#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
||||
#define MUX_PB10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
||||
#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
||||
#define MUX_PB11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
||||
#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
||||
#define MUX_PB10D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
||||
#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
||||
#define MUX_PB11D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
||||
#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
||||
#define MUX_PB22D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
||||
#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
||||
#define MUX_PB23D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
||||
#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
||||
#define MUX_PB10F_TCC0_WO4 5L
|
||||
#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
||||
#define PORT_PB10F_TCC0_WO4 (1ul << 10)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
||||
#define MUX_PB11F_TCC0_WO5 5L
|
||||
#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
||||
#define PORT_PB11F_TCC0_WO5 (1ul << 11)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
|
||||
#define MUX_PB10E_TC5_WO0 4L
|
||||
#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
||||
#define PORT_PB10E_TC5_WO0 (1ul << 10)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
|
||||
#define MUX_PB11E_TC5_WO1 4L
|
||||
#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
||||
#define PORT_PB11E_TC5_WO1 (1ul << 11)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
|
||||
#define MUX_PB10G_I2S_MCK1 6L
|
||||
#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
|
||||
#define PORT_PB10G_I2S_MCK1 (1ul << 10)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
|
||||
#define MUX_PB11G_I2S_SCK1 6L
|
||||
#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
|
||||
#define PORT_PB11G_I2S_SCK1 (1ul << 11)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G15B_PIO_ */
|
|
@ -1,918 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G16A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G16A_PIO_
|
||||
#define _SAMD21G16A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
|
||||
#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
|
||||
#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
|
||||
#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
|
||||
#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
|
||||
#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
|
||||
#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
|
||||
#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
|
||||
#define MUX_PB22H_GCLK_IO0 7L
|
||||
#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
|
||||
#define PORT_PB22H_GCLK_IO0 (1ul << 22)
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
|
||||
#define MUX_PB23H_GCLK_IO1 7L
|
||||
#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
|
||||
#define PORT_PB23H_GCLK_IO1 (1ul << 23)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
|
||||
#define MUX_PB10H_GCLK_IO4 7L
|
||||
#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
|
||||
#define PORT_PB10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
|
||||
#define MUX_PB11H_GCLK_IO5 7L
|
||||
#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
|
||||
#define PORT_PB11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
||||
#define MUX_PB22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
||||
#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
||||
#define MUX_PB23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
||||
#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
||||
#define MUX_PB10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
||||
#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
||||
#define MUX_PB11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
||||
#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
||||
#define MUX_PB10D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
||||
#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
||||
#define MUX_PB11D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
||||
#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
||||
#define MUX_PB22D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
||||
#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
||||
#define MUX_PB23D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
||||
#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
||||
#define MUX_PB10F_TCC0_WO4 5L
|
||||
#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
||||
#define PORT_PB10F_TCC0_WO4 (1ul << 10)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
||||
#define MUX_PB11F_TCC0_WO5 5L
|
||||
#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
||||
#define PORT_PB11F_TCC0_WO5 (1ul << 11)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
|
||||
#define MUX_PB10E_TC5_WO0 4L
|
||||
#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
||||
#define PORT_PB10E_TC5_WO0 (1ul << 10)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
|
||||
#define MUX_PB11E_TC5_WO1 4L
|
||||
#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
||||
#define PORT_PB11E_TC5_WO1 (1ul << 11)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
|
||||
#define MUX_PB10G_I2S_MCK1 6L
|
||||
#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
|
||||
#define PORT_PB10G_I2S_MCK1 (1ul << 10)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
|
||||
#define MUX_PB11G_I2S_SCK1 6L
|
||||
#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
|
||||
#define PORT_PB11G_I2S_SCK1 (1ul << 11)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G16A_PIO_ */
|
|
@ -1,915 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G16B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G16B_PIO_
|
||||
#define _SAMD21G16B_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
|
||||
#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
|
||||
#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
|
||||
#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
|
||||
#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
|
||||
#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
|
||||
#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
|
||||
#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
|
||||
#define MUX_PB22H_GCLK_IO0 7L
|
||||
#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
|
||||
#define PORT_PB22H_GCLK_IO0 (1ul << 22)
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
|
||||
#define MUX_PB23H_GCLK_IO1 7L
|
||||
#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
|
||||
#define PORT_PB23H_GCLK_IO1 (1ul << 23)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
|
||||
#define MUX_PB10H_GCLK_IO4 7L
|
||||
#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
|
||||
#define PORT_PB10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
|
||||
#define MUX_PB11H_GCLK_IO5 7L
|
||||
#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
|
||||
#define PORT_PB11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
||||
#define MUX_PB22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
||||
#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
||||
#define MUX_PB23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
||||
#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
||||
#define MUX_PB10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
||||
#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
||||
#define MUX_PB11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
||||
#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
||||
#define MUX_PB10D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
||||
#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
||||
#define MUX_PB11D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
||||
#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
||||
#define MUX_PB22D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
||||
#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
||||
#define MUX_PB23D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
||||
#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
||||
#define MUX_PB10F_TCC0_WO4 5L
|
||||
#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
||||
#define PORT_PB10F_TCC0_WO4 (1ul << 10)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
||||
#define MUX_PB11F_TCC0_WO5 5L
|
||||
#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
||||
#define PORT_PB11F_TCC0_WO5 (1ul << 11)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
|
||||
#define MUX_PB10E_TC5_WO0 4L
|
||||
#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
||||
#define PORT_PB10E_TC5_WO0 (1ul << 10)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
|
||||
#define MUX_PB11E_TC5_WO1 4L
|
||||
#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
||||
#define PORT_PB11E_TC5_WO1 (1ul << 11)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
|
||||
#define MUX_PB10G_I2S_MCK1 6L
|
||||
#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
|
||||
#define PORT_PB10G_I2S_MCK1 (1ul << 10)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
|
||||
#define MUX_PB11G_I2S_SCK1 6L
|
||||
#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
|
||||
#define PORT_PB11G_I2S_SCK1 (1ul << 11)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G16B_PIO_ */
|
|
@ -1,918 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G17A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G17A_PIO_
|
||||
#define _SAMD21G17A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
|
||||
#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
|
||||
#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
|
||||
#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
|
||||
#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
|
||||
#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
|
||||
#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
|
||||
#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
|
||||
#define MUX_PB22H_GCLK_IO0 7L
|
||||
#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
|
||||
#define PORT_PB22H_GCLK_IO0 (1ul << 22)
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
|
||||
#define MUX_PB23H_GCLK_IO1 7L
|
||||
#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
|
||||
#define PORT_PB23H_GCLK_IO1 (1ul << 23)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
|
||||
#define MUX_PB10H_GCLK_IO4 7L
|
||||
#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
|
||||
#define PORT_PB10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
|
||||
#define MUX_PB11H_GCLK_IO5 7L
|
||||
#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
|
||||
#define PORT_PB11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
||||
#define MUX_PB22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
||||
#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
||||
#define MUX_PB23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
||||
#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
||||
#define MUX_PB10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
||||
#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
||||
#define MUX_PB11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
||||
#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
||||
#define MUX_PB10D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
||||
#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
||||
#define MUX_PB11D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
||||
#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
||||
#define MUX_PB22D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
||||
#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
||||
#define MUX_PB23D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
||||
#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
||||
#define MUX_PB10F_TCC0_WO4 5L
|
||||
#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
||||
#define PORT_PB10F_TCC0_WO4 (1ul << 10)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
||||
#define MUX_PB11F_TCC0_WO5 5L
|
||||
#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
||||
#define PORT_PB11F_TCC0_WO5 (1ul << 11)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
|
||||
#define MUX_PB10E_TC5_WO0 4L
|
||||
#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
||||
#define PORT_PB10E_TC5_WO0 (1ul << 10)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
|
||||
#define MUX_PB11E_TC5_WO1 4L
|
||||
#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
||||
#define PORT_PB11E_TC5_WO1 (1ul << 11)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
|
||||
#define MUX_PB10G_I2S_MCK1 6L
|
||||
#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
|
||||
#define PORT_PB10G_I2S_MCK1 (1ul << 10)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
|
||||
#define MUX_PB11G_I2S_SCK1 6L
|
||||
#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
|
||||
#define PORT_PB11G_I2S_SCK1 (1ul << 11)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G17A_PIO_ */
|
|
@ -1,866 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G17AU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G17AU_PIO_
|
||||
#define _SAMD21G17AU_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
|
||||
#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
|
||||
#define MUX_PB04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
|
||||
#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for TC6 peripheral ========== */
|
||||
#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
|
||||
#define MUX_PB02E_TC6_WO0 4L
|
||||
#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
|
||||
#define PORT_PB02E_TC6_WO0 (1ul << 2)
|
||||
#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
|
||||
#define MUX_PB03E_TC6_WO1 4L
|
||||
#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
|
||||
#define PORT_PB03E_TC6_WO1 (1ul << 3)
|
||||
/* ========== PORT definition for TC7 peripheral ========== */
|
||||
#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
|
||||
#define MUX_PA20E_TC7_WO0 4L
|
||||
#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
|
||||
#define PORT_PA20E_TC7_WO0 (1ul << 20)
|
||||
#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
|
||||
#define MUX_PA21E_TC7_WO1 4L
|
||||
#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
|
||||
#define PORT_PA21E_TC7_WO1 (1ul << 21)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
|
||||
#define MUX_PB04B_ADC_AIN12 1L
|
||||
#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
|
||||
#define PORT_PB04B_ADC_AIN12 (1ul << 4)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G17AU_PIO_ */
|
|
@ -1,918 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G18A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G18A_PIO_
|
||||
#define _SAMD21G18A_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
|
||||
#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
|
||||
#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
|
||||
#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
|
||||
#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
|
||||
#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
|
||||
#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
|
||||
#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
|
||||
#define MUX_PB22H_GCLK_IO0 7L
|
||||
#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
|
||||
#define PORT_PB22H_GCLK_IO0 (1ul << 22)
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
|
||||
#define MUX_PB23H_GCLK_IO1 7L
|
||||
#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
|
||||
#define PORT_PB23H_GCLK_IO1 (1ul << 23)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
|
||||
#define MUX_PB10H_GCLK_IO4 7L
|
||||
#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
|
||||
#define PORT_PB10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
|
||||
#define MUX_PB11H_GCLK_IO5 7L
|
||||
#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
|
||||
#define PORT_PB11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
||||
#define MUX_PB22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
||||
#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
||||
#define MUX_PB23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
||||
#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
||||
#define MUX_PB10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
||||
#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
||||
#define MUX_PB11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
||||
#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
||||
#define MUX_PB10D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
||||
#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
||||
#define MUX_PB11D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
||||
#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
||||
#define MUX_PB22D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
||||
#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
||||
#define MUX_PB23D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
||||
#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
||||
#define MUX_PB10F_TCC0_WO4 5L
|
||||
#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
||||
#define PORT_PB10F_TCC0_WO4 (1ul << 10)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
||||
#define MUX_PB11F_TCC0_WO5 5L
|
||||
#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
||||
#define PORT_PB11F_TCC0_WO5 (1ul << 11)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
|
||||
#define MUX_PB10E_TC5_WO0 4L
|
||||
#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
||||
#define PORT_PB10E_TC5_WO0 (1ul << 10)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
|
||||
#define MUX_PB11E_TC5_WO1 4L
|
||||
#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
||||
#define PORT_PB11E_TC5_WO1 (1ul << 11)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
|
||||
#define MUX_PB10G_I2S_MCK1 6L
|
||||
#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
|
||||
#define PORT_PB10G_I2S_MCK1 (1ul << 10)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
|
||||
#define MUX_PB11G_I2S_SCK1 6L
|
||||
#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
|
||||
#define PORT_PB11G_I2S_SCK1 (1ul << 11)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G18A_PIO_ */
|
|
@ -1,866 +0,0 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Peripheral I/O description for SAMD21G18AU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel microcontroller product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G18AU_PIO_
|
||||
#define _SAMD21G18AU_PIO_
|
||||
|
||||
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
|
||||
#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
|
||||
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
|
||||
#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
|
||||
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
|
||||
#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
|
||||
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
|
||||
#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
|
||||
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
|
||||
#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
|
||||
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
|
||||
#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
|
||||
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
|
||||
#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
|
||||
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
|
||||
#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
|
||||
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
|
||||
#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
|
||||
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
|
||||
#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
|
||||
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
|
||||
#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
|
||||
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
|
||||
#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
|
||||
#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
|
||||
#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
|
||||
#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
|
||||
#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
|
||||
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
|
||||
#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
|
||||
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
|
||||
#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
|
||||
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
|
||||
#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
|
||||
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
|
||||
#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
|
||||
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
|
||||
#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
|
||||
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
|
||||
#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
|
||||
#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
|
||||
#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
|
||||
#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
|
||||
#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
|
||||
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
|
||||
#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
|
||||
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
|
||||
#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
|
||||
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
|
||||
#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
|
||||
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
|
||||
#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
|
||||
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
|
||||
#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
|
||||
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
|
||||
#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
|
||||
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
|
||||
#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
|
||||
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
|
||||
#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
|
||||
#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
|
||||
#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
|
||||
#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
|
||||
#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
|
||||
#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
|
||||
#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
|
||||
#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
|
||||
#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
|
||||
#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
|
||||
#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
|
||||
/* ========== PORT definition for GCLK peripheral ========== */
|
||||
#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
|
||||
#define MUX_PA14H_GCLK_IO0 7L
|
||||
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
|
||||
#define PORT_PA14H_GCLK_IO0 (1ul << 14)
|
||||
#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
|
||||
#define MUX_PA27H_GCLK_IO0 7L
|
||||
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
|
||||
#define PORT_PA27H_GCLK_IO0 (1ul << 27)
|
||||
#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
|
||||
#define MUX_PA28H_GCLK_IO0 7L
|
||||
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
|
||||
#define PORT_PA28H_GCLK_IO0 (1ul << 28)
|
||||
#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
|
||||
#define MUX_PA30H_GCLK_IO0 7L
|
||||
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
|
||||
#define PORT_PA30H_GCLK_IO0 (1ul << 30)
|
||||
#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
|
||||
#define MUX_PA15H_GCLK_IO1 7L
|
||||
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
|
||||
#define PORT_PA15H_GCLK_IO1 (1ul << 15)
|
||||
#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
|
||||
#define MUX_PA16H_GCLK_IO2 7L
|
||||
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
|
||||
#define PORT_PA16H_GCLK_IO2 (1ul << 16)
|
||||
#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
|
||||
#define MUX_PA17H_GCLK_IO3 7L
|
||||
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
|
||||
#define PORT_PA17H_GCLK_IO3 (1ul << 17)
|
||||
#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
|
||||
#define MUX_PA10H_GCLK_IO4 7L
|
||||
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
|
||||
#define PORT_PA10H_GCLK_IO4 (1ul << 10)
|
||||
#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
|
||||
#define MUX_PA20H_GCLK_IO4 7L
|
||||
#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
|
||||
#define PORT_PA20H_GCLK_IO4 (1ul << 20)
|
||||
#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
|
||||
#define MUX_PA11H_GCLK_IO5 7L
|
||||
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
|
||||
#define PORT_PA11H_GCLK_IO5 (1ul << 11)
|
||||
#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
|
||||
#define MUX_PA21H_GCLK_IO5 7L
|
||||
#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
|
||||
#define PORT_PA21H_GCLK_IO5 (1ul << 21)
|
||||
#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
|
||||
#define MUX_PA22H_GCLK_IO6 7L
|
||||
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
|
||||
#define PORT_PA22H_GCLK_IO6 (1ul << 22)
|
||||
#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
|
||||
#define MUX_PA23H_GCLK_IO7 7L
|
||||
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
|
||||
#define PORT_PA23H_GCLK_IO7 (1ul << 23)
|
||||
/* ========== PORT definition for EIC peripheral ========== */
|
||||
#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
||||
#define MUX_PA16A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
||||
#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
|
||||
#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
||||
#define MUX_PA00A_EIC_EXTINT0 0L
|
||||
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
||||
#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
|
||||
#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
||||
#define MUX_PA17A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
||||
#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
|
||||
#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
||||
#define MUX_PA01A_EIC_EXTINT1 0L
|
||||
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
||||
#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
|
||||
#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
||||
#define MUX_PA18A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
||||
#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
|
||||
#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
||||
#define MUX_PA02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
||||
#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
||||
#define MUX_PB02A_EIC_EXTINT2 0L
|
||||
#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
||||
#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
|
||||
#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
||||
#define MUX_PA03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
||||
#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
||||
#define MUX_PA19A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
||||
#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
|
||||
#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
||||
#define MUX_PB03A_EIC_EXTINT3 0L
|
||||
#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
||||
#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
|
||||
#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
||||
#define MUX_PA04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
||||
#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
||||
#define MUX_PA20A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
||||
#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
|
||||
#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
|
||||
#define MUX_PB04A_EIC_EXTINT4 0L
|
||||
#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
|
||||
#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
|
||||
#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
||||
#define MUX_PA05A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
||||
#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
|
||||
#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
||||
#define MUX_PA21A_EIC_EXTINT5 0L
|
||||
#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
||||
#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
|
||||
#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
||||
#define MUX_PA06A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
|
||||
#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
|
||||
#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
||||
#define MUX_PA22A_EIC_EXTINT6 0L
|
||||
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
|
||||
#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
|
||||
#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
||||
#define MUX_PA07A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
|
||||
#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
|
||||
#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
||||
#define MUX_PA23A_EIC_EXTINT7 0L
|
||||
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
||||
#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
|
||||
#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
|
||||
#define MUX_PA28A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
|
||||
#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
|
||||
#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
||||
#define MUX_PB08A_EIC_EXTINT8 0L
|
||||
#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
||||
#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
|
||||
#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
||||
#define MUX_PA09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
||||
#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
||||
#define MUX_PB09A_EIC_EXTINT9 0L
|
||||
#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
||||
#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
|
||||
#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
||||
#define MUX_PA10A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
||||
#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
|
||||
#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
|
||||
#define MUX_PA30A_EIC_EXTINT10 0L
|
||||
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
|
||||
#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
|
||||
#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
||||
#define MUX_PA11A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
||||
#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
|
||||
#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
|
||||
#define MUX_PA31A_EIC_EXTINT11 0L
|
||||
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
|
||||
#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
|
||||
#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
||||
#define MUX_PA12A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
||||
#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
|
||||
#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
|
||||
#define MUX_PA24A_EIC_EXTINT12 0L
|
||||
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
|
||||
#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
|
||||
#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
||||
#define MUX_PA13A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
||||
#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
|
||||
#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
|
||||
#define MUX_PA25A_EIC_EXTINT13 0L
|
||||
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
|
||||
#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
|
||||
#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
||||
#define MUX_PA14A_EIC_EXTINT14 0L
|
||||
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
||||
#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
|
||||
#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
||||
#define MUX_PA15A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
||||
#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
|
||||
#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
|
||||
#define MUX_PA27A_EIC_EXTINT15 0L
|
||||
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
|
||||
#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
|
||||
#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
|
||||
#define MUX_PA08A_EIC_NMI 0L
|
||||
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
||||
#define PORT_PA08A_EIC_NMI (1ul << 8)
|
||||
/* ========== PORT definition for USB peripheral ========== */
|
||||
#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
|
||||
#define MUX_PA24G_USB_DM 6L
|
||||
#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
|
||||
#define PORT_PA24G_USB_DM (1ul << 24)
|
||||
#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
|
||||
#define MUX_PA25G_USB_DP 6L
|
||||
#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
|
||||
#define PORT_PA25G_USB_DP (1ul << 25)
|
||||
#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
|
||||
#define MUX_PA23G_USB_SOF_1KHZ 6L
|
||||
#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
|
||||
#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
|
||||
/* ========== PORT definition for SERCOM0 peripheral ========== */
|
||||
#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
||||
#define MUX_PA04D_SERCOM0_PAD0 3L
|
||||
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
||||
#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
|
||||
#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
||||
#define MUX_PA08C_SERCOM0_PAD0 2L
|
||||
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
||||
#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
|
||||
#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
||||
#define MUX_PA05D_SERCOM0_PAD1 3L
|
||||
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
||||
#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
|
||||
#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
||||
#define MUX_PA09C_SERCOM0_PAD1 2L
|
||||
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
||||
#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
|
||||
#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
||||
#define MUX_PA06D_SERCOM0_PAD2 3L
|
||||
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
||||
#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
|
||||
#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
||||
#define MUX_PA10C_SERCOM0_PAD2 2L
|
||||
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
||||
#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
|
||||
#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
||||
#define MUX_PA07D_SERCOM0_PAD3 3L
|
||||
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
||||
#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
|
||||
#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
||||
#define MUX_PA11C_SERCOM0_PAD3 2L
|
||||
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
||||
#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
|
||||
/* ========== PORT definition for SERCOM1 peripheral ========== */
|
||||
#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
||||
#define MUX_PA16C_SERCOM1_PAD0 2L
|
||||
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
||||
#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
|
||||
#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
||||
#define MUX_PA00D_SERCOM1_PAD0 3L
|
||||
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
||||
#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
|
||||
#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
||||
#define MUX_PA17C_SERCOM1_PAD1 2L
|
||||
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
||||
#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
|
||||
#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
||||
#define MUX_PA01D_SERCOM1_PAD1 3L
|
||||
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
||||
#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
|
||||
#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
||||
#define MUX_PA30D_SERCOM1_PAD2 3L
|
||||
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
||||
#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
|
||||
#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
||||
#define MUX_PA18C_SERCOM1_PAD2 2L
|
||||
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
||||
#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
|
||||
#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
||||
#define MUX_PA31D_SERCOM1_PAD3 3L
|
||||
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
||||
#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
|
||||
#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
||||
#define MUX_PA19C_SERCOM1_PAD3 2L
|
||||
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
||||
#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
|
||||
/* ========== PORT definition for SERCOM2 peripheral ========== */
|
||||
#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
|
||||
#define MUX_PA08D_SERCOM2_PAD0 3L
|
||||
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
|
||||
#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
|
||||
#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
||||
#define MUX_PA12C_SERCOM2_PAD0 2L
|
||||
#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
||||
#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
|
||||
#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
|
||||
#define MUX_PA09D_SERCOM2_PAD1 3L
|
||||
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
|
||||
#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
|
||||
#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
||||
#define MUX_PA13C_SERCOM2_PAD1 2L
|
||||
#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
||||
#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
|
||||
#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
||||
#define MUX_PA10D_SERCOM2_PAD2 3L
|
||||
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
||||
#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
|
||||
#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
||||
#define MUX_PA14C_SERCOM2_PAD2 2L
|
||||
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
||||
#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
|
||||
#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
||||
#define MUX_PA11D_SERCOM2_PAD3 3L
|
||||
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
||||
#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
|
||||
#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
||||
#define MUX_PA15C_SERCOM2_PAD3 2L
|
||||
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
||||
#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM3 peripheral ========== */
|
||||
#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
|
||||
#define MUX_PA16D_SERCOM3_PAD0 3L
|
||||
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
|
||||
#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
|
||||
#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
||||
#define MUX_PA22C_SERCOM3_PAD0 2L
|
||||
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
||||
#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
|
||||
#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
|
||||
#define MUX_PA17D_SERCOM3_PAD1 3L
|
||||
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
|
||||
#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
|
||||
#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
||||
#define MUX_PA23C_SERCOM3_PAD1 2L
|
||||
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
||||
#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
|
||||
#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
||||
#define MUX_PA18D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
||||
#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
|
||||
#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
||||
#define MUX_PA20D_SERCOM3_PAD2 3L
|
||||
#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
||||
#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
|
||||
#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
||||
#define MUX_PA24C_SERCOM3_PAD2 2L
|
||||
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
||||
#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
|
||||
#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
||||
#define MUX_PA19D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
||||
#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
|
||||
#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
||||
#define MUX_PA21D_SERCOM3_PAD3 3L
|
||||
#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
||||
#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
|
||||
#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
||||
#define MUX_PA25C_SERCOM3_PAD3 2L
|
||||
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
||||
#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
|
||||
/* ========== PORT definition for SERCOM4 peripheral ========== */
|
||||
#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
|
||||
#define MUX_PA12D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
|
||||
#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
|
||||
#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
||||
#define MUX_PB08D_SERCOM4_PAD0 3L
|
||||
#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
||||
#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
|
||||
#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
|
||||
#define MUX_PA13D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
|
||||
#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
|
||||
#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
||||
#define MUX_PB09D_SERCOM4_PAD1 3L
|
||||
#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
||||
#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
|
||||
#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
||||
#define MUX_PA14D_SERCOM4_PAD2 3L
|
||||
#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
||||
#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
|
||||
#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
||||
#define MUX_PA15D_SERCOM4_PAD3 3L
|
||||
#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
||||
#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
|
||||
/* ========== PORT definition for SERCOM5 peripheral ========== */
|
||||
#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
|
||||
#define MUX_PA22D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
|
||||
#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
|
||||
#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
||||
#define MUX_PB02D_SERCOM5_PAD0 3L
|
||||
#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
||||
#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
|
||||
#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
|
||||
#define MUX_PA23D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
|
||||
#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
|
||||
#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
||||
#define MUX_PB03D_SERCOM5_PAD1 3L
|
||||
#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
||||
#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
|
||||
#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
||||
#define MUX_PA24D_SERCOM5_PAD2 3L
|
||||
#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
||||
#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
|
||||
#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
||||
#define MUX_PA20C_SERCOM5_PAD2 2L
|
||||
#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
||||
#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
|
||||
#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
||||
#define MUX_PA25D_SERCOM5_PAD3 3L
|
||||
#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
||||
#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
|
||||
#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
||||
#define MUX_PA21C_SERCOM5_PAD3 2L
|
||||
#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
||||
#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
|
||||
/* ========== PORT definition for TCC0 peripheral ========== */
|
||||
#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
|
||||
#define MUX_PA04E_TCC0_WO0 4L
|
||||
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
|
||||
#define PORT_PA04E_TCC0_WO0 (1ul << 4)
|
||||
#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
|
||||
#define MUX_PA08E_TCC0_WO0 4L
|
||||
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
|
||||
#define PORT_PA08E_TCC0_WO0 (1ul << 8)
|
||||
#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
|
||||
#define MUX_PA05E_TCC0_WO1 4L
|
||||
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
|
||||
#define PORT_PA05E_TCC0_WO1 (1ul << 5)
|
||||
#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
|
||||
#define MUX_PA09E_TCC0_WO1 4L
|
||||
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
|
||||
#define PORT_PA09E_TCC0_WO1 (1ul << 9)
|
||||
#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
||||
#define MUX_PA10F_TCC0_WO2 5L
|
||||
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
||||
#define PORT_PA10F_TCC0_WO2 (1ul << 10)
|
||||
#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
|
||||
#define MUX_PA18F_TCC0_WO2 5L
|
||||
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
|
||||
#define PORT_PA18F_TCC0_WO2 (1ul << 18)
|
||||
#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
||||
#define MUX_PA11F_TCC0_WO3 5L
|
||||
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
||||
#define PORT_PA11F_TCC0_WO3 (1ul << 11)
|
||||
#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
|
||||
#define MUX_PA19F_TCC0_WO3 5L
|
||||
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
|
||||
#define PORT_PA19F_TCC0_WO3 (1ul << 19)
|
||||
#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
|
||||
#define MUX_PA14F_TCC0_WO4 5L
|
||||
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
|
||||
#define PORT_PA14F_TCC0_WO4 (1ul << 14)
|
||||
#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
|
||||
#define MUX_PA22F_TCC0_WO4 5L
|
||||
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
|
||||
#define PORT_PA22F_TCC0_WO4 (1ul << 22)
|
||||
#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
|
||||
#define MUX_PA15F_TCC0_WO5 5L
|
||||
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
|
||||
#define PORT_PA15F_TCC0_WO5 (1ul << 15)
|
||||
#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
|
||||
#define MUX_PA23F_TCC0_WO5 5L
|
||||
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
|
||||
#define PORT_PA23F_TCC0_WO5 (1ul << 23)
|
||||
#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
||||
#define MUX_PA12F_TCC0_WO6 5L
|
||||
#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
||||
#define PORT_PA12F_TCC0_WO6 (1ul << 12)
|
||||
#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
|
||||
#define MUX_PA20F_TCC0_WO6 5L
|
||||
#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
|
||||
#define PORT_PA20F_TCC0_WO6 (1ul << 20)
|
||||
#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
|
||||
#define MUX_PA16F_TCC0_WO6 5L
|
||||
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
|
||||
#define PORT_PA16F_TCC0_WO6 (1ul << 16)
|
||||
#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
||||
#define MUX_PA13F_TCC0_WO7 5L
|
||||
#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
||||
#define PORT_PA13F_TCC0_WO7 (1ul << 13)
|
||||
#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
|
||||
#define MUX_PA21F_TCC0_WO7 5L
|
||||
#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
|
||||
#define PORT_PA21F_TCC0_WO7 (1ul << 21)
|
||||
#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
|
||||
#define MUX_PA17F_TCC0_WO7 5L
|
||||
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
|
||||
#define PORT_PA17F_TCC0_WO7 (1ul << 17)
|
||||
/* ========== PORT definition for TCC1 peripheral ========== */
|
||||
#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
|
||||
#define MUX_PA06E_TCC1_WO0 4L
|
||||
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
|
||||
#define PORT_PA06E_TCC1_WO0 (1ul << 6)
|
||||
#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
|
||||
#define MUX_PA10E_TCC1_WO0 4L
|
||||
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
|
||||
#define PORT_PA10E_TCC1_WO0 (1ul << 10)
|
||||
#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
|
||||
#define MUX_PA30E_TCC1_WO0 4L
|
||||
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
|
||||
#define PORT_PA30E_TCC1_WO0 (1ul << 30)
|
||||
#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
|
||||
#define MUX_PA07E_TCC1_WO1 4L
|
||||
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
|
||||
#define PORT_PA07E_TCC1_WO1 (1ul << 7)
|
||||
#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
|
||||
#define MUX_PA11E_TCC1_WO1 4L
|
||||
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
|
||||
#define PORT_PA11E_TCC1_WO1 (1ul << 11)
|
||||
#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
|
||||
#define MUX_PA31E_TCC1_WO1 4L
|
||||
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
|
||||
#define PORT_PA31E_TCC1_WO1 (1ul << 31)
|
||||
#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
|
||||
#define MUX_PA08F_TCC1_WO2 5L
|
||||
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
|
||||
#define PORT_PA08F_TCC1_WO2 (1ul << 8)
|
||||
#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
|
||||
#define MUX_PA24F_TCC1_WO2 5L
|
||||
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
|
||||
#define PORT_PA24F_TCC1_WO2 (1ul << 24)
|
||||
#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
|
||||
#define MUX_PA09F_TCC1_WO3 5L
|
||||
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
|
||||
#define PORT_PA09F_TCC1_WO3 (1ul << 9)
|
||||
#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
|
||||
#define MUX_PA25F_TCC1_WO3 5L
|
||||
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
|
||||
#define PORT_PA25F_TCC1_WO3 (1ul << 25)
|
||||
/* ========== PORT definition for TCC2 peripheral ========== */
|
||||
#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
|
||||
#define MUX_PA12E_TCC2_WO0 4L
|
||||
#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
|
||||
#define PORT_PA12E_TCC2_WO0 (1ul << 12)
|
||||
#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
|
||||
#define MUX_PA16E_TCC2_WO0 4L
|
||||
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
|
||||
#define PORT_PA16E_TCC2_WO0 (1ul << 16)
|
||||
#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
|
||||
#define MUX_PA00E_TCC2_WO0 4L
|
||||
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
|
||||
#define PORT_PA00E_TCC2_WO0 (1ul << 0)
|
||||
#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
|
||||
#define MUX_PA13E_TCC2_WO1 4L
|
||||
#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
|
||||
#define PORT_PA13E_TCC2_WO1 (1ul << 13)
|
||||
#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
|
||||
#define MUX_PA17E_TCC2_WO1 4L
|
||||
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
|
||||
#define PORT_PA17E_TCC2_WO1 (1ul << 17)
|
||||
#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
|
||||
#define MUX_PA01E_TCC2_WO1 4L
|
||||
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
|
||||
#define PORT_PA01E_TCC2_WO1 (1ul << 1)
|
||||
/* ========== PORT definition for TC3 peripheral ========== */
|
||||
#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
|
||||
#define MUX_PA18E_TC3_WO0 4L
|
||||
#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
||||
#define PORT_PA18E_TC3_WO0 (1ul << 18)
|
||||
#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
|
||||
#define MUX_PA14E_TC3_WO0 4L
|
||||
#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
||||
#define PORT_PA14E_TC3_WO0 (1ul << 14)
|
||||
#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
|
||||
#define MUX_PA19E_TC3_WO1 4L
|
||||
#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
||||
#define PORT_PA19E_TC3_WO1 (1ul << 19)
|
||||
#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
|
||||
#define MUX_PA15E_TC3_WO1 4L
|
||||
#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
||||
#define PORT_PA15E_TC3_WO1 (1ul << 15)
|
||||
/* ========== PORT definition for TC4 peripheral ========== */
|
||||
#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
|
||||
#define MUX_PA22E_TC4_WO0 4L
|
||||
#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
||||
#define PORT_PA22E_TC4_WO0 (1ul << 22)
|
||||
#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
|
||||
#define MUX_PB08E_TC4_WO0 4L
|
||||
#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
||||
#define PORT_PB08E_TC4_WO0 (1ul << 8)
|
||||
#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
|
||||
#define MUX_PA23E_TC4_WO1 4L
|
||||
#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
||||
#define PORT_PA23E_TC4_WO1 (1ul << 23)
|
||||
#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
|
||||
#define MUX_PB09E_TC4_WO1 4L
|
||||
#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
||||
#define PORT_PB09E_TC4_WO1 (1ul << 9)
|
||||
/* ========== PORT definition for TC5 peripheral ========== */
|
||||
#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
|
||||
#define MUX_PA24E_TC5_WO0 4L
|
||||
#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
||||
#define PORT_PA24E_TC5_WO0 (1ul << 24)
|
||||
#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
|
||||
#define MUX_PA25E_TC5_WO1 4L
|
||||
#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
||||
#define PORT_PA25E_TC5_WO1 (1ul << 25)
|
||||
/* ========== PORT definition for TC6 peripheral ========== */
|
||||
#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
|
||||
#define MUX_PB02E_TC6_WO0 4L
|
||||
#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
|
||||
#define PORT_PB02E_TC6_WO0 (1ul << 2)
|
||||
#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
|
||||
#define MUX_PB03E_TC6_WO1 4L
|
||||
#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
|
||||
#define PORT_PB03E_TC6_WO1 (1ul << 3)
|
||||
/* ========== PORT definition for TC7 peripheral ========== */
|
||||
#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
|
||||
#define MUX_PA20E_TC7_WO0 4L
|
||||
#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
|
||||
#define PORT_PA20E_TC7_WO0 (1ul << 20)
|
||||
#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
|
||||
#define MUX_PA21E_TC7_WO1 4L
|
||||
#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
|
||||
#define PORT_PA21E_TC7_WO1 (1ul << 21)
|
||||
/* ========== PORT definition for ADC peripheral ========== */
|
||||
#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
|
||||
#define MUX_PA02B_ADC_AIN0 1L
|
||||
#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
|
||||
#define PORT_PA02B_ADC_AIN0 (1ul << 2)
|
||||
#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
|
||||
#define MUX_PA03B_ADC_AIN1 1L
|
||||
#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
|
||||
#define PORT_PA03B_ADC_AIN1 (1ul << 3)
|
||||
#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
|
||||
#define MUX_PB08B_ADC_AIN2 1L
|
||||
#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
|
||||
#define PORT_PB08B_ADC_AIN2 (1ul << 8)
|
||||
#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
|
||||
#define MUX_PB09B_ADC_AIN3 1L
|
||||
#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
|
||||
#define PORT_PB09B_ADC_AIN3 (1ul << 9)
|
||||
#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_AIN4 1L
|
||||
#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
|
||||
#define PORT_PA04B_ADC_AIN4 (1ul << 4)
|
||||
#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
|
||||
#define MUX_PA05B_ADC_AIN5 1L
|
||||
#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
|
||||
#define PORT_PA05B_ADC_AIN5 (1ul << 5)
|
||||
#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
|
||||
#define MUX_PA06B_ADC_AIN6 1L
|
||||
#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
|
||||
#define PORT_PA06B_ADC_AIN6 (1ul << 6)
|
||||
#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
|
||||
#define MUX_PA07B_ADC_AIN7 1L
|
||||
#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
|
||||
#define PORT_PA07B_ADC_AIN7 (1ul << 7)
|
||||
#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
|
||||
#define MUX_PB02B_ADC_AIN10 1L
|
||||
#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
|
||||
#define PORT_PB02B_ADC_AIN10 (1ul << 2)
|
||||
#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
|
||||
#define MUX_PB03B_ADC_AIN11 1L
|
||||
#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
|
||||
#define PORT_PB03B_ADC_AIN11 (1ul << 3)
|
||||
#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
|
||||
#define MUX_PB04B_ADC_AIN12 1L
|
||||
#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
|
||||
#define PORT_PB04B_ADC_AIN12 (1ul << 4)
|
||||
#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
|
||||
#define MUX_PA08B_ADC_AIN16 1L
|
||||
#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
|
||||
#define PORT_PA08B_ADC_AIN16 (1ul << 8)
|
||||
#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
|
||||
#define MUX_PA09B_ADC_AIN17 1L
|
||||
#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
|
||||
#define PORT_PA09B_ADC_AIN17 (1ul << 9)
|
||||
#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
|
||||
#define MUX_PA10B_ADC_AIN18 1L
|
||||
#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
|
||||
#define PORT_PA10B_ADC_AIN18 (1ul << 10)
|
||||
#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
|
||||
#define MUX_PA11B_ADC_AIN19 1L
|
||||
#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
|
||||
#define PORT_PA11B_ADC_AIN19 (1ul << 11)
|
||||
#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
|
||||
#define MUX_PA04B_ADC_VREFP 1L
|
||||
#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
|
||||
#define PORT_PA04B_ADC_VREFP (1ul << 4)
|
||||
/* ========== PORT definition for AC peripheral ========== */
|
||||
#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
|
||||
#define MUX_PA04B_AC_AIN0 1L
|
||||
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
||||
#define PORT_PA04B_AC_AIN0 (1ul << 4)
|
||||
#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
|
||||
#define MUX_PA05B_AC_AIN1 1L
|
||||
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
||||
#define PORT_PA05B_AC_AIN1 (1ul << 5)
|
||||
#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
|
||||
#define MUX_PA06B_AC_AIN2 1L
|
||||
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
||||
#define PORT_PA06B_AC_AIN2 (1ul << 6)
|
||||
#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
|
||||
#define MUX_PA07B_AC_AIN3 1L
|
||||
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
||||
#define PORT_PA07B_AC_AIN3 (1ul << 7)
|
||||
#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
|
||||
#define MUX_PA12H_AC_CMP0 7L
|
||||
#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
|
||||
#define PORT_PA12H_AC_CMP0 (1ul << 12)
|
||||
#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
|
||||
#define MUX_PA18H_AC_CMP0 7L
|
||||
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
|
||||
#define PORT_PA18H_AC_CMP0 (1ul << 18)
|
||||
#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
|
||||
#define MUX_PA13H_AC_CMP1 7L
|
||||
#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
|
||||
#define PORT_PA13H_AC_CMP1 (1ul << 13)
|
||||
#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
|
||||
#define MUX_PA19H_AC_CMP1 7L
|
||||
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
|
||||
#define PORT_PA19H_AC_CMP1 (1ul << 19)
|
||||
/* ========== PORT definition for DAC peripheral ========== */
|
||||
#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
|
||||
#define MUX_PA02B_DAC_VOUT 1L
|
||||
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
|
||||
#define PORT_PA02B_DAC_VOUT (1ul << 2)
|
||||
#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
|
||||
#define MUX_PA03B_DAC_VREFP 1L
|
||||
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
|
||||
#define PORT_PA03B_DAC_VREFP (1ul << 3)
|
||||
/* ========== PORT definition for I2S peripheral ========== */
|
||||
#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
|
||||
#define MUX_PA11G_I2S_FS0 6L
|
||||
#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
|
||||
#define PORT_PA11G_I2S_FS0 (1ul << 11)
|
||||
#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
|
||||
#define MUX_PA21G_I2S_FS0 6L
|
||||
#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
|
||||
#define PORT_PA21G_I2S_FS0 (1ul << 21)
|
||||
#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
|
||||
#define MUX_PA09G_I2S_MCK0 6L
|
||||
#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
|
||||
#define PORT_PA09G_I2S_MCK0 (1ul << 9)
|
||||
#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
|
||||
#define MUX_PA10G_I2S_SCK0 6L
|
||||
#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
|
||||
#define PORT_PA10G_I2S_SCK0 (1ul << 10)
|
||||
#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
|
||||
#define MUX_PA20G_I2S_SCK0 6L
|
||||
#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
|
||||
#define PORT_PA20G_I2S_SCK0 (1ul << 20)
|
||||
#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
|
||||
#define MUX_PA07G_I2S_SD0 6L
|
||||
#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
|
||||
#define PORT_PA07G_I2S_SD0 (1ul << 7)
|
||||
#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
|
||||
#define MUX_PA19G_I2S_SD0 6L
|
||||
#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
|
||||
#define PORT_PA19G_I2S_SD0 (1ul << 19)
|
||||
#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
|
||||
#define MUX_PA08G_I2S_SD1 6L
|
||||
#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
|
||||
#define PORT_PA08G_I2S_SD1 (1ul << 8)
|
||||
|
||||
#endif /* _SAMD21G18AU_PIO_ */
|
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Reference in New Issue