993 lines
34 KiB
C
993 lines
34 KiB
C
/**
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* \file
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*
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* \brief SAM SystemControl
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAME54_SystemControl_COMPONENT_
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#ifndef _HRI_SystemControl_E54_H_INCLUDED_
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#define _HRI_SystemControl_E54_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
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#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define SystemControl_CRITICAL_SECTION_ENTER()
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#define SystemControl_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_systemcontrol_actlr_reg_t;
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typedef uint32_t hri_systemcontrol_adr_reg_t;
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typedef uint32_t hri_systemcontrol_afsr_reg_t;
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typedef uint32_t hri_systemcontrol_aircr_reg_t;
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typedef uint32_t hri_systemcontrol_bfar_reg_t;
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typedef uint32_t hri_systemcontrol_ccr_reg_t;
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typedef uint32_t hri_systemcontrol_cfsr_reg_t;
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typedef uint32_t hri_systemcontrol_cpacr_reg_t;
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typedef uint32_t hri_systemcontrol_cpuid_reg_t;
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typedef uint32_t hri_systemcontrol_dfr_reg_t;
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typedef uint32_t hri_systemcontrol_dfsr_reg_t;
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typedef uint32_t hri_systemcontrol_hfsr_reg_t;
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typedef uint32_t hri_systemcontrol_icsr_reg_t;
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typedef uint32_t hri_systemcontrol_ictr_reg_t;
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typedef uint32_t hri_systemcontrol_isar_reg_t;
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typedef uint32_t hri_systemcontrol_mmfar_reg_t;
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typedef uint32_t hri_systemcontrol_mmfr_reg_t;
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typedef uint32_t hri_systemcontrol_pfr_reg_t;
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typedef uint32_t hri_systemcontrol_scr_reg_t;
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typedef uint32_t hri_systemcontrol_shcsr_reg_t;
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typedef uint32_t hri_systemcontrol_shpr1_reg_t;
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typedef uint32_t hri_systemcontrol_shpr2_reg_t;
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typedef uint32_t hri_systemcontrol_shpr3_reg_t;
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typedef uint32_t hri_systemcontrol_vtor_reg_t;
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static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_get_ICTR_INTLINESNUM_bf(const void *const hw,
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hri_systemcontrol_ictr_reg_t mask)
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{
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return (((Systemcontrol *)hw)->ICTR.reg & SystemControl_ICTR_INTLINESNUM(mask)) >> 0;
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}
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static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_read_ICTR_INTLINESNUM_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->ICTR.reg & SystemControl_ICTR_INTLINESNUM_Msk) >> 0;
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}
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static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_get_ICTR_reg(const void *const hw,
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hri_systemcontrol_ictr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->ICTR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_read_ICTR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->ICTR.reg;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_CONSTANT_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_CONSTANT(mask)) >> 16;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_CONSTANT_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_CONSTANT_Msk) >> 16;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20;
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}
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static inline hri_systemcontrol_cpuid_reg_t
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hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
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{
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return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw,
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hri_systemcontrol_cpuid_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->CPUID.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->CPUID.reg;
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}
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static inline hri_systemcontrol_dfr_reg_t hri_systemcontrol_get_DFR_reg(const void *const hw,
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hri_systemcontrol_dfr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->DFR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_dfr_reg_t hri_systemcontrol_read_DFR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->DFR.reg;
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}
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static inline hri_systemcontrol_adr_reg_t hri_systemcontrol_get_ADR_reg(const void *const hw,
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hri_systemcontrol_adr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->ADR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_adr_reg_t hri_systemcontrol_read_ADR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->ADR.reg;
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}
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static inline hri_systemcontrol_mmfr_reg_t hri_systemcontrol_get_MMFR_reg(const void *const hw, uint8_t index,
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hri_systemcontrol_mmfr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->MMFR[index].reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_mmfr_reg_t hri_systemcontrol_read_MMFR_reg(const void *const hw, uint8_t index)
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{
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return ((Systemcontrol *)hw)->MMFR[index].reg;
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}
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static inline hri_systemcontrol_isar_reg_t hri_systemcontrol_get_ISAR_reg(const void *const hw, uint8_t index,
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hri_systemcontrol_isar_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->ISAR[index].reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_systemcontrol_isar_reg_t hri_systemcontrol_read_ISAR_reg(const void *const hw, uint8_t index)
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{
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return ((Systemcontrol *)hw)->ISAR[index].reg;
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}
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static inline void hri_systemcontrol_set_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ACTLR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_actlr_reg_t hri_systemcontrol_get_ACTLR_reg(const void *const hw,
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hri_systemcontrol_actlr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->ACTLR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ACTLR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ACTLR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ACTLR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_actlr_reg_t hri_systemcontrol_read_ACTLR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->ACTLR.reg;
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}
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static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw,
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hri_systemcontrol_icsr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->ICSR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->ICSR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->ICSR.reg;
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}
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static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw,
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hri_systemcontrol_vtor_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->VTOR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->VTOR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->VTOR.reg;
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}
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static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw,
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hri_systemcontrol_aircr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->AIRCR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->AIRCR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->AIRCR.reg;
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}
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static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg |= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw,
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hri_systemcontrol_scr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Systemcontrol *)hw)->SCR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg = data;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg &= ~mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
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((Systemcontrol *)hw)->SCR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
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{
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return ((Systemcontrol *)hw)->SCR.reg;
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}
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static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
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{
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SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CCR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw,
|
|
hri_systemcontrol_ccr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->CCR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CCR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CCR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CCR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->CCR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR1.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shpr1_reg_t hri_systemcontrol_get_SHPR1_reg(const void *const hw,
|
|
hri_systemcontrol_shpr1_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->SHPR1.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR1.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR1.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR1.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shpr1_reg_t hri_systemcontrol_read_SHPR1_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->SHPR1.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR2.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw,
|
|
hri_systemcontrol_shpr2_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->SHPR2.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR2.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR2.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->SHPR2.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR3.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw,
|
|
hri_systemcontrol_shpr3_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->SHPR3.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR3.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHPR3.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->SHPR3.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHCSR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw,
|
|
hri_systemcontrol_shcsr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->SHCSR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHCSR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHCSR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->SHCSR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->SHCSR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CFSR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_cfsr_reg_t hri_systemcontrol_get_CFSR_reg(const void *const hw,
|
|
hri_systemcontrol_cfsr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->CFSR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CFSR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CFSR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CFSR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_cfsr_reg_t hri_systemcontrol_read_CFSR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->CFSR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->HFSR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_hfsr_reg_t hri_systemcontrol_get_HFSR_reg(const void *const hw,
|
|
hri_systemcontrol_hfsr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->HFSR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->HFSR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->HFSR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->HFSR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_hfsr_reg_t hri_systemcontrol_read_HFSR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->HFSR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->DFSR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw,
|
|
hri_systemcontrol_dfsr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->DFSR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->DFSR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->DFSR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->DFSR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->DFSR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->MMFAR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_mmfar_reg_t hri_systemcontrol_get_MMFAR_reg(const void *const hw,
|
|
hri_systemcontrol_mmfar_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->MMFAR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->MMFAR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->MMFAR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->MMFAR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_mmfar_reg_t hri_systemcontrol_read_MMFAR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->MMFAR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->BFAR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_bfar_reg_t hri_systemcontrol_get_BFAR_reg(const void *const hw,
|
|
hri_systemcontrol_bfar_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->BFAR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->BFAR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->BFAR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->BFAR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_bfar_reg_t hri_systemcontrol_read_BFAR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->BFAR.reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->AFSR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_afsr_reg_t hri_systemcontrol_get_AFSR_reg(const void *const hw,
|
|
hri_systemcontrol_afsr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->AFSR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->AFSR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->AFSR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
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((Systemcontrol *)hw)->AFSR.reg ^= mask;
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SystemControl_CRITICAL_SECTION_LEAVE();
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}
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|
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static inline hri_systemcontrol_afsr_reg_t hri_systemcontrol_read_AFSR_reg(const void *const hw)
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|
{
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return ((Systemcontrol *)hw)->AFSR.reg;
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|
}
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|
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static inline void hri_systemcontrol_set_PFR_reg(const void *const hw, uint8_t index, hri_systemcontrol_pfr_reg_t mask)
|
|
{
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|
SystemControl_CRITICAL_SECTION_ENTER();
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|
((Systemcontrol *)hw)->PFR[index].reg |= mask;
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|
SystemControl_CRITICAL_SECTION_LEAVE();
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|
}
|
|
|
|
static inline hri_systemcontrol_pfr_reg_t hri_systemcontrol_get_PFR_reg(const void *const hw, uint8_t index,
|
|
hri_systemcontrol_pfr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
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|
tmp = ((Systemcontrol *)hw)->PFR[index].reg;
|
|
tmp &= mask;
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|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_PFR_reg(const void *const hw, uint8_t index,
|
|
hri_systemcontrol_pfr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->PFR[index].reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_PFR_reg(const void *const hw, uint8_t index,
|
|
hri_systemcontrol_pfr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->PFR[index].reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_PFR_reg(const void *const hw, uint8_t index,
|
|
hri_systemcontrol_pfr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->PFR[index].reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_pfr_reg_t hri_systemcontrol_read_PFR_reg(const void *const hw, uint8_t index)
|
|
{
|
|
return ((Systemcontrol *)hw)->PFR[index].reg;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_set_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CPACR.reg |= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_cpacr_reg_t hri_systemcontrol_get_CPACR_reg(const void *const hw,
|
|
hri_systemcontrol_cpacr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Systemcontrol *)hw)->CPACR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_systemcontrol_write_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t data)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CPACR.reg = data;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_clear_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CPACR.reg &= ~mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_systemcontrol_toggle_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask)
|
|
{
|
|
SystemControl_CRITICAL_SECTION_ENTER();
|
|
((Systemcontrol *)hw)->CPACR.reg ^= mask;
|
|
SystemControl_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_systemcontrol_cpacr_reg_t hri_systemcontrol_read_CPACR_reg(const void *const hw)
|
|
{
|
|
return ((Systemcontrol *)hw)->CPACR.reg;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HRI_SystemControl_E54_H_INCLUDED */
|
|
#endif /* _SAME54_SystemControl_COMPONENT_ */
|