362 lines
10 KiB
C
362 lines
10 KiB
C
/**
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* \file
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*
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* \brief SAM CMCC
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAME54_CMCC_COMPONENT_
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#ifndef _HRI_CMCC_E54_H_INCLUDED_
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#define _HRI_CMCC_E54_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_CMCC_CRITICAL_SECTIONS)
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#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define CMCC_CRITICAL_SECTION_ENTER()
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#define CMCC_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_cmcc_cfg_reg_t;
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typedef uint32_t hri_cmcc_ctrl_reg_t;
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typedef uint32_t hri_cmcc_lckway_reg_t;
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typedef uint32_t hri_cmcc_maint0_reg_t;
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typedef uint32_t hri_cmcc_maint1_reg_t;
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typedef uint32_t hri_cmcc_mcfg_reg_t;
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typedef uint32_t hri_cmcc_mctrl_reg_t;
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typedef uint32_t hri_cmcc_men_reg_t;
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typedef uint32_t hri_cmcc_msr_reg_t;
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typedef uint32_t hri_cmcc_sr_reg_t;
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typedef uint32_t hri_cmcc_type_reg_t;
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static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos;
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}
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static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos;
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}
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static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw)
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{
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return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->TYPE.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->TYPE.reg;
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}
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static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw)
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{
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return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos;
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}
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static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->SR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->SR.reg;
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}
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static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask)
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{
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return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos;
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}
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static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw)
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{
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return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos;
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}
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static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->MSR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->MSR.reg;
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}
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static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->CFG.reg |= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->CFG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->CFG.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->CFG.reg &= ~mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->CFG.reg ^= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->CFG.reg;
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}
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static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->LCKWAY.reg |= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->LCKWAY.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->LCKWAY.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->LCKWAY.reg &= ~mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->LCKWAY.reg ^= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->LCKWAY.reg;
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}
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static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MCFG.reg |= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->MCFG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MCFG.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MCFG.reg &= ~mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MCFG.reg ^= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->MCFG.reg;
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}
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static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MEN.reg |= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Cmcc *)hw)->MEN.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MEN.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MEN.reg &= ~mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MEN.reg ^= mask;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw)
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{
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return ((Cmcc *)hw)->MEN.reg;
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}
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static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->CTRL.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MAINT0.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MAINT1.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data)
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{
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CMCC_CRITICAL_SECTION_ENTER();
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((Cmcc *)hw)->MCTRL.reg = data;
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CMCC_CRITICAL_SECTION_LEAVE();
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HRI_CMCC_E54_H_INCLUDED */
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#endif /* _SAME54_CMCC_COMPONENT_ */
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