356 lines
16 KiB
C
356 lines
16 KiB
C
/* Auto-generated config file hpl_usb_config.h */
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#ifndef HPL_USB_CONFIG_H
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#define HPL_USB_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#define CONF_USB_N_0 0
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#define CONF_USB_N_1 1
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#define CONF_USB_N_2 2
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#define CONF_USB_N_3 3
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#define CONF_USB_N_4 4
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#define CONF_USB_N_5 5
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#define CONF_USB_N_6 6
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#define CONF_USB_N_7 7
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#define CONF_USB_N_8 8
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#define CONF_USB_N_9 9
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#define CONF_USB_N_10 10
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#define CONF_USB_N_11 11
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#define CONF_USB_N_12 12
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#define CONF_USB_N_13 13
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#define CONF_USB_N_14 14
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#define CONF_USB_N_15 15
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#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1)
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#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1)
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// <h> USB Device HAL Configuration
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// <y> Max number of endpoints supported
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// <i> Limits the number of endpoints (described by EP address) can be used in app.
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// <CONF_USB_N_1"> 1 (EP0 only)
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// <CONF_USB_N_2"> 2 (EP0 + 1 endpoint)
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// <CONF_USB_N_3"> 3 (EP0 + 2 endpoints)
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// <CONF_USB_N_4"> 4 (EP0 + 3 endpoints)
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// <CONF_USB_N_5"> 5 (EP0 + 4 endpoints)
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// <CONF_USB_N_6"> 6 (EP0 + 5 endpoints)
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// <CONF_USB_N_7"> 7 (EP0 + 6 endpoints)
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// <CONF_USB_N_8"> 8 (EP0 + 7 endpoints)
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// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config)
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// <id> usbd_num_ep_sp
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#ifndef CONF_USB_D_NUM_EP_SP
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#define CONF_USB_D_NUM_EP_SP CONF_USB_N_1
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#endif
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// </h>
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// <y> Max Endpoint Number supported
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// <i> Limits the max endpoint number.
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// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1.
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// <i> Reduce the value according to specific device design, to cut-off memory usage.
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// <CONF_USB_N_0"> 0 (only EP0)
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// <CONF_USB_N_1"> 1 (EP 0x81 or 0x01)
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// <CONF_USB_N_2"> 2 (EP 0x82 or 0x02)
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// <CONF_USB_N_3"> 3 (EP 0x83 or 0x03)
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// <CONF_USB_N_4"> 4 (EP 0x84 or 0x04)
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// <CONF_USB_N_5"> 5 (EP 0x85 or 0x05)
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// <CONF_USB_N_6"> 6 (EP 0x86 or 0x06)
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// <CONF_USB_N_7"> 7 (EP 0x87 or 0x07)
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// <CONF_USB_EP_N_MAX"> Max possible (by HW)
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// <i> The number of physical endpoints - 1
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// <id> usbd_arch_max_ep_n
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#ifndef CONF_USB_D_MAX_EP_N
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#define CONF_USB_D_MAX_EP_N CONF_USB_N_0
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#endif
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// <y> USB Speed Limit
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// <i> Limits the working speed of the device.
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// <USB_SPEED_FS"> Full speed
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// <USB_SPEED_LS"> Low Speed
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// <id> usbd_arch_speed
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#ifndef CONF_USB_D_SPEED
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#define CONF_USB_D_SPEED USB_SPEED_FS
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#endif
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// <o> Cache buffer size for EP0
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time.
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <id> usb_arch_ep0_cache
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#ifndef CONF_USB_EP0_CACHE
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#define CONF_USB_EP0_CACHE 64
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#endif
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// <h> Cache configuration EP1
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// <o> Cache buffer size for EP1 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep1_cache
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#ifndef CONF_USB_EP1_CACHE
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#define CONF_USB_EP1_CACHE 64
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#endif
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// <o> Cache buffer size for EP1 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep1_I_CACHE
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#ifndef CONF_USB_EP1_I_CACHE
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#define CONF_USB_EP1_I_CACHE 0
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#endif
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// </h>
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// <h> Cache configuration EP2
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// <o> Cache buffer size for EP2 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep2_cache
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#ifndef CONF_USB_EP2_CACHE
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#define CONF_USB_EP2_CACHE 64
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#endif
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// <o> Cache buffer size for EP2 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep2_I_CACHE
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#ifndef CONF_USB_EP2_I_CACHE
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#define CONF_USB_EP2_I_CACHE 0
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#endif
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// </h>
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// <h> Cache configuration EP3
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// <o> Cache buffer size for EP3 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep3_cache
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#ifndef CONF_USB_EP3_CACHE
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#define CONF_USB_EP3_CACHE 64
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#endif
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// <o> Cache buffer size for EP3 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep3_I_CACHE
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#ifndef CONF_USB_EP3_I_CACHE
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#define CONF_USB_EP3_I_CACHE 0
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#endif
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// </h>
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// <h> Cache configuration EP4
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// <o> Cache buffer size for EP4 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep4_cache
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#ifndef CONF_USB_EP4_CACHE
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#define CONF_USB_EP4_CACHE 64
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#endif
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// <o> Cache buffer size for EP4 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep4_I_CACHE
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#ifndef CONF_USB_EP4_I_CACHE
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#define CONF_USB_EP4_I_CACHE 0
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#endif
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// </h>
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// <h> Cache configuration EP5
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// <o> Cache buffer size for EP5 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep5_cache
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#ifndef CONF_USB_EP5_CACHE
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#define CONF_USB_EP5_CACHE 64
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#endif
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// <o> Cache buffer size for EP5 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep5_I_CACHE
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#ifndef CONF_USB_EP5_I_CACHE
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#define CONF_USB_EP5_I_CACHE 0
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#endif
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// </h>
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// <h> Cache configuration EP6
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// <o> Cache buffer size for EP6 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep6_cache
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#ifndef CONF_USB_EP6_CACHE
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#define CONF_USB_EP6_CACHE 64
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#endif
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// <o> Cache buffer size for EP6 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep6_I_CACHE
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#ifndef CONF_USB_EP6_I_CACHE
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#define CONF_USB_EP6_I_CACHE 0
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#endif
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// </h>
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// <h> Cache configuration EP7
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// <o> Cache buffer size for EP7 OUT
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_arch_ep7_cache
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#ifndef CONF_USB_EP7_CACHE
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#define CONF_USB_EP7_CACHE 64
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#endif
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// <o> Cache buffer size for EP7 IN
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// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
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// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
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// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
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// <0=> No cache
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// <8=> Cached by 8 bytes buffer
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// <16=> Cached by 16 bytes buffer
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// <32=> Cached by 32 bytes buffer
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// <64=> Cached by 64 bytes buffer
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// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
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// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
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// <id> usb_ep7_I_CACHE
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#ifndef CONF_USB_EP7_I_CACHE
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#define CONF_USB_EP7_I_CACHE 0
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#endif
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// </h>
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// <<< end of configuration section >>>
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#endif // HPL_USB_CONFIG_H
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