212 lines
6.1 KiB
C
212 lines
6.1 KiB
C
/**
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* @defgroup bkp_defines BKP Defines
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* @ingroup STM32F1xx_defines
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* @brief <b>Defined Constants and Types for the Backup Registers</b>
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*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_BKP_H
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#define LIBOPENCM3_BKP_H
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/** @defgroup BKP_registers BKP Registers
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* @ingroup bkp_defines
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@{*/
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/* Backup data register 1 (BKP_DR1) */
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#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04)
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/* Backup data register 2 (BKP_DR2) */
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#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08)
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/* Backup data register 3 (BKP_DR3) */
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#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C)
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/* Backup data register 4 (BKP_DR4) */
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#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10)
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/* Backup data register 5 (BKP_DR5) */
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#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14)
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/* Backup data register 6 (BKP_DR6) */
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#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18)
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/* Backup data register 7 (BKP_DR7) */
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#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C)
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/* Backup data register 8 (BKP_DR8) */
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#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20)
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/* Backup data register 9 (BKP_DR9) */
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#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24)
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/* Backup data register 10 (BKP_DR10) */
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#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28)
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/** RTC clock calibration register (BKP_RTCCR) */
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#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C)
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/** Backup control register (BKP_CR) */
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#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30)
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/** Backup control/status register (BKP_CSR) */
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#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34)
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/* Backup data register 11 (BKP_DR11) */
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#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40)
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/* Backup data register 12 (BKP_DR12) */
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#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44)
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/* Backup data register 13 (BKP_DR13) */
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#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48)
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/* Backup data register 14 (BKP_DR14) */
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#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C)
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/* Backup data register 15 (BKP_DR15) */
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#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50)
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/* Backup data register 16 (BKP_DR16) */
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#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54)
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/* Backup data register 17 (BKP_DR17) */
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#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58)
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/* Backup data register 18 (BKP_DR18) */
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#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C)
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/* Backup data register 19 (BKP_DR19) */
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#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60)
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/* Backup data register 20 (BKP_DR20) */
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#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64)
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/* Backup data register 21 (BKP_DR21) */
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#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68)
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/* Backup data register 22 (BKP_DR22) */
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#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C)
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/* Backup data register 23 (BKP_DR23) */
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#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70)
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/* Backup data register 24 (BKP_DR24) */
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#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74)
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/* Backup data register 25 (BKP_DR25) */
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#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78)
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/* Backup data register 26 (BKP_DR26) */
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#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C)
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/* Backup data register 27 (BKP_DR27) */
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#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80)
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/* Backup data register 28 (BKP_DR28) */
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#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84)
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/* Backup data register 29 (BKP_DR29) */
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#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88)
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/* Backup data register 30 (BKP_DR30) */
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#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C)
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/* Backup data register 31 (BKP_DR31) */
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#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90)
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/* Backup data register 32 (BKP_DR32) */
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#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94)
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/* Backup data register 33 (BKP_DR33) */
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#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98)
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/* Backup data register 34 (BKP_DR34) */
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#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C)
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/* Backup data register 35 (BKP_DR35) */
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#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0)
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/* Backup data register 36 (BKP_DR36) */
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#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4)
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/* Backup data register 37 (BKP_DR37) */
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#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8)
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/* Backup data register 38 (BKP_DR38) */
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#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC)
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/* Backup data register 39 (BKP_DR39) */
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#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0)
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/* Backup data register 40 (BKP_DR40) */
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#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4)
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/* Backup data register 41 (BKP_DR41) */
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#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8)
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/* Backup data register 42 (BKP_DR42) */
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#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC)
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/*@}*/
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/** @defgroup BKP_RTCCR_Values BKP_RTCCR Values
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* @ingroup bkp_defines
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@{*/
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/** ASOS: Alarm or second output selection */
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#define BKP_RTCCR_ASOS (1 << 9)
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/** ASOE: Alarm or second output enable */
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#define BKP_RTCCR_ASOE (1 << 8)
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/** CCO: Calibration clock output */
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#define BKP_RTCCR_CCO (1 << 7)
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/** CAL[6:0]: Calibration value */
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#define BKP_RTCCR_CAL_LSB 0
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/*@}*/
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/** @defgroup BKP_CR_Values BKP_CR Values
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* @ingroup bkp_defines
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@{*/
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/** TPAL: TAMPER pin active level */
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#define BKP_CR_TPAL (1 << 1)
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/** TPE: TAMPER pin enable */
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#define BKP_CR_TPE (1 << 0)
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/*@}*/
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/** @defgroup BKP_CSR_Values BKP_CSR Values
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* @ingroup bkp_defines
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@{*/
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/** TIF: Tamper interrupt flag */
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#define BKP_CSR_TIF (1 << 9)
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/** TEF: Tamper event flag */
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#define BKP_CSR_TEF (1 << 8)
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/** TPIE: TAMPER pin interrupt enable */
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#define BKP_CSR_TPIE (1 << 2)
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/** CTI: Clear tamper interrupt */
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#define BKP_CSR_CTI (1 << 1)
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/** CTE: Clear tamper event */
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#define BKP_CSR_CTE (1 << 0)
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/*@}*/
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#endif
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