124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/** @addtogroup iwdg_defines
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H
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The order of header inclusion is important. iwdg.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_IWDG_H
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/** @endcond */
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#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H
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#define LIBOPENCM3_IWDG_COMMON_ALL_H
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/* --- IWDG registers ------------------------------------------------------ */
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/* Key Register (IWDG_KR) */
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#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
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/* Prescaler register (IWDG_PR) */
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#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
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/* Reload register (IWDG_RLR) */
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#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
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/* Status register (IWDG_SR) */
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#define IWDG_SR MMIO32(IWDG_BASE + 0x0c)
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/* --- IWDG_KR values ------------------------------------------------------ */
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/* Bits [31:16]: Reserved. */
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/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
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/** @defgroup iwdg_key IWDG Key Values
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@ingroup STM32F_iwdg_defines
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@{*/
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#define IWDG_KR_RESET 0xaaaa
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#define IWDG_KR_UNLOCK 0x5555
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#define IWDG_KR_START 0xcccc
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/**@}*/
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/* --- IWDG_PR values ------------------------------------------------------ */
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/* Bits [31:3]: Reserved. */
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/* PR[2:0]: Prescaler divider */
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#define IWDG_PR_LSB 0
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/** @defgroup iwdg_prediv IWDG Prescaler divider
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@ingroup STM32F_iwdg_defines
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@{*/
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#define IWDG_PR_DIV4 0x0
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#define IWDG_PR_DIV8 0x1
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#define IWDG_PR_DIV16 0x2
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#define IWDG_PR_DIV32 0x3
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#define IWDG_PR_DIV64 0x4
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#define IWDG_PR_DIV128 0x5
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#define IWDG_PR_DIV256 0x6
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/**@}*/
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/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
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/* #define IWDG_PR_DIV256 0x7 */
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/* --- IWDG_RLR values ----------------------------------------------------- */
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/* Bits [31:12]: Reserved. */
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/* RL[11:0]: Watchdog counter reload value */
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/* --- IWDG_SR values ------------------------------------------------------ */
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/* Bits [31:2]: Reserved. */
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/* RVU: Watchdog counter reload value update */
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#define IWDG_SR_RVU (1 << 1)
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/* PVU: Watchdog prescaler value update */
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#define IWDG_SR_PVU (1 << 0)
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/* --- IWDG function prototypes---------------------------------------------- */
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BEGIN_DECLS
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void iwdg_start(void);
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void iwdg_set_period_ms(u32 period);
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bool iwdg_reload_busy(void);
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bool iwdg_prescaler_busy(void);
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void iwdg_reset(void);
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END_DECLS
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#endif
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/** @cond */
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#else
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#warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h"
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#endif
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/** @endcond */
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/**@}*/
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