490 lines
12 KiB
C
490 lines
12 KiB
C
/** @addtogroup i2c_file
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/i2c.h>
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#include <libopencm3/stm32/rcc.h>
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/**@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Reset.
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*
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* The I2C peripheral and all its associated configuration registers are placed
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* in the reset condition. The reset is effected via the RCC peripheral reset
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* system.
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*
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* @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
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*/
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void i2c_reset(uint32_t i2c)
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{
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switch (i2c) {
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case I2C1:
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rcc_periph_reset_pulse(RST_I2C1);
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break;
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#if defined(I2C2_BASE)
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case I2C2:
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rcc_periph_reset_pulse(RST_I2C2);
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break;
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#endif
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#if defined(I2C3_BASE)
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case I2C3:
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rcc_periph_reset_pulse(RST_I2C3);
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break;
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#endif
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#if defined(I2C4_BASE)
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case I2C4:
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rcc_periph_reset_pulse(RST_I2C4);
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break;
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#endif
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default:
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Peripheral Enable.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_peripheral_enable(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_PE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Peripheral Disable.
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*
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* This must not be reset while in Master mode until a communication has
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* finished. In Slave mode, the peripheral is disabled only after communication
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* has ended.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_peripheral_disable(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_PE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Start Condition.
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*
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* If in Master mode this will cause a restart condition to occur at the end of
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* the current transmission. If in Slave mode, this will initiate a start
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* condition when the current bus activity is completed.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_send_start(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_START;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Stop Condition.
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*
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* After the current byte transfer this will initiate a stop condition if in
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* Master mode, or simply release the bus if in Slave mode.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_send_stop(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_STOP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Clear Stop Flag.
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*
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* Clear the "Send Stop" flag in the I2C config register
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_clear_stop(uint32_t i2c)
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{
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I2C_ICR(i2c) |= I2C_ICR_STOPCF;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
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*
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* This sets an address for Slave mode operation, in 7 bit form.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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* @param[in] slave Unsigned int8. Slave address 0...127.
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*/
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void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
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{
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I2C_OAR1(i2c) = (uint16_t)(slave << 1);
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I2C_OAR1(i2c) &= ~I2C_OAR1_OA1MODE;
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I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
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*
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* This sets an address for Slave mode operation, in 10 bit form.
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*
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* @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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* @param[in] slave Unsigned int16. Slave address 0...1023.
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*/
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void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
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{
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I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_OA1MODE | slave);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Data.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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* @param[in] data Unsigned int8. Byte to send.
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*/
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void i2c_send_data(uint32_t i2c, uint8_t data)
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{
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I2C_TXDR(i2c) = data;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Get Data.
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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uint8_t i2c_get_data(uint32_t i2c)
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{
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return I2C_RXDR(i2c) & 0xff;
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}
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void i2c_enable_analog_filter(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF;
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}
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void i2c_disable_analog_filter(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_ANFOFF;
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}
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void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting)
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{
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I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting;
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}
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/* t_presc= (presc+1)*t_i2cclk */
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void i2c_set_prescaler(uint32_t i2c, uint8_t presc)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) |
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(presc << I2C_TIMINGR_PRESC_SHIFT);
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}
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void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) |
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(s_time << I2C_TIMINGR_SCLDEL_SHIFT);
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}
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void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) |
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(h_time << I2C_TIMINGR_SDADEL_SHIFT);
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}
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void i2c_set_scl_high_period(uint32_t i2c, uint8_t period)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) |
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(period << I2C_TIMINGR_SCLH_SHIFT);
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}
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void i2c_set_scl_low_period(uint32_t i2c, uint8_t period)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) |
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(period << I2C_TIMINGR_SCLL_SHIFT);
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}
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void i2c_enable_stretching(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH;
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}
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void i2c_disable_stretching(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH;
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}
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void i2c_100khz_i2cclk8mhz(uint32_t i2c)
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{
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i2c_set_prescaler(i2c, 1);
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i2c_set_scl_low_period(i2c, 0x13);
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i2c_set_scl_high_period(i2c, 0xF);
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i2c_set_data_hold_time(i2c, 0x2);
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i2c_set_data_setup_time(i2c, 0x4);
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}
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void i2c_set_7bit_addr_mode(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_ADD10;
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}
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void i2c_set_10bit_addr_mode(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_ADD10;
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}
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void i2c_set_7bit_address(uint32_t i2c, uint8_t addr)
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{
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I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) |
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((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT);
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}
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void i2c_set_10bit_address(uint32_t i2c, uint16_t addr)
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{
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I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) |
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((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT);
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}
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void i2c_set_write_transfer_dir(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN;
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}
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void i2c_set_read_transfer_dir(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_RD_WRN;
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}
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void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes)
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{
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I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) |
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(n_bytes << I2C_CR2_NBYTES_SHIFT);
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}
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uint8_t i2c_is_start(uint32_t i2c)
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{
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if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) {
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return 1;
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}
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return 0;
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}
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void i2c_enable_autoend(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_AUTOEND;
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}
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void i2c_disable_autoend(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND;
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}
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uint8_t i2c_nack(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) {
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return 1;
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}
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return 0;
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}
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uint8_t i2c_busy(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) {
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return 1;
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}
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return 0;
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}
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uint8_t i2c_transmit_int_status(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) {
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return 1;
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}
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return 0;
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}
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uint8_t i2c_transfer_complete(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) {
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return 1;
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}
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return 0;
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}
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uint8_t i2c_received_data(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) {
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return 1;
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}
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable Interrupt
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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* @param[in] interrupt Unsigned int32. Interrupt to enable.
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*/
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void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
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{
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I2C_CR1(i2c) |= interrupt;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable Interrupt
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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* @param[in] interrupt Unsigned int32. Interrupt to disable.
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*/
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void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
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{
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I2C_CR1(i2c) &= ~interrupt;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable reception DMA
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_rxdma(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_RXDMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable reception DMA
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_rxdma(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable transmission DMA
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_txdma(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_TXDMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable transmission DMA
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*
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* @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_txdma(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;
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}
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void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
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uint8_t *data)
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{
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int wait;
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int i;
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while (i2c_busy(i2c) == 1);
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while (i2c_is_start(i2c) == 1);
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/*Setting transfer properties*/
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i2c_set_bytes_to_transfer(i2c, size + 1);
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i2c_set_7bit_address(i2c, (i2c_addr & 0x7F));
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i2c_set_write_transfer_dir(i2c);
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i2c_enable_autoend(i2c);
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/*start transfer*/
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i2c_send_start(i2c);
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wait = true;
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while (wait) {
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if (i2c_transmit_int_status(i2c)) {
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wait = false;
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}
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while (i2c_nack(i2c));
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}
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i2c_send_data(i2c, reg);
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for (i = 0; i < size; i++) {
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wait = true;
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while (wait) {
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if (i2c_transmit_int_status(i2c)) {
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wait = false;
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}
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while (i2c_nack(i2c));
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}
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i2c_send_data(i2c, data[i]);
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}
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}
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void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
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uint8_t *data)
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{
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int wait;
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int i;
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while (i2c_busy(i2c) == 1);
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while (i2c_is_start(i2c) == 1);
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/*Setting transfer properties*/
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i2c_set_bytes_to_transfer(i2c, 1);
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i2c_set_7bit_address(i2c, i2c_addr);
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i2c_set_write_transfer_dir(i2c);
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i2c_disable_autoend(i2c);
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/*start transfer*/
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i2c_send_start(i2c);
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wait = true;
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while (wait) {
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if (i2c_transmit_int_status(i2c)) {
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wait = false;
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}
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while (i2c_nack(i2c)); /* Some error */
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}
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i2c_send_data(i2c, reg);
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while (i2c_is_start(i2c) == 1);
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/*Setting transfer properties*/
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i2c_set_bytes_to_transfer(i2c, size);
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i2c_set_7bit_address(i2c, i2c_addr);
|
|
i2c_set_read_transfer_dir(i2c);
|
|
i2c_enable_autoend(i2c);
|
|
/*start transfer*/
|
|
i2c_send_start(i2c);
|
|
|
|
for (i = 0; i < size; i++) {
|
|
while (i2c_received_data(i2c) == 0);
|
|
data[i] = i2c_get_data(i2c);
|
|
}
|
|
}
|
|
|
|
/**@}*/
|