295 lines
9.0 KiB
C
295 lines
9.0 KiB
C
/** @addtogroup lptimer_file LPTIM peripheral API
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* @ingroup peripheral_apis
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*
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* @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
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*
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* @date 2 July 2019
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*
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* LGPL License Terms @ref lgpl_license
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*
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* @section lptim_api_ex Basic LPTIMER handling API.
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*
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* Example: LPTIM1 with 2x clock prescaler, from internal clock (LSE), irq on match and reload.
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*
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* @code
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*
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* rcc_set_peripheral_clk_sel(LPTIM1, RCC_CCIPR_LPTIM1SEL_LSE);
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*
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* rcc_periph_clock_enable(RCC_LPTIM1);
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*
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* lptimer_set_internal_clock_source(LPTIM1);
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* lptimer_enable_trigger(LPTIM1, LPTIM_CFGR_TRIGEN_SW);
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* lptimer_set_prescaler(LPTIM1, LPTIM_CFGR_PRESC_2);
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*
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* lptimer_enable(LPTIM1);
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*
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* lptimer_set_period(LPTIM1, 0xffff);
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* lptimer_set_compare(LPTIM1, 1234);
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*
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* lptimer_enable_irq(LPTIM1, LPTIM_IER_ARRMIE | LPTIM_IER_CMPMIE);
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* nvic_enable_irq(NVIC_LPTIM1_IRQ);
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*
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* lptimer_start_counter(LPTIM1, LPTIM_CR_CNTSTRT);
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*
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* @endcode
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*
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* Note: LPTIM internal clock source selection is device specific, see clock tree
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* and rcc section of reference manual.
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/lptimer.h>
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/** @brief Set lptimer Counter
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*
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* Set the value of a lptimer counter.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] count Counter value.
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*/
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void lptimer_set_counter(uint32_t lptimer_peripheral, uint16_t count)
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{
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LPTIM_CNT(lptimer_peripheral) = count;
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}
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/** @brief Read lptimer Counter
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*
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* Read back the value of lptimer counter.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @returns Counter value.
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*/
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uint16_t lptimer_get_counter(uint32_t lptimer_peripheral)
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{
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return LPTIM_CNT(lptimer_peripheral);
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}
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/** @brief Clear lptimer Status Flag.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] flag Status Register clear flag (@ref lptim_icr)
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*/
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void lptimer_clear_flag(uint32_t lptimer_peripheral, uint32_t flag)
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{
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LPTIM_ICR(lptimer_peripheral) = flag;
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}
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/** @brief Read lptimer Status Flag.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] flag Status Register flag (@ref lptim_isr)
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* @returns flag set.
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*/
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bool lptimer_get_flag(uint32_t lptimer_peripheral, uint32_t flag)
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{
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return (LPTIM_ISR(lptimer_peripheral) & flag);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable lptimer interrupts.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] irq Logical or of all interrupt enable bits to be set (@ref lptim_ier)
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*/
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void lptimer_enable_irq(uint32_t lptimer_peripheral, uint32_t irq)
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{
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LPTIM_IER(lptimer_peripheral) |= irq;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable lptimer Interrupts.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] irq Logical or of all interrupt enable bits to be cleared (@ref lptim_ier)
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*/
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void lptimer_disable_irq(uint32_t lptimer_peripheral, uint32_t irq)
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{
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LPTIM_IER(lptimer_peripheral) &= ~irq;
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}
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/** @brief Enable lptimer.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_enable(uint32_t lptimer_peripheral)
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{
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LPTIM_CR(lptimer_peripheral) |= LPTIM_CR_ENABLE;
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}
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/** @brief Disable lptimer.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_disable(uint32_t lptimer_peripheral)
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{
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LPTIM_CR(lptimer_peripheral) &= ~LPTIM_CR_ENABLE;
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}
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/** @brief Start lptimer in a given mode.
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*
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* Starts the timer in specified mode - Either Single (@ref LPTIM_CR_SNGSTRT) or
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* Continuous mode (@ref LPTIM_CR_CNTSTRT). In Single mode, the timer will stop at
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* next match on compare or period value.
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* If LPTIM_CR_SNGSTRT is set while timer is started in countious mode, it
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* will stop at next match on compare or period value.
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* If Software trigger is disabled, start will be delayed until programmed
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* triggers is detected.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] mode lptimer start mode (@ref LPTIM_CR_SNGSTRT or @ref LPTIM_CR_CNTSTRT)
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*/
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void lptimer_start_counter(uint32_t lptimer_peripheral, uint32_t mode)
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{
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LPTIM_CR(lptimer_peripheral) |= mode;
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}
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/** @brief Set lptimer clock prescaler.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] prescaler Clock prescaler (@ref lptim_cfgr_presc)
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*/
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void lptimer_set_prescaler(uint32_t lptimer_peripheral, uint32_t prescaler)
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{
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uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral);
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reg32 &= ~(LPTIM_CFGR_PRESC_MASK << LPTIM_CFGR_PRESC_SHIFT);
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LPTIM_CFGR(lptimer_peripheral) = reg32 | prescaler;
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}
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/** @brief Enable lptimer External Trigger
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] trigen Enable Trigger
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*/
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void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen)
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{
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uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral);
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reg32 &= ~(LPTIM_CFGR_TRIGEN_MASK << LPTIM_CFGR_TRIGEN_SHIFT);
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LPTIM_CFGR(lptimer_peripheral) = reg32 | trigen;
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}
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/** @brief Select lptimer Trigger Source
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*
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* Select timer external trigger source.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] trigger_source Trigger selector (@ref lptim_cfgr_trigsel)
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*/
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void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source)
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{
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uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral);
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reg32 &= ~(LPTIM_CFGR_TRIGSEL_MASK << LPTIM_CFGR_TRIGSEL_SHIFT);
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LPTIM_CFGR(lptimer_peripheral) = reg32 | trigger_source;
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}
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/** @brief Set lptimer counter Compare Value
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*
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* Set the timer compare value. Must only be set with timer enabled.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] compare_value Compare value.
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*/
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void lptimer_set_compare(uint32_t lptimer_peripheral, uint16_t compare_value)
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{
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LPTIM_CMP(lptimer_peripheral) = compare_value;
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}
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/** @brief Set lptimer period
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*
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* Set the timer period in the auto-reload register. Must only be set with timer
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* enabled.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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* @param[in] period_value Autoreload value. Must be greater that CMP value.
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*/
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void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value)
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{
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LPTIM_ARR(lptimer_peripheral) = period_value;
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}
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/** @brief Enable lptimer Preload mode.
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*
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* Enable lptimer preload mode, delaying update of period and compare registers
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* to the end of current period.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_enable_preload(uint32_t lptimer_peripheral)
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{
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LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_PRELOAD;
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}
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/** @brief Disable lptimer Preload mode.
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*
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* Disable lptimer preload mode, ensureing updated period and compare registers
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* values are taken in account immediatly.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_disable_preload(uint32_t lptimer_peripheral)
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{
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LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_PRELOAD;
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}
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/** @brief Set lptimer Internal Clock source
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_set_internal_clock_source(uint32_t lptimer_peripheral)
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{
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LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_CKSEL;
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}
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/** @brief Set lptimer External Clock source
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_set_external_clock_source(uint32_t lptimer_peripheral)
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{
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LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_CKSEL;
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}
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/** @brief Set lptimer Waveform Output Polarity High
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*
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* Set lptimer waveform output to reflect compare result between LPTIN_CNT
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* and LPTIM_CMP.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral)
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{
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LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_WAVPOL;
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}
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/** @brief Set lptimer Waveform Output Polarity Low
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*
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* Set lptimer waveform output to reflect the inverse of the compare result
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* between LPTIN_CNT and LPTIM_CMP.
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*
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* @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
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*/
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void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral)
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{
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LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_WAVPOL;
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}
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/**@}*/
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