409 lines
14 KiB
C
409 lines
14 KiB
C
/** @file
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@ingroup STM32L1xx
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@brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
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@date 18 May 2012
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LGPL License Terms @ref lgpl_license
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*/
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/** @defgroup STM32L1xx_rcc_defines
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@brief Defined Constants and Types for the STM32L1xx Reset and Clock Control
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@ingroup STM32L1xx_defines
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*
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* Originally based on the F1 code, as it seemed most similar to the L1
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* TODO: very incomplete still!
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*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
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#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)
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#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)
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#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)
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#define RCC_CSR MMIO32(RCC_BASE + 0x34)
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/* --- RCC_CR values ------------------------------------------------------- */
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/* RTCPRE[1:0] at 30:29 */
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#define RCC_CR_CSSON (1 << 28)
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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#define RCC_CR_MSIRDY (1 << 9)
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#define RCC_CR_MSION (1 << 8)
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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#define RCC_CR_RTCPRE_DIV2 0
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#define RCC_CR_RTCPRE_DIV4 1
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#define RCC_CR_RTCPRE_DIV8 2
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#define RCC_CR_RTCPRE_DIV18 3
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/* --- RCC_ICSCR values ---------------------------------------------------- */
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// TODO
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/* --- RCC_CFGR values ----------------------------------------------------- */
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/* MCOPRE */
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#define RCC_CFGR_MCOPRE_DIV1 0
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#define RCC_CFGR_MCOPRE_DIV2 1
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#define RCC_CFGR_MCOPRE_DIV4 2
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#define RCC_CFGR_MCOPRE_DIV8 3
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#define RCC_CFGR_MCOPRE_DIV16 4
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/* MCO: Microcontroller clock output */
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#define RCC_CFGR_MCO_NOCLK 0x0
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#define RCC_CFGR_MCO_SYSCLK 0x1
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#define RCC_CFGR_MCO_HSICLK 0x2
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#define RCC_CFGR_MCO_MSICLK 0x3
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#define RCC_CFGR_MCO_HSECLK 0x4
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#define RCC_CFGR_MCO_PLLCLK 0x5
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#define RCC_CFGR_MCO_LSICLK 0x6
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#define RCC_CFGR_MCO_LSECLK 0x7
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/* PLL Output division selection */
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#define RCC_CFGR_PLLDIV_DIV2 0x1
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#define RCC_CFGR_PLLDIV_DIV3 0x2
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#define RCC_CFGR_PLLDIV_DIV4 0x3
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/* PLLMUL: PLL multiplication factor */
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#define RCC_CFGR_PLLMUL_MUL3 0x0
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#define RCC_CFGR_PLLMUL_MUL4 0x1
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#define RCC_CFGR_PLLMUL_MUL6 0x2
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#define RCC_CFGR_PLLMUL_MUL8 0x3
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#define RCC_CFGR_PLLMUL_MUL12 0x4
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#define RCC_CFGR_PLLMUL_MUL16 0x5
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#define RCC_CFGR_PLLMUL_MUL24 0x6
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#define RCC_CFGR_PLLMUL_MUL32 0x7
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#define RCC_CFGR_PLLMUL_MUL48 0x8
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/* PLLSRC: PLL entry clock source */
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#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
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#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
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#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
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#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
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#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
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#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
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#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
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#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
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#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
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#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
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/* HPRE: AHB prescaler */
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#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
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#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
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#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
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#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
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#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
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#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
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#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
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#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
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#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
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#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
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#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
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#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
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/* SW: System clock switch */
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#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0
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#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
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#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
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#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
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/* --- RCC_CIR values ------------------------------------------------------ */
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/* Clock security system interrupt clear bit */
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#define RCC_CIR_CSSC (1 << 23)
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/* OSC ready interrupt clear bits */
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#define RCC_CIR_MSIRDYC (1 << 21)
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#define RCC_CIR_PLLRDYC (1 << 20)
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#define RCC_CIR_HSERDYC (1 << 19)
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#define RCC_CIR_HSIRDYC (1 << 18)
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#define RCC_CIR_LSERDYC (1 << 17)
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#define RCC_CIR_LSIRDYC (1 << 16)
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/* OSC ready interrupt enable bits */
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#define RCC_CIR_MSIRDYIE (1 << 13)
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#define RCC_CIR_PLLRDYIE (1 << 12)
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#define RCC_CIR_HSERDYIE (1 << 11)
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#define RCC_CIR_HSIRDYIE (1 << 10)
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#define RCC_CIR_LSERDYIE (1 << 9)
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#define RCC_CIR_LSIRDYIE (1 << 8)
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/* Clock security system interrupt flag bit */
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#define RCC_CIR_CSSF (1 << 7)
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/* OSC ready interrupt flag bits */
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#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */
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#define RCC_CIR_PLLRDYF (1 << 4)
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#define RCC_CIR_HSERDYF (1 << 3)
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#define RCC_CIR_HSIRDYF (1 << 2)
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#define RCC_CIR_LSERDYF (1 << 1)
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#define RCC_CIR_LSIRDYF (1 << 0)
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/* --- RCC_AHBRSTR values ------------------------------------------------- */
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#define RCC_AHBRSTR_DMA1RST (1 << 24)
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#define RCC_AHBRSTR_FLITFRST (1 << 15)
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#define RCC_AHBRSTR_CRCRST (1 << 12)
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#define RCC_AHBRSTR_GPIOHRST (1 << 5)
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#define RCC_AHBRSTR_GPIOERST (1 << 4)
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#define RCC_AHBRSTR_GPIODRST (1 << 3)
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#define RCC_AHBRSTR_GPIOCRST (1 << 2)
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#define RCC_AHBRSTR_GPIOBRST (1 << 1)
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#define RCC_AHBRSTR_GPIOARST (1 << 0)
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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#define RCC_APB2RSTR_USART1RST (1 << 14)
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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#define RCC_APB2RSTR_ADC1RST (1 << 9)
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#define RCC_APB2RSTR_TIM11RST (1 << 4)
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#define RCC_APB2RSTR_TIM10RST (1 << 3)
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#define RCC_APB2RSTR_TIM9RST (1 << 2)
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#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define RCC_APB1RSTR_COMPRST (1 << 31)
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_USART3RST (1 << 18)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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#define RCC_APB1RSTR_SPI2RST (1 << 14)
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#define RCC_APB1RSTR_WWDGRST (1 << 11)
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#define RCC_APB1RSTR_LCDRST (1 << 9)
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#define RCC_APB1RSTR_TIM7RST (1 << 5)
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#define RCC_APB1RSTR_TIM6RST (1 << 4)
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#define RCC_APB1RSTR_TIM4RST (1 << 2)
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#define RCC_APB1RSTR_TIM3RST (1 << 1)
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#define RCC_APB1RSTR_TIM2RST (1 << 0)
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/* --- RCC_AHBENR values --------------------------------------------------- */
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/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
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@ingroup STM32L1xx_rcc_defines
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@{*/
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#define RCC_AHBENR_DMA1EN (1 << 24)
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#define RCC_AHBENR_FLITFEN (1 << 15)
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#define RCC_AHBENR_CRCEN (1 << 12)
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#define RCC_AHBENR_GPIOHEN (1 << 5)
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#define RCC_AHBENR_GPIOEEN (1 << 4)
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#define RCC_AHBENR_GPIODEN (1 << 3)
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#define RCC_AHBENR_GPIOCEN (1 << 2)
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#define RCC_AHBENR_GPIOBEN (1 << 1)
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#define RCC_AHBENR_GPIOAEN (1 << 0)
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/*@}*/
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
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@ingroup STM32L1xx_rcc_defines
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@{*/
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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#define RCC_APB2ENR_ADC1EN (1 << 9)
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#define RCC_APB2ENR_TIM11EN (1 << 4)
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#define RCC_APB2ENR_TIM10EN (1 << 3)
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#define RCC_APB2ENR_TIM9EN (1 << 2)
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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/*@}*/
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
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@ingroup STM32L1xx_rcc_defines
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@{*/
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#define RCC_APB1ENR_COMPEN (1 << 31)
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#define RCC_APB1ENR_DACEN (1 << 29)
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_USART3EN (1 << 18)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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#define RCC_APB1ENR_SPI2EN (1 << 14)
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#define RCC_APB1ENR_WWDGEN (1 << 11)
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#define RCC_APB1ENR_LCDEN (1 << 9)
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#define RCC_APB1ENR_TIM7EN (1 << 5)
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#define RCC_APB1ENR_TIM6EN (1 << 4)
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#define RCC_APB1ENR_TIM4EN (1 << 2)
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#define RCC_APB1ENR_TIM3EN (1 << 1)
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#define RCC_APB1ENR_TIM2EN (1 << 0)
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/*@}*/
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/* --- RCC_AHBLPENR -------------------------------------------------------- */
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#define RCC_AHBLPENR_DMA1LPEN (1 << 24)
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#define RCC_AHBLPENR_SRAMLPEN (1 << 16)
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#define RCC_AHBLPENR_FLITFLPEN (1 << 15)
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#define RCC_AHBLPENR_CRCLPEN (1 << 12)
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#define RCC_AHBLPENR_GPIOHLPEN (1 << 5)
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#define RCC_AHBLPENR_GPIOELPEN (1 << 4)
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#define RCC_AHBLPENR_GPIODLPEN (1 << 3)
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#define RCC_AHBLPENR_GPIOCLPEN (1 << 2)
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#define RCC_AHBLPENR_GPIOBLPEN (1 << 1)
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#define RCC_AHBLPENR_GPIOALPEN (1 << 0)
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#define RCC_APB2LPENR_USART1LPEN (1 << 14)
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#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
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#define RCC_APB2LPENR_ADC1LPEN (1 << 9)
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#define RCC_APB2LPENR_TIM11LPEN (1 << 4)
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#define RCC_APB2LPENR_TIM10LPEN (1 << 3)
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#define RCC_APB2LPENR_TIM9LPEN (1 << 2)
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#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0)
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#define RCC_APB1LPENR_COMPLPEN (1 << 31)
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#define RCC_APB1LPENR_DACLPEN (1 << 29)
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#define RCC_APB1LPENR_PWRLPEN (1 << 28)
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#define RCC_APB1LPENR_USBLPEN (1 << 23)
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#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
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#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
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#define RCC_APB1LPENR_USART3LPEN (1 << 18)
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#define RCC_APB1LPENR_USART2LPEN (1 << 17)
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#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
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#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
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#define RCC_APB1LPENR_LCDLPEN (1 << 9)
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#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
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#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
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#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
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#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
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#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
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/* --- RCC_CSR values ------------------------------------------------------ */
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#define RCC_CSR_LPWRRSTF (1 << 31)
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#define RCC_CSR_WWDGRSTF (1 << 30)
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#define RCC_CSR_IWDGRSTF (1 << 29)
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#define RCC_CSR_SFTRSTF (1 << 28)
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#define RCC_CSR_PORRSTF (1 << 27)
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#define RCC_CSR_PINRSTF (1 << 26)
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#define RCC_CSR_OBLRSTF (1 << 25)
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#define RCC_CSR_RMVF (1 << 24)
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#define RCC_CSR_RTCRST (1 << 23)
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#define RCC_CSR_RTCEN (1 << 22)
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/* RTCSEL[1:0] */
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#define RCC_CSR_LSEBYP (1 << 10)
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#define RCC_CSR_LSERDY (1 << 9)
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#define RCC_CSR_LSEON (1 << 8)
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/* --- Variable definitions ------------------------------------------------ */
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extern u32 rcc_ppre1_frequency;
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extern u32 rcc_ppre2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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PLL, HSE, HSI, MSI, LSE, LSI
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} osc_t;
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void rcc_osc_ready_int_clear(osc_t osc);
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void rcc_osc_ready_int_enable(osc_t osc);
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void rcc_osc_ready_int_disable(osc_t osc);
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int rcc_osc_ready_int_flag(osc_t osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_wait_for_osc_ready(osc_t osc);
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void rcc_osc_on(osc_t osc);
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void rcc_osc_off(osc_t osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_osc_bypass_enable(osc_t osc);
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void rcc_osc_bypass_disable(osc_t osc);
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
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void rcc_set_sysclk_source(u32 clk);
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void rcc_set_pll_multiplication_factor(u32 mul);
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void rcc_set_pll_source(u32 pllsrc);
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void rcc_set_pllxtpre(u32 pllxtpre);
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void rcc_set_adcpre(u32 adcpre);
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void rcc_set_ppre2(u32 ppre2);
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void rcc_set_ppre1(u32 ppre1);
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void rcc_set_hpre(u32 hpre);
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void rcc_set_usbpre(u32 usbpre);
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u32 rcc_get_system_clock_source(int i);
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void rcc_clock_setup_in_hsi_out_64mhz(void);
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void rcc_clock_setup_in_hsi_out_48mhz(void);
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/**
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* Maximum speed possible for F100 (Value Line) on HSI
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*/
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void rcc_clock_setup_in_hsi_out_24mhz(void);
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void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
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void rcc_backupdomain_reset(void);
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#endif
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